2014-12-31 04:32:06 +00:00
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/******************************************************************************
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* Copyright 2013-2014 Espressif Systems (Wuxi)
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*
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* FileName: uart.c
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*
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* Description: Two UART mode configration and interrupt handler.
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* Check your hardware connection while use this mode.
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*
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* Modification history:
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* 2014/3/12, v1.0 create this file.
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*******************************************************************************/
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#include "ets_sys.h"
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#include "osapi.h"
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#include "driver/uart.h"
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#include "osapi.h"
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#include "driver/uart_register.h"
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2016-09-09 15:37:03 +00:00
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#include "mem.h"
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2014-12-31 04:32:06 +00:00
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// UartDev is defined and initialized in rom code.
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extern UartDevice UartDev;
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LOCAL void uart0_rx_intr_handler(void *para);
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LOCAL void ICACHE_FLASH_ATTR
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uart_config(uint8 uart_no)
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{
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if (uart_no == UART1)
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{
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_U1TXD_BK);
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}
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else
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{
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/* rcv_buff size if 0x100 */
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ETS_UART_INTR_ATTACH(uart0_rx_intr_handler, &(UartDev.rcv_buff));
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PIN_PULLUP_DIS(PERIPHS_IO_MUX_U0TXD_U);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_U0RTS);
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}
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uart_div_modify(uart_no, UART_CLK_FREQ / (UartDev.baut_rate));
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WRITE_PERI_REG(UART_CONF0(uart_no), UartDev.exist_parity
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| UartDev.parity
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| (UartDev.stop_bits << UART_STOP_BIT_NUM_S)
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| (UartDev.data_bits << UART_BIT_NUM_S));
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//clear rx and tx fifo,not ready
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SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST);
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CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST);
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2016-09-09 15:37:03 +00:00
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2014-12-31 04:32:06 +00:00
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if (uart_no == UART0)
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{
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//set rx fifo trigger
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WRITE_PERI_REG(UART_CONF1(uart_no),
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((0x7F & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S) |
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//((128 & UART_RX_FLOW_THRHD) << UART_RX_FLOW_THRHD_S) |
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//UART_RX_FLOW_EN |
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((0x0F & UART_TXFIFO_EMPTY_THRHD) << UART_TXFIFO_EMPTY_THRHD_S));
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//UART_RX_TOUT_EN);
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SET_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_RXFIFO_TOUT_INT_ENA | UART_FRM_ERR_INT_ENA);
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2014-12-31 04:32:06 +00:00
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}
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else
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{
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WRITE_PERI_REG(UART_CONF1(uart_no),
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((UartDev.rcv_buff.TrigLvl & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S));
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}
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//clear all interrupt
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WRITE_PERI_REG(UART_INT_CLR(uart_no), 0xffff);
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//enable rx_interrupt
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SET_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_RXFIFO_FULL_INT_ENA | UART_RXFIFO_OVF_INT_ENA);
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2014-12-31 04:32:06 +00:00
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}
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LOCAL STATUS
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uart_tx_one_char(uint8 uart, uint8 TxChar)
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{
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while (true)
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{
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uint32 fifo_cnt = READ_PERI_REG(UART_STATUS(uart)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S);
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if ((fifo_cnt >> UART_TXFIFO_CNT_S & UART_TXFIFO_CNT) < 126) {
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break;
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}
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}
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WRITE_PERI_REG(UART_FIFO(uart) , TxChar);
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return OK;
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2014-12-31 04:32:06 +00:00
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}
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void ICACHE_FLASH_ATTR
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uart1_write_char(char c)
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{
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if (c == '\n')
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{
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uart_tx_one_char(UART1, '\r');
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uart_tx_one_char(UART1, '\n');
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}
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else if (c == '\r')
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{
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}
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else
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{
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uart_tx_one_char(UART1, c);
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}
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}
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void ICACHE_FLASH_ATTR
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uart0_write_char(char c)
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{
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if (c == '\n')
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{
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uart_tx_one_char(UART0, '\r');
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uart_tx_one_char(UART0, '\n');
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}
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else if (c == '\r')
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{
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}
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else
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{
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uart_tx_one_char(UART0, c);
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}
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}
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2014-12-31 04:32:06 +00:00
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void ICACHE_FLASH_ATTR
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uart0_tx_buffer(uint8 *buf, uint16 len)
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{
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uint16 i;
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for (i = 0; i < len; i++)
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{
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uart_tx_one_char(UART0, buf[i]);
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}
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}
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void ICACHE_FLASH_ATTR
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uart0_sendStr(const char *str)
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{
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while (*str)
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{
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uart_tx_one_char(UART0, *str++);
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}
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2014-12-31 04:32:06 +00:00
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}
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LOCAL void
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uart0_rx_intr_handler(void *para)
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{
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uint8 RcvChar;
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uint8 uart_no = UART0;//UartDev.buff_uart_no;
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/* Is the frame Error interrupt set ? */
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if (UART_FRM_ERR_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_FRM_ERR_INT_ST))
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{
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//INFO("FRM_ERR\r\n");
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WRITE_PERI_REG(UART_INT_CLR(uart_no), UART_FRM_ERR_INT_CLR);
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}
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else if (UART_RXFIFO_FULL_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_RXFIFO_FULL_INT_ST)) /*fifo full*/
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{
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CLEAR_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_RXFIFO_FULL_INT_ENA | UART_RXFIFO_TOUT_INT_ENA);
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WRITE_PERI_REG(UART_INT_CLR(UART0), UART_RXFIFO_FULL_INT_CLR);
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//INFO("Fifo full: %d\n", (READ_PERI_REG(UART_STATUS(UART0))>>UART_RXFIFO_CNT_S)&UART_RXFIFO_CNT);
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while ((READ_PERI_REG(UART_STATUS(UART0)) >> UART_RXFIFO_CNT_S)&UART_RXFIFO_CNT)
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{
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//TODO: MCU_Input( READ_PERI_REG(UART_FIFO(UART0)) & 0xFF );
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}
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WRITE_PERI_REG(UART_INT_CLR(UART0), UART_RXFIFO_FULL_INT_CLR);
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2014-12-31 04:32:06 +00:00
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2016-09-09 15:37:03 +00:00
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SET_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_RXFIFO_FULL_INT_ENA | UART_RXFIFO_TOUT_INT_ENA);
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}
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else if (UART_RXFIFO_TOUT_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_RXFIFO_TOUT_INT_ST))
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{
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2016-09-09 15:37:03 +00:00
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CLEAR_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_RXFIFO_FULL_INT_ENA | UART_RXFIFO_TOUT_INT_ENA);
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WRITE_PERI_REG(UART_INT_CLR(UART0), UART_RXFIFO_TOUT_INT_CLR);
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//INFO("Fifo timeout: %d\n", (READ_PERI_REG(UART_STATUS(UART0))>>UART_RXFIFO_CNT_S)&UART_RXFIFO_CNT);
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while ((READ_PERI_REG(UART_STATUS(UART0)) >> UART_RXFIFO_CNT_S)&UART_RXFIFO_CNT)
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{
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//MCU_Input( READ_PERI_REG(UART_FIFO(UART0)) & 0xFF );
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}
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SET_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_RXFIFO_FULL_INT_ENA | UART_RXFIFO_TOUT_INT_ENA);
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2014-12-31 04:32:06 +00:00
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2016-09-09 15:37:03 +00:00
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}
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else if (UART_RXFIFO_OVF_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_RXFIFO_OVF_INT_ST))
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{
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//INFO("FIFO FULL\n");
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WRITE_PERI_REG(UART_INT_CLR(uart_no), UART_RXFIFO_OVF_INT_CLR);
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}
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else if (UART_TXFIFO_EMPTY_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_TXFIFO_EMPTY_INT_ST)) {
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//INFO("TX EMPTY\n");
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WRITE_PERI_REG(UART_INT_CLR(uart_no), UART_TXFIFO_EMPTY_INT_CLR);
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CLEAR_PERI_REG_MASK(UART_INT_ENA(UART0), UART_TXFIFO_EMPTY_INT_ENA);
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2014-12-31 04:32:06 +00:00
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}
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2016-09-09 15:37:03 +00:00
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ETS_UART_INTR_ENABLE();
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2014-12-31 04:32:06 +00:00
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}
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void ICACHE_FLASH_ATTR
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uart_init(UartBautRate uart0_br, UartBautRate uart1_br)
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{
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UartDev.baut_rate = uart0_br;
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uart_config(UART0);
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UartDev.baut_rate = uart1_br;
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uart_config(UART1);
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ETS_UART_INTR_ENABLE();
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// install uart1 putc callback
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os_install_putc1((void *)uart0_write_char);
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}
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void ICACHE_FLASH_ATTR
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uart_reattach()
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{
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2016-09-09 15:37:03 +00:00
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uart_init(BIT_RATE_115200, BIT_RATE_115200);
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2014-12-31 04:32:06 +00:00
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}
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