kopia lustrzana https://github.com/espressif/esp-idf
17 KiB
17 KiB
| 1 | # field_name, | efuse_block, | bit_start, | bit_count, |comment # |
|---|---|
| 2 | # | (EFUSE_BLK0 | (0..255) | (1..256) | # |
| 3 | # | EFUSE_BLK1 | | | # |
| 4 | # | ... | | | # |
| 5 | # | EFUSE_BLK10)| | | # |
| 6 | ########################################################################## |
| 7 | # !!!!!!!!!!! # |
| 8 | # this will generate new source files, next rebuild all the sources. |
| 9 | # !!!!!!!!!!! # |
| 10 | # EFUSE_RD_REPEAT_DATA BLOCK # |
| 11 | ############################## |
| 12 | # EFUSE_RD_WR_DIS_REG # |
| 13 | WR_DIS, EFUSE_BLK0, 0, 32, Write protection |
| 14 | WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2 |
| 15 | WR_DIS.GROUP_1, EFUSE_BLK0, 2, 1, Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG HARD_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT |
| 16 | WR_DIS.GROUP_2, EFUSE_BLK0, 3, 1, Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL |
| 17 | WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, Write protection for SPI_BOOT_CRYPT_CNT |
| 18 | WR_DIS.SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0, 5, 1, Write protection for SECURE_BOOT_KEY_REVOKE0 |
| 19 | WR_DIS.SECURE_BOOT_KEY_REVOKE1,EFUSE_BLK0, 6, 1, Write protection for SECURE_BOOT_KEY_REVOKE1 |
| 20 | WR_DIS.SECURE_BOOT_KEY_REVOKE2,EFUSE_BLK0, 7, 1, Write protection for SECURE_BOOT_KEY_REVOKE2 |
| 21 | WR_DIS.KEY0_PURPOSE, EFUSE_BLK0, 8, 1, Write protection for key_purpose. KEY0 |
| 22 | WR_DIS.KEY1_PURPOSE, EFUSE_BLK0, 9, 1, Write protection for key_purpose. KEY1 |
| 23 | WR_DIS.KEY2_PURPOSE, EFUSE_BLK0, 10, 1, Write protection for key_purpose. KEY2 |
| 24 | WR_DIS.KEY3_PURPOSE, EFUSE_BLK0, 11, 1, Write protection for key_purpose. KEY3 |
| 25 | WR_DIS.KEY4_PURPOSE, EFUSE_BLK0, 12, 1, Write protection for key_purpose. KEY4 |
| 26 | WR_DIS.KEY5_PURPOSE, EFUSE_BLK0, 13, 1, Write protection for key_purpose. KEY5 |
| 27 | WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, Write protection for SECURE_BOOT_EN |
| 28 | WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,EFUSE_BLK0, 16, 1, Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE |
| 29 | WR_DIS.GROUP_3, EFUSE_BLK0, 18, 1, Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_SERIAL_JTAG_ROM_PRINT DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION |
| 30 | WR_DIS.BLK1, EFUSE_BLK0, 20, 1, Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS |
| 31 | WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, Write protection for EFUSE_BLK2. SYS_DATA_PART1 |
| 32 | WR_DIS.USER_DATA, EFUSE_BLK0, 22, 1, Write protection for EFUSE_BLK3. USER_DATA |
| 33 | WR_DIS.KEY0, EFUSE_BLK0, 23, 1, Write protection for EFUSE_BLK4. KEY0 |
| 34 | WR_DIS.KEY1, EFUSE_BLK0, 24, 1, Write protection for EFUSE_BLK5. KEY1 |
| 35 | WR_DIS.KEY2, EFUSE_BLK0, 25, 1, Write protection for EFUSE_BLK6. KEY2 |
| 36 | WR_DIS.KEY3, EFUSE_BLK0, 26, 1, Write protection for EFUSE_BLK7. KEY3 |
| 37 | WR_DIS.KEY4, EFUSE_BLK0, 27, 1, Write protection for EFUSE_BLK8. KEY4 |
| 38 | WR_DIS.KEY5, EFUSE_BLK0, 28, 1, Write protection for EFUSE_BLK9. KEY5 |
| 39 | WR_DIS.SYS_DATA_PART2, EFUSE_BLK0, 29, 1, Write protection for EFUSE_BLK10. SYS_DATA_PART2 |
| 40 | WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, Write protection for USB_EXCHG_PINS |
| 41 | # EFUSE_RD_REPEAT_DATA0_REG # |
| 42 | RD_DIS, EFUSE_BLK0, 32, 7, Read protection |
| 43 | RD_DIS.KEY0, EFUSE_BLK0, 32, 1, Read protection for EFUSE_BLK4. KEY0 |
| 44 | RD_DIS.KEY1, EFUSE_BLK0, 33, 1, Read protection for EFUSE_BLK5. KEY1 |
| 45 | RD_DIS.KEY2, EFUSE_BLK0, 34, 1, Read protection for EFUSE_BLK6. KEY2 |
| 46 | RD_DIS.KEY3, EFUSE_BLK0, 35, 1, Read protection for EFUSE_BLK7. KEY3 |
| 47 | RD_DIS.KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4 |
| 48 | RD_DIS.KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5 |
| 49 | RD_DIS.SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2 |
| 50 | DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache |
| 51 | DIS_DCACHE, EFUSE_BLK0, 41, 1, Disable Dcace |
| 52 | DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode include boot_mode 0 1 2 3 6 7 |
| 53 | DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 43, 1, Disable Dcache in download mode include boot_mode 0 1 2 3 6 7 |
| 54 | DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, Disable force chip go to download mode function |
| 55 | DIS_USB, EFUSE_BLK0, 45, 1, Disable USB function |
| 56 | DIS_CAN, EFUSE_BLK0, 46, 1, Disable CAN function |
| 57 | DIS_APP_CPU, EFUSE_BLK0, 47, 1, Disables APP CPU |
| 58 | SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, Software disables JTAG by programming odd number of 1 bit(s). JTAG can be re-enabled via HMAC peripheral |
| 59 | HARD_DIS_JTAG, EFUSE_BLK0, 51, 1, Hardware disable jtag permanently disable jtag function |
| 60 | DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, Disable flash encrypt function, other than SPI/Legacy SPI boot mode |
| 61 | USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, Exchange D+ D- pins |
| 62 | USB_EXT_PHY_ENABLE, EFUSE_BLK0, 58, 1, Enable external PHY |
| 63 | BTLC_GPIO_ENABLE, EFUSE_BLK0, 59, 2, Enables BTLC GPIO |
| 64 | # EFUSE_RD_REPEAT_DATA1_REG # |
| 65 | VDD_SPI_XPD, EFUSE_BLK0, 68, 1, VDD_SPI regulator power up |
| 66 | VDD_SPI_TIEH, EFUSE_BLK0, 69, 1, VDD_SPI regulator tie high to vdda |
| 67 | VDD_SPI_FORCE, EFUSE_BLK0, 70, 1, Force using eFuse configuration of VDD_SPI |
| 68 | WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, Select RTC WDT time out threshold |
| 69 | SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable |
| 70 | SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, Enable revoke first secure boot key |
| 71 | SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, Enable revoke second secure boot key |
| 72 | SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, Enable revoke third secure boot key |
| 73 | KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, Key0 purpose |
| 74 | KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, Key1 purpose |
| 75 | # EFUSE_RD_REPEAT_DATA2_REG # |
| 76 | KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, Key2 purpose |
| 77 | KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, Key3 purpose |
| 78 | KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, Key4 purpose |
| 79 | KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, Key5 purpose |
| 80 | SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, Secure boot enable |
| 81 | SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, Enable aggressive secure boot revoke |
| 82 | DIS_USB_JTAG, EFUSE_BLK0, 118, 1, Set to disable usb_serial_jtag-to-jtag function |
| 83 | DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 119, 1, Set to disable usb_serial_jtag module |
| 84 | STRAP_JTAG_SEL, EFUSE_BLK0, 120, 1, Enable selection between usb_to_jtag or pad_to_jtag through gpio10 |
| 85 | USB_PHY_SEL, EFUSE_BLK0, 121, 1, Select internal/external PHY for USB OTG and usb_serial_jtag |
| 86 | FLASH_TPUW, EFUSE_BLK0, 124, 4, Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms |
| 87 | # EFUSE_RD_REPEAT_DATA3_REG # |
| 88 | DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 |
| 89 | DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, Disable direct boot mode |
| 90 | DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, Disable usb serial jtag print during rom boot |
| 91 | FLASH_ECC_MODE, EFUSE_BLK0, 131, 1, Configures the ECC mode for SPI flash. 0:16-byte to 18-byte mode. 1:16-byte to 17-byte mode |
| 92 | DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,EFUSE_BLK0, 132, 1, Set this bit to disable download through USB-Serial-JTAG |
| 93 | ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, Enable security download mode |
| 94 | UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print. |
| 95 | PIN_POWER_SELECTION, EFUSE_BLK0, 136, 1, GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI. |
| 96 | FLASH_TYPE, EFUSE_BLK0, 137, 1, Connected Flash interface type. 0: 4 data line. 1: 8 data line |
| 97 | FLASH_PAGE_SIZE, EFUSE_BLK0, 138, 2, Sets the size of flash page |
| 98 | FLASH_ECC_EN, EFUSE_BLK0, 140, 1, Enables ECC in Flash boot mode |
| 99 | FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, Force ROM code to send a resume command during SPI boot |
| 100 | SECURE_VERSION, EFUSE_BLK0, 142, 16, Secure version for anti-rollback |
| 101 | DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 159, 1, Set this bit to disable download through USB-OTG |
| 102 | # EFUSE_RD_REPEAT_DATA4_REG # |
| 103 | DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major |
| 104 | DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, Disables check of blk version major |
| 105 | # MAC_SPI_8M_SYS BLOCK# |
| 106 | ####################### |
| 107 | MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0] |
| 108 | , EFUSE_BLK1, 32, 8, Factory MAC addr [1] |
| 109 | , EFUSE_BLK1, 24, 8, Factory MAC addr [2] |
| 110 | , EFUSE_BLK1, 16, 8, Factory MAC addr [3] |
| 111 | , EFUSE_BLK1, 8, 8, Factory MAC addr [4] |
| 112 | , EFUSE_BLK1, 0, 8, Factory MAC addr [5] |
| 113 | SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK |
| 114 | SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1) |
| 115 | SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0) |
| 116 | SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS |
| 117 | SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3) |
| 118 | SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2) |
| 119 | SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS |
| 120 | SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4 |
| 121 | # RD_MAC_SPI_SYS_3 |
| 122 | SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5 |
| 123 | SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6 |
| 124 | SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7 |
| 125 | WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 3, WAFER_VERSION_MINOR least significant bits |
| 126 | , EFUSE_BLK1, 183, 1, WAFER_VERSION_MINOR most significant bit |
| 127 | # WAFER_VERSION_MINOR most significant bit is from RD_MAC_SPI_SYS_5 |
| 128 | PKG_VERSION, EFUSE_BLK1, 117, 3, Package version |
| 129 | BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, BLK_VERSION_MINOR |
| 130 | # RD_MAC_SPI_SYS_5 |
| 131 | # WAFER_VERSION_MINOR most significant bit |
| 132 | WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, WAFER_VERSION_MAJOR |
| 133 | ADC2_CAL_VOL_ATTEN3, EFUSE_BLK1, 186, 6, ADC2 calibration voltage at atten3 |
| 134 | # SYS_DATA_PART1 BLOCK# - System configuration |
| 135 | ####################### |
| 136 | # RD_SYS_PART1_DATA0 |
| 137 | OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID |
| 138 | # RD_SYS_PART1_DATA4 |
| 139 | BLK_VERSION_MAJOR, EFUSE_BLK2, 128, 2, BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware |
| 140 | TEMP_CALIB, EFUSE_BLK2, 132, 9, Temperature calibration data |
| 141 | OCODE, EFUSE_BLK2, 141, 8, ADC OCode |
| 142 | ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 149, 8, ADC1 init code at atten0 |
| 143 | ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 157, 6, ADC1 init code at atten1 |
| 144 | # RD_SYS_PART1_DATA5 |
| 145 | ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 163, 6, ADC1 init code at atten2 |
| 146 | ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 169, 6, ADC1 init code at atten3 |
| 147 | ADC2_INIT_CODE_ATTEN0, EFUSE_BLK2, 175, 8, ADC2 init code at atten0 |
| 148 | ADC2_INIT_CODE_ATTEN1, EFUSE_BLK2, 183, 6, ADC2 init code at atten1 |
| 149 | ADC2_INIT_CODE_ATTEN2, EFUSE_BLK2, 189, 6, ADC2 init code at atten2 |
| 150 | ADC2_INIT_CODE_ATTEN3, EFUSE_BLK2, 195, 6, ADC2 init code at atten3 |
| 151 | ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 201, 8, ADC1 calibration voltage at atten0 |
| 152 | ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 209, 8, ADC1 calibration voltage at atten1 |
| 153 | ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 217, 8, ADC1 calibration voltage at atten2 |
| 154 | ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 225, 8, ADC1 calibration voltage at atten3 |
| 155 | ADC2_CAL_VOL_ATTEN0, EFUSE_BLK2, 233, 8, ADC2 calibration voltage at atten0 |
| 156 | ADC2_CAL_VOL_ATTEN1, EFUSE_BLK2, 241, 7, ADC2 calibration voltage at atten1 |
| 157 | ADC2_CAL_VOL_ATTEN2, EFUSE_BLK2, 248, 7, ADC2 calibration voltage at atten2 |
| 158 | ################ |
| 159 | USER_DATA, EFUSE_BLK3, 0, 256, User data |
| 160 | USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, Custom MAC |
| 161 | ################ |
| 162 | KEY0, EFUSE_BLK4, 0, 256, Key0 or user data |
| 163 | KEY1, EFUSE_BLK5, 0, 256, Key1 or user data |
| 164 | KEY2, EFUSE_BLK6, 0, 256, Key2 or user data |
| 165 | KEY3, EFUSE_BLK7, 0, 256, Key3 or user data |
| 166 | KEY4, EFUSE_BLK8, 0, 256, Key4 or user data |
| 167 | KEY5, EFUSE_BLK9, 0, 256, Key5 or user data |
| 168 | SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration |
| 169 | # AUTO CONFIG DIG&RTC DBIAS# |
| 170 | ################ |
| 171 | K_RTC_LDO, EFUSE_BLK1, 141, 7, BLOCK1 K_RTC_LDO |
| 172 | K_DIG_LDO, EFUSE_BLK1, 148, 7, BLOCK1 K_DIG_LDO |
| 173 | V_RTC_DBIAS20, EFUSE_BLK1, 155, 8, BLOCK1 voltage of rtc dbias20 |
| 174 | V_DIG_DBIAS20, EFUSE_BLK1, 163, 8, BLOCK1 voltage of digital dbias20 |
| 175 | DIG_DBIAS_HVT, EFUSE_BLK1, 171, 5, BLOCK1 digital dbias when hvt |