esp-idf

Historia

Darian 105f6dd22c Merge branch 'refactor/soc_caps_multiple_cores' into 'master' change(docs): Update multicore tags to SOC_CPU_HAS_MULTIPLE_CORES See merge request espressif/esp-idf!27523		2023-12-05 18:20:21 +08:00
..
esp32	Merge branch 'refactor/soc_caps_multiple_cores' into 'master'	2023-12-05 18:20:21 +08:00
esp32c2	change(fpga): added bypass rng configuration	2023-12-05 11:38:35 +08:00
esp32c3	change(fpga): added bypass rng configuration	2023-12-05 11:38:35 +08:00
esp32c5	…
esp32c6	change(fpga): added bypass rng configuration	2023-12-05 11:38:35 +08:00
esp32h2	change(fpga): added bypass rng configuration	2023-12-05 11:38:35 +08:00
esp32p4	Merge branch 'refactor/soc_caps_multiple_cores' into 'master'	2023-12-05 18:20:21 +08:00
esp32s2	change(fpga): added bypass rng configuration	2023-12-05 11:38:35 +08:00
esp32s3	Merge branch 'refactor/soc_caps_multiple_cores' into 'master'	2023-12-05 18:20:21 +08:00
include/soc	…
linux/include/soc	…
CMakeLists.txt	…
Kconfig	…
README.md	…
dport_access_common.c	…
linker.lf	…
lldesc.c	…

README.md

`soc`

The soc component provides hardware description for targets supported by ESP-IDF.

- `xxx_reg.h`   - defines registers related to the hardware
- `xxx_struct.h` - hardware description in C `struct`
- `xxx_channel.h` - definitions for hardware with multiple channels
- `xxx_caps.h`  - features/capabilities of the hardware
- `xxx_pins.h`  - pin definitions
- `xxx_periph.h/*.c`  - includes all headers related to a peripheral; declaration and definition of IO mapping for that hardware