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2160 Commity (83e18bd3bd8f3abea820d4a9b7190beb13cb94f0)

Autor SHA1 Wiadomość Data
Darian 105f6dd22c Merge branch 'refactor/soc_caps_multiple_cores' into 'master' 
change(docs): Update multicore tags to SOC_CPU_HAS_MULTIPLE_CORES

See merge request espressif/esp-idf!27523
 2023-12-05 18:20:21 +08:00
Armando 2c32bd209a change(fpga): added bypass rng configuration 2023-12-05 11:38:35 +08:00
Darian Leung 5697f260fe change(soc): Add SOC_HP_CPU_HAS_MULTIPLE_CORES 
This commit adds a the SOC_HP_CPU_HAS_MULTIPLE_CORES convenience macro to
soc_caps.h. This is a convenience boolean cap to represent whether or not the
target has multiple cores, and is intended to be used when writing docs for
multiple targets.
 2023-12-05 10:56:22 +08:00
Kevin (Lao Kaiyao) 03414a1550 Merge branch 'feature/add_esp32c5_beta3_soc_header_files_part3' into 'master' 
feat(esp32c5): add struct name and reformat struct headers (stage 2/8, part3)

See merge request espressif/esp-idf!27521
 2023-12-02 21:49:31 +08:00
Darian cc34c4fc08 Merge branch 'contrib/github_pr_12481' into 'master' 
Many places in the ESP_SYSTEM are using CONFIG_FREERTOS_UNICORE instead of CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE (GitHub PR)

Closes IDFGH-11333

See merge request espressif/esp-idf!27435
 2023-12-01 19:33:19 +08:00
laokaiyao 40bce13348 feat(esp32c5): update reg headers for multiple instances module (part3) 2023-12-01 19:04:55 +08:00
laokaiyao 9b31979107 feat(esp32c5): add struct name and reformat struct headers (part3) 2023-12-01 19:04:46 +08:00
morris 2d4a6748a3 Merge branch 'feature/sdm_driver_esp32p4' into 'master' 
esp_driver_sdm driver support on esp32p4

Closes IDF-7551

See merge request espressif/esp-idf!27543
 2023-12-01 17:21:04 +08:00
Mahavir Jain 0df6afadef Merge branch 'fix/esp32s3_soc_drom_high_addr' into 'master' 
fix(soc): esp32s3/Fix the DROM_HIGH_ADDR

See merge request espressif/esp-idf!27015
 2023-12-01 12:41:59 +08:00
morris 846751216b feat(sdm): add driver support for esp32p4 2023-12-01 10:03:09 +08:00
Kevin (Lao Kaiyao) 15803e14e9 Merge branch 'feature/add_esp32c5_beta3_soc_header_files' into 'master' 
feat(esp32c5): add esp32c5 soc header files (stage 2, part 1)

See merge request espressif/esp-idf!27492
 2023-11-30 15:07:04 +08:00
Kevin (Lao Kaiyao) 11461aff62 Merge branch 'feature/add_esp32c5_beta3_soc_header_files_part2' into 'master' 
feat(esp32c5): add esp32c5-beta3 soc header files (stage2, part2)

See merge request espressif/esp-idf!27500
 2023-11-30 14:35:54 +08:00
Marius Vikhammer ae4be8eb03 Merge branch 'feature/p4_lp_core' into 'master' 
feat(ulp/lp_core): Added basic support for building and running a LP-Core app on ESP32P4

Closes IDF-7534

See merge request espressif/esp-idf!26869
 2023-11-30 09:35:49 +08:00
laokaiyao d87e007c66 feat(esp32c5): add esp32c5-beta3 soc header files (part1) 2023-11-29 20:53:33 +08:00
laokaiyao 87f7d2edc4 feat(esp32c5): add esp32c5-beta3 soc header files (part2) 2023-11-29 20:48:52 +08:00
Marius Vikhammer 0c067fcb05 feat(ulp/lp_core): Added basic support for building and running a LP-Core app on ESP32P4 2023-11-29 10:50:40 +08:00
laokaiyao bb0879b3f8 feat(esp32c5): introduce target esp32c5 2023-11-28 16:14:17 +08:00
fl0wl0w d149c1b26f Use configuration option instead of in components not related to FreeRTOS 
Mergeshttps://github.com/espressif/esp-idf/pull/12481
 2023-11-28 07:49:20 +00:00
morris f2751213fd feat(rmt): move the driver to a new component 2023-11-25 00:29:53 +00:00
Gao Xu b9a3dd1b37 Merge branch 'bugfix/fix_adc_cali_error_after_light_sleep_wake_on_h2' into 'master' 
adc: fix calibration error when waking up from light sleep on H2 and enable test

Closes IDF-8569

See merge request espressif/esp-idf!27242
 2023-11-24 18:25:35 +08:00
Cao Sen Miao 2c131672db fix(spi_flash): Fix ESP32S2 multi-flash test 2023-11-23 19:49:59 +08:00
Jakob Hasse 5f4865e838 Merge branch 'doc/soc_cap_tool' into 'master' 
Doc/soc cap tool

See merge request espressif/esp-idf!27154
 2023-11-23 10:47:01 +08:00
morris e86acbe556 feat(lcd): pre-support rgb and i80 lcd driver on esp32p4 
added LL functions for LCD_CAM module, only the LCD part
 2023-11-21 10:46:52 +08:00
gaoxu 4f81883ccf fix(adc): restore cali registers after light sleep wake up on H2 and enable test 2023-11-20 17:38:34 +08:00
morris 72e414105d Merge branch 'contrib/github_pr_12559' into 'master' 
fix(spi): correct macro REG_SPI_BASE(i) for all targets (GitHub PR)

Closes IDFGH-11421 and IDFGH-11424

See merge request espressif/esp-idf!27085
 2023-11-20 15:55:41 +08:00
Mahavir Jain f2a0beb579 Merge branch 'fix/esp32p4-memory-layout' into 'master' 
fix(heap): Update the heap memory layout on esp32p4 target

Closes IDF-8024, IDF-7921, and IDF-8002

See merge request espressif/esp-idf!26702
 2023-11-20 11:14:39 +08:00
Mahavir Jain 9fb38d82a3 Merge branch 'fix/rng_register_prefix_discrepency_newer_targets' into 'master' 
Fix: RNG register prefix discrepancy for ESP32C6 and ESP32H2

Closes DOC-5161 and DOC-5175

See merge request espressif/esp-idf!27212
 2023-11-20 10:53:09 +08:00
Mahavir Jain 7505667e7d Merge branch 'bugfix/esp32h2_ecdsa_hardware_k' into 'master' 
fix(esp32h2): program use_hardware_k efuse bit for ECDSA key purpose

Closes IDF-8508 and IDF-8506

See merge request espressif/esp-idf!26918
 2023-11-17 15:10:12 +08:00
Wu Zheng Hui a2f0198cd1 Merge branch 'bugfix/fix_onebyte_watchpoint_setting' into 'master' 
fix(riscv): supports 1 byte and larger than 64byte range watchpoint setting

See merge request espressif/esp-idf!27159
 2023-11-17 10:47:23 +08:00
Jakob Hasse 46e44ee154 docs(soc): improved soc caps generation documentation 2023-11-17 10:43:59 +08:00
wanlei 4dcd6d7913 fix(spi): correct some signals and dummy bits docs 2023-11-17 02:39:28 +00:00
TD-er 90eada6993 fix(spi): Correct REG_SPI_BASE(i) macro for all targets 
The existing formula can never match these registers.

Closes https://github.com/espressif/esp-idf/pull/12559
Closes https://github.com/espressif/esp-idf/pull/12562
 2023-11-17 02:39:28 +00:00
harshal.patil 91af44d6e8
fix(soc/esp32h2): Fix llperi_rng_data field discrepancy 2023-11-16 17:49:26 +05:30
harshal.patil 798059ace1
fix(soc/esp32c6): Fix llperi_rng_data field discrepancy 2023-11-16 17:49:26 +05:30
laokaiyao f35ec64a0b feat(touch): support touch driver on p4 (soc) 2023-11-16 11:13:02 +00:00
wuzhenghui 783059a592 fix(riscv): supports 1 byte and larger than 64byte range watchpoint setting 2023-11-16 18:11:57 +08:00
wuzhenghui 161bd8bfed change(soc): rename SOC_CPU_WATCHPOINT_SIZE to SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 2023-11-16 18:11:57 +08:00
Jakob Hasse bf6a904a44 Merge branch 'refactor/remove_unnecessary_mock_headers' into 'master' 
refactor(ci): removed unnecessary hal and soc mock header files

Closes IDF-8511

See merge request espressif/esp-idf!27047
 2023-11-16 09:37:21 +08:00
Jakob Hasse 7b4cd55d97 refactor(ci): removed unnecessary hal and soc mock header files 2023-11-15 12:15:08 +08:00
Mahavir Jain 94bf4710fa
fix(esp32h2): program use_hardware_k efuse bit for ECDSA key purpose 
In ESP32-H2, the ECDSA peripheral by default uses the TRNG (hardware)
generated k value but it can be overridden to software supplied k.
This can happen through by overriding the `ECDSA_SOFTWARE_SET_K` bit
in the configuration register. Even though the HAL API is not exposed
for this but still it could be achieved by direct register
programming. And for this scenario, if sufficiently random k is not
supplied by the software then it could posses a security risk.

In this change, we are unconditionally programming the efuse
`ESP_EFUSE_ECDSA_FORCE_USE_HARDWARE_K` bit during startup security
checks itself. Additionally, same is ensured in the `esp_efuse_write_key`
API as well. This always enforces the hardware k mode in the ECDSA
peripheral and ensures strongest possible security.
 2023-11-15 09:42:26 +05:30
Darian Leung a51813d9d9 refactor(soc): SOC_USB_PERIPH_NUM option 
This commit refactors SOC_USB_PERIPH_NUM as follows:

- Renamed to SOC_USB_OTG_PERIPH_NUM to avoid confusion with USB Serial JTAG
- Updated to unsigned integer "1U"
- Updated some build rules to depend on SOC_USB_OTG_SUPPORTED instead
 2023-11-14 18:48:01 +08:00
Guillaume Souchere fd2b8b5eb3 fix(heap): Update the heap memory layout on esp32p4 target 
- fix the value of SOC_ROM_STACK_START in soc.h
- Update the memory usage of ROM bootloader appendix in bootloader.ld
- Update the soc_memory_regions table to minimize the number of regions
  created after the startup stack is added back as a heap.
 2023-11-10 07:29:22 +01:00
Song Ruo Jing 365123dfaa Merge branch 'bugfix/uart_custom_console' into 'master' 
fix(console): enable to select UART1 port for console output

Closes IDF-6190

See merge request espressif/esp-idf!26642
 2023-11-10 12:31:22 +08:00
Jiang Jiang Jian 221122ebeb Merge branch 'bugfix/fix_deinit_init_wifi_scan_fail_issue' into 'master' 
fix(wifi): fix deinit init wifi scan fail issue

Closes WIFIBUG-200 and WIFI-5775

See merge request espressif/esp-idf!26957
 2023-11-10 11:05:03 +08:00
Song Ruo Jing 46d33e46ef fix(console): enable to select UART1 port for console output 
This feature was only enabled for esp32, esp32s2, esp32s3 previously.
Now, enabling this feature for all targets.
 2023-11-09 22:32:49 +08:00
Wan Lei c8c7f999ef Merge branch 'feature/esp32p4_hp_spi_slave_hd_support' into 'master' 
Feature/esp32p4 hp spi slave hd support

Closes IDF-7505

See merge request espressif/esp-idf!25974
 2023-11-09 14:42:05 +08:00
Aditya Patwardhan 7c1d9a5813 fix(soc): esp32s3/Fix the DROM_DROM_HIGH limit 
Previously the DROM_HIGH_ADDR for esp32s3 was 0x3D000000, which
    convers only 16 MB of address range. But esp32s3 supports 32 MB
    external memory. So this address should be 0x3E000000
 2023-11-09 09:58:17 +05:30
muhaidong 1ddcca6dcd fix(wifi): fix deinit init wifi scan fail issue 2023-11-09 12:05:20 +08:00
wanlei daeb71d7e4 feat(spi_slave_hd): add esp32p4 support for seg and append mode 2023-11-07 15:59:56 +08:00
Jakob Hasse af0a502f97 Merge branch 'bugfix/linux_gpio_definitions' into 'master' 
fix(driver): gpio number definitions on Linux

Closes IDFGH-11376

See merge request espressif/esp-idf!26934
 2023-11-07 12:24:29 +08:00