esp-idf/components/freertos/port
Marius Vikhammer c36dd7834f core: fix cases where riscv SP were not 16 byte aligned
RISC-V stack pointer should always be 16 byte aligned, but for some cases where
we were doing manual SP manipulation this was not always the case.
2021-02-19 11:26:21 +08:00
..
riscv core: fix cases where riscv SP were not 16 byte aligned 2021-02-19 11:26:21 +08:00
xtensa
port_common.c