esp-idf/components/freertos
Marius Vikhammer c36dd7834f core: fix cases where riscv SP were not 16 byte aligned
RISC-V stack pointer should always be 16 byte aligned, but for some cases where
we were doing manual SP manipulation this was not always the case.
2021-02-19 11:26:21 +08:00
..
include/freertos
port core: fix cases where riscv SP were not 16 byte aligned 2021-02-19 11:26:21 +08:00
test
CMakeLists.txt
FreeRTOS-openocd.c
History.txt
Kconfig
component.mk
croutine.c
event_groups.c
freertos_v8_compat.c
license.txt
linker.lf
list.c
queue.c
sdkconfig.rename
stream_buffer.c
tasks.c
timers.c