kopia lustrzana https://github.com/espressif/esp-idf
217 wiersze
8.0 KiB
C
217 wiersze
8.0 KiB
C
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <stdint.h>
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#include <stddef.h>
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#include <assert.h>
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#include "sdkconfig.h"
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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// These are the register definitions for the OpenCores Ethernet MAC.
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// See comments in esp_eth_mac_openeth.c for more details about this driver.
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// DMA buffers configuration
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#define DMA_BUF_SIZE 1600
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#define RX_BUF_COUNT CONFIG_ETH_OPENETH_DMA_RX_BUFFER_NUM
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#define TX_BUF_COUNT CONFIG_ETH_OPENETH_DMA_TX_BUFFER_NUM
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// This driver uses the interrupt source number of the internal EMAC of the ESP32 chip,
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// and uses the same register address base. This of course only works in QEMU, where
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// the OpenCores MAC is mapped to the same register base and to the same interrupt
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// source. This driver does a sanity check that it is not running on the real ESP32
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// chip, using the EMAC date register.
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#define OPENETH_INTR_SOURCE ETS_ETH_MAC_INTR_SOURCE
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#define OPENETH_BASE DR_REG_EMAC_BASE
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// OpenCores ethmac registers
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#define OPENETH_MODER_REG (OPENETH_BASE + 0x00)
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#define OPENETH_MODER_DEFAULT 0xa000
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// OPENETH_RST: reset the MAC
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#define OPENETH_RST BIT(11)
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// OPENETH_PRO: enable promiscuous mode
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#define OPENETH_PRO BIT(5)
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// OPENETH_TXEN: enable transmit
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#define OPENETH_TXEN BIT(1)
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// OPENETH_RXEN: enable receive
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#define OPENETH_RXEN BIT(0)
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#define OPENETH_INT_SOURCE_REG (OPENETH_BASE + 0x04)
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#define OPENETH_INT_MASK_REG (OPENETH_BASE + 0x08)
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// These bits apply to INT_SOURCE and INT_MASK registers:
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// OPENETH_INT_BUSY: Buffer was received and discarded due to lack of buffers
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#define OPENETH_INT_BUSY BIT(4)
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// OPENETH_INT_RXB: Frame received
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#define OPENETH_INT_RXB BIT(2)
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// OPENETH_INT_TXB: Frame transmitted
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#define OPENETH_INT_TXB BIT(0)
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// IPGT, IPGR1, IPGR2 registers are not implemented in QEMU, hence not used here
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#define OPENETH_PACKETLEN_REG (OPENETH_BASE + 0x18)
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// OPENETH_MINFL: minimum frame length
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#define OPENETH_MINFL_S 16
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#define OPENETH_MINFL_V 0xffff
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#define OPENETH_MINFL_M (OPENETH_MINFL_V << OPENETH_MINFL_S)
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// OPENETH_MAXFL: maximum frame length
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#define OPENETH_MAXFL_S 0
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#define OPENETH_MAXFL_V 0xffff
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#define OPENETH_MAXFL_M (OPENETH_MAXFL_V << OPENETH_MAXFL_S)
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// COLLCONF is not implemented in QEMU
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#define OPENETH_TX_BD_NUM_REG (OPENETH_BASE + 0x20)
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// CTRLMODER, MIIMODER are not implemented in QEMU
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#define OPENETH_MIICOMMAND_REG (OPENETH_BASE + 0x2c)
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// OPENETH_WCTRLDATA: write control data
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#define OPENETH_WCTRLDATA BIT(2)
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// OPENETH_RSTAT: read status
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#define OPENETH_RSTAT BIT(1)
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// OPENETH_SCANSTAT: scan status
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#define OPENETH_SCANSTAT BIT(0)
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#define OPENETH_MIIADDRESS_REG (OPENETH_BASE + 0x30)
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// OPENETH_RGAD: register address
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#define OPENETH_RGAD_S 8
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#define OPENETH_RGAD_V 0x1f
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#define OPENETH_RGAD_M (OPENETH_RGAD_V << OPENETH_RGAD_S)
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// OPENETH_FIAD: PHY address
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#define OPENETH_FIAD_S 0
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#define OPENETH_FIAD_V 0x1f
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#define OPENETH_FIAD_N (OPENETH_FIAD_V << OPENETH_FIAD_S)
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#define OPENETH_MIITX_DATA_REG (OPENETH_BASE + 0x34)
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#define OPENETH_MIIRX_DATA_REG (OPENETH_BASE + 0x38)
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#define OPENETH_MII_DATA_MASK 0xffff
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#define OPENETH_MIISTATUS_REG (OPENETH_BASE + 0x3c)
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// OPENETH_LINKFAIL: link is down
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#define OPENETH_LINKFAIL BIT(0)
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// OPENETH_MAC_ADDR0_REG: bytes 2-5 of the MAC address (byte 5 in LSB)
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#define OPENETH_MAC_ADDR0_REG (OPENETH_BASE + 0x40)
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// OPENETH_MAC_ADDR1_REG: bytes 0-1 of the MAC address (byte 1 in LSB)
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#define OPENETH_MAC_ADDR1_REG (OPENETH_BASE + 0x44)
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#define OPENETH_HASH0_ADR_REG (OPENETH_BASE + 0x48)
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#define OPENETH_HASH1_ADR_REG (OPENETH_BASE + 0x4c)
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// Location of the DMA descriptors
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#define OPENETH_DESC_BASE (OPENETH_BASE + 0x400)
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// Total number of (TX + RX) DMA descriptors
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#define OPENETH_DESC_CNT 128
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// Structures describing TX and RX descriptors.
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// The field names are same as in the OpenCores ethmac documentation.
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typedef struct {
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uint16_t cs: 1; //!< Carrier sense lost (flag set by HW)
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uint16_t df: 1; //!< Defer indication (flag set by HW)
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uint16_t lc: 1; //!< Late collision occured (flag set by HW)
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uint16_t rl: 1; //!< TX failed due to retransmission limit (flag set by HW)
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uint16_t rtry: 4; //!< Number of retries before the frame was sent (set by HW)
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uint16_t ur: 1; //!< Underrun status (flag set by HW)
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uint16_t rsv: 2; //!< Reserved
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uint16_t crc: 1; //!< Add CRC at the end of the packet
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uint16_t pad: 1; //!< Add padding to the end of short packets
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uint16_t wr: 1; //!< Wrap-around. 0: not the last descriptor in the table, 1: last descriptor.
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uint16_t irq: 1; //!< Generate interrupt after this descriptor is transmitted
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uint16_t rd: 1; //!< Descriptor ready. 0: descriptor owned by SW, 1: descriptor owned by HW. Cleared by HW.
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uint16_t len; //!< Number of bytes to be transmitted
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void* txpnt; //!< Pointer to the data to transmit
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} openeth_tx_desc_t;
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_Static_assert(sizeof(openeth_tx_desc_t) == 8, "incorrect size of openeth_tx_desc_t");
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typedef struct {
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uint16_t lc: 1; //!< Late collision flag
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uint16_t crc: 1; //!< RX CRC error flag
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uint16_t sf: 1; //!< Frame shorter than set in PACKETLEN register
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uint16_t tl: 1; //!< Frame longer than set in PACKETLEN register
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uint16_t dn: 1; //!< Dribble nibble (frame length not divisible by 8 bits) flag
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uint16_t is: 1; //!< Invalid symbol flag
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uint16_t or: 1; //!< Overrun flag
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uint16_t m: 1; //!< Frame received because of the promiscuous mode
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uint16_t rsv: 5; //!< Reserved
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uint16_t wr: 1; //!< Wrap-around. 0: not the last descriptor in the table, 1: last descriptor.
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uint16_t irq: 1; //!< Generate interrupt after this descriptor is transmitted
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uint16_t e: 1; //!< The buffer is empty. 0: descriptor owned by SW, 1: descriptor owned by HW.
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uint16_t len; //!< Number of bytes received (filled by HW)
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void* rxpnt; //!< Pointer to the receive buffer
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} openeth_rx_desc_t;
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_Static_assert(sizeof(openeth_rx_desc_t) == 8, "incorrect size of openeth_rx_desc_t");
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static inline openeth_tx_desc_t* openeth_tx_desc(int idx)
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{
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assert(idx < TX_BUF_COUNT);
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return &((openeth_tx_desc_t*)OPENETH_DESC_BASE)[idx];
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}
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static inline openeth_rx_desc_t* openeth_rx_desc(int idx)
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{
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assert(idx < OPENETH_DESC_CNT - TX_BUF_COUNT);
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return &((openeth_rx_desc_t*)OPENETH_DESC_BASE)[idx + TX_BUF_COUNT];
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}
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static inline void openeth_enable(void)
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{
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REG_SET_BIT(OPENETH_MODER_REG, OPENETH_TXEN | OPENETH_RXEN | OPENETH_PRO);
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REG_SET_BIT(OPENETH_INT_MASK_REG, OPENETH_INT_RXB);
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}
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static inline void openeth_disable(void)
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{
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REG_CLR_BIT(OPENETH_INT_MASK_REG, OPENETH_INT_RXB);
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REG_CLR_BIT(OPENETH_MODER_REG, OPENETH_TXEN | OPENETH_RXEN | OPENETH_PRO);
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}
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static inline void openeth_reset(void)
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{
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REG_SET_BIT(OPENETH_MODER_REG, OPENETH_RST);
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REG_CLR_BIT(OPENETH_MODER_REG, OPENETH_RST);
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}
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static inline void openeth_init_tx_desc(openeth_tx_desc_t* desc, void* buf)
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{
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*desc = (openeth_tx_desc_t) {
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.rd = 0,
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.txpnt = buf
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};
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}
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static inline void openeth_init_rx_desc(openeth_rx_desc_t* desc, void* buf)
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{
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*desc = (openeth_rx_desc_t) {
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.e = 1,
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.irq = 1,
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.rxpnt = buf
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};
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}
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static inline void openeth_set_tx_desc_cnt(int tx_desc_cnt)
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{
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assert(tx_desc_cnt <= OPENETH_DESC_CNT);
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REG_WRITE(OPENETH_TX_BD_NUM_REG, tx_desc_cnt);
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}
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#ifdef __cplusplus
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}
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#endif
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