mirror
/
esp-idf
kopia lustrzana https://github.com/espressif/esp-idf
1
0
Forkuj 0
Kod Zgłoszenia Projekty Wydania Wiki Aktywność
20 630 Commity
20 Gałęzie
149 Tagi
419 MiB
Wykres commitów

97 Commity (c2c4b126f7fa68a6a9e8ababf0ff53112d52ff82)

Autor SHA1 Wiadomość Data
Li Shuai a939f7d34b light sleep: add software workaround for esp32s3 gpio reset issue 2021-10-20 11:36:22 +08:00
Marius Vikhammer 4869b3cd4a WDT: Add support for XTAL32K Watchdog timer 2021-09-02 09:09:00 +08:00
SalimTerryLi 2347e68e6b
soc: move peripheral linker scripts out of target component 2021-07-22 12:55:01 +08:00
morris 2058e89448 Merge branch 'feature/fpga_bootloader' into 'master' 
Boot ESP32 & ESP32-S2 apps on FPGA

See merge request espressif/esp-idf!8270
 2021-07-18 08:06:38 +00:00
Angus Gratton 9d6366f290 esp_hw_support: Move rtc.h header from target components 2021-07-16 20:14:28 +08:00
Renz Bagaporo b06dba7823 esp32: move app linker scripts 2021-07-16 20:14:27 +08:00
Renz Bagaporo fddc0b6799 esp32: move remaining tests 2021-07-16 20:14:27 +08:00
Renz Bagaporo 7c22cccb9c esp32: cleanup build script 2021-07-16 20:14:27 +08:00
Renz Bagaporo 452bfda367 esp32: move dport_access 2021-07-16 20:14:26 +08:00
Renz Bagaporo 702e41e1c8 esp32s2: move crypto related functions 2021-07-16 20:14:26 +08:00
Renz Bagaporo ea2aafbb7a esp32s2: move memprot api 2021-07-16 20:14:26 +08:00
Omar Chebib 9dd02354d2 Merge branch 'feature/riscv_panic_backtrace' into 'master' 
espsystem: add support for RISC-V panic backtrace

Closes IDF-2064

See merge request espressif/esp-idf!12070
 2021-07-16 04:13:44 +00:00
Angus Gratton c5d20dc231 fpga: Disable BOD when running on FPGA 2021-07-16 10:50:06 +10:00
Marius Vikhammer 126c6405f1 Merge branch 'feature/s3_default_2_config' into 'master' 
CI: add S3 default_2 unit test config

See merge request espressif/esp-idf!14279
 2021-07-15 09:29:31 +00:00
Omar Chebib 0771bd1711 espsystem: Rearchitecture and fix eh_frame_parser bugs 
eh_frame_parser is architecture independent, thus the files have
been rearchitectured. Some bugs have been fixed in the test.
A README file has also been added to eh_frame_parser host test
directory.

eh_frame_parser is now able to detect empty gaps in .eh_frame_hdr
table (missing DWARF information).
Fix a bug occuring when parsing backtraces originated from abort().
Fix build missing dependencies issue.
 2021-07-15 12:47:51 +08:00
Omar Chebib b967dc0dbf espsystem: add support for RISC-V panic backtrace 
Add .eh_frame and .eh_frame_hdr sections to the binary (can be
enabled/disabled within menuconfig). These sections are parsed
when a panic occurs. Their DWARF instructions are decoded and
executed at runtime, to retrieve the whole backtrace. This
parser has been tested on both RISC-V and x86 architectures.

This feature needs esptool's merge adjacent ELF sections feature.
 2021-07-13 15:42:40 +08:00
Marius Vikhammer 5d184dcfe0 soc: update S3 memory layout 2021-07-09 12:29:56 +08:00
Marius Vikhammer 4553654f40 build system: fix rtc_data being placed in wrong region for S3 2021-07-08 18:40:01 +08:00
morris 3b821b8ac3 Merge branch 'bugfix/rotary_encoder_example_main' into 'master' 
bugfix: rotary encoder example isr service install

Closes IDFGH-5105

See merge request espressif/esp-idf!14114
 2021-07-08 04:25:30 +00:00
Zhang Jun Hao 4702feeeeb esp_wifi: move unused wifi log to noload section to save binary size 2021-07-01 10:18:37 +08:00
bizhuangyang 1829783886 bugfix:rotary encoder example isr service install 
Fix the issue mentioned when using two or more encoders. Modify PCNT_CTRL_GND_IO
to avoid the affect of USB JTAG(origin pin 19 is used for USB D-). Update esp32c3.
peripherals.ld and docs for esp32s3.

Closes https://github.com/espressif/esp-idf/issues/6889
 2021-06-30 18:44:02 +08:00
Alexey Gerenkov 792461aa99 esp32c3: Do not enable memory protection under debugger 2021-06-24 13:10:11 +03:00
Michael (XIAO Xufeng) 58490418ad Merge branch 'feature/merge_c3_caps' into 'master' 
soc: merge C3 caps into a single soc_caps.h

See merge request espressif/esp-idf!13337
 2021-05-06 05:56:42 +00:00
Michael (XIAO Xufeng) 76fbb689fd Merge branch 'bugfix/remove_uart2_c3' into 'master' 
uart: remove misleading ld files and soc defs for UART2

See merge request espressif/esp-idf!13340
 2021-04-29 05:18:25 +00:00
Jeroen Domburg 2c75f63f89 * ets_delay_us(1) has too much overhead; change logic 
* Fix MR comments
 2021-04-28 16:38:24 +08:00
Marius Vikhammer 504a1e6102 soc: merge C3 caps into a single soc_caps.h 2021-04-28 14:42:35 +08:00
Michael (XIAO Xufeng) a0d13a31ec uart: fix misleading files for UART2 
Includes: header files, ld files and clk.c

ESP32-C3 only have UART0 and UART1.
 2021-04-27 17:40:19 +08:00
Angus Gratton 96c2acd9a8 Merge branch 'refactor/strip_systimer_hal_layer' into 'master' 
refactor HAL driver of systimer to a common systimer_hal

Closes IDF-2996

See merge request espressif/esp-idf!13027
 2021-04-23 07:45:31 +00:00
Angus Gratton 64a96ca96d Merge branch 'bugfix/RTC_CLK_CAL_CYCLES' into 'master' 
esp32xx: Fix the Number of cycles for RTC_SLOW_CLK calibration

See merge request espressif/esp-idf!13202
 2021-04-23 04:55:28 +00:00
morris 7c1e1c9e2d systimer: update soc data 2021-04-22 21:07:35 +08:00
morris 7eb9ecb4f6 esp_ds: move timeout mechanism to driver layer 2021-04-22 21:07:35 +08:00
Ivan Grokhotkov 0535195983 freertos: fix TLS run-time address calculation 
Since dd849ffc, _rodata_start label has been moved to a different
linker output section from where the TLS templates (.tdata, .tbss)
are located. Since link-time addresses of thread-local variables are
calculated relative to the section start address, this resulted in
incorrect calculation of THREADPTR/$tp registers.

Fix by introducing new linker label, _flash_rodata_start, which points
to the .flash.rodata output section where TLS variables are located,
and use it when calculating THREADPTR/$tp.

Also remove the hardcoded rodata section alignment for Xtensa targets.
Alignment of rodata can be affected by the user application, which is
the issue dd849ffc was fixing. To accommodate any possible alignment,
save it in a linker label (_flash_rodata_align) and then use when
calculating THREADPTR. Note that this is not required on RISC-V, since
this target doesn't use TPOFF.
 2021-04-21 13:45:21 +02:00
KonstantinKondrashov 8e1256ca88 esp32xx: Fix the Number of cycles for RTC_SLOW_CLK calibration 2021-04-20 06:29:42 +00:00
Omar Chebib dd849ffc26 build: (Custom) App version info is now on a dedicated section, independent of the rodata alignment 
It is now possible to have any alignment restriction on rodata in the user
applicaiton. It will not affect the first section which must be aligned
on a 16-byte bound.

Closes https://github.com/espressif/esp-idf/issues/6719
 2021-04-19 12:53:08 +08:00
Angus Gratton 111098568a esp32c3: Reserve RTC memory from bootloader in the app linker script 2021-04-15 16:20:58 +10:00
Martin Vychodil f27c9c5139 esp32c3: memprot API upgrade and test application 
Closes IDF-2641
 2021-04-12 13:44:11 +10:00
Angus Gratton 936523b904 Merge branch 'feature/secure_bootv2_c3' into 'master' 
secure_boot_v2: Support SB_V2 for ESP32-C3 ECO3

Closes IDF-2647

See merge request espressif/esp-idf!13040
 2021-04-12 01:31:25 +00:00
aditi_lonkar ed424c5f9f esp32c3: Fix issue of crashing if debug logs are enabled. 2021-04-08 09:43:25 +00:00
KonstantinKondrashov 1d8f885928 esp32c3: Default supported ESP32-C3 Revision ECO3 2021-04-08 15:06:22 +08:00
Renz Bagaporo a202a604d8 esp32: move system libs 2021-03-31 19:17:33 +08:00
Renz Bagaporo bbc599493e esp32: move common fragment definitions 2021-03-31 19:17:33 +08:00
Renz Bagaporo 9478298aa4 esp32: move mac target specific configs 2021-03-31 19:17:33 +08:00
Renz Bagaporo e6edf34e82 esp32: move esp_clk functions 2021-03-31 19:17:33 +08:00
Renz Bagaporo a7bac58480 esp32: move system api to esp_system 2021-03-31 19:13:03 +08:00
Renz Bagaporo 393bd64a1e esp32: move crosscore int 2021-03-31 19:13:03 +08:00
Renz Bagaporo 7d85c42e52 esp32: move brownout and cache err int setup 2021-03-31 19:13:03 +08:00
Renz Bagaporo 6014e3a198 esp32: move stack check test 2021-03-31 19:13:03 +08:00
Renz Bagaporo 784a02a4ee esp32: move hw random 2021-03-31 19:13:03 +08:00
Angus Gratton 771718d07a Merge branch 'bugfix/prefetch_invalid' into 'master' 
soc: add dummy bytes to ensure instr prefetch always valid

Closes IDFCI-533

See merge request espressif/esp-idf!12940
 2021-03-31 00:44:10 +00:00
Marius Vikhammer 8ac74082f1 soc: add dummy bytes to ensure instr prefetch always valid 
The CPU might prefetch instructions, which means it in some cases
will try to fetch instruction located after the last instruction in
flash.text.

Add dummy bytes to ensure fetching these wont result in an error,
 e.g. MMU exceptions
 2021-03-29 13:50:03 +08:00