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* ets_delay_us(1) has too much overhead; change logic 

* Fix MR comments
pull/6995/head
Jeroen Domburg 2021-04-28 16:38:24 +08:00
rodzic 184b977707
commit 2c75f63f89
28 zmienionych plików z 2099 dodań i 51 usunięć
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8
components/bootloader_support/src/bootloader_console.c
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@ -111,3 +111,11 @@ void bootloader_console_init(void)
esp_rom_install_channel_putc(1, bootloader_console_write_char_usb);
}
#endif //CONFIG_ESP_CONSOLE_USB_CDC
#ifdef CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
void bootloader_console_init(void)
{
//Nothing to do; ROM already outputs here by default.
//(But also to the UART; should we disable that? hmm.)
}
#endif //CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG

1
components/esp32c3/ld/esp32c3.peripherals.ld
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@ -27,4 +27,5 @@ PROVIDE ( SYSCON = 0x60026000 );
PROVIDE ( TWAI = 0x6002B000 );
PROVIDE ( GPSPI4 = 0x60037000 );
PROVIDE ( APB_SARADC = 0x60040000 );
PROVIDE ( USB_SERIAL_JTAG = 0x60043000 );
PROVIDE ( GDMA = 0x6003F000 );

5
components/esp_gdbstub/esp32/gdbstub_esp32.c
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@ -39,6 +39,11 @@ void esp_gdbstub_putchar(int c)
REG_WRITE(UART_FIFO_REG(UART_NUM), c);
}
void esp_gdbstub_flush()
{
//not needed for uart
}
int esp_gdbstub_readmem(intptr_t addr)
{
if (addr < 0x20000000 || addr >= 0x80000000) {

36
components/esp_gdbstub/esp32c3/gdbstub_esp32c3.c
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@ -15,6 +15,8 @@
#include "soc/uart_periph.h"
#include "soc/gpio_periph.h"
#include "soc/soc.h"
#include "soc/usb_serial_jtag_struct.h"
#include "hal/usb_serial_jtag_ll.h"
#include "esp_gdbstub_common.h"
#include "sdkconfig.h"
@ -60,6 +62,33 @@ void esp_gdbstub_target_init()
{
}
#if CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
int esp_gdbstub_getchar()
{
uint8_t c;
//retry the read until we succeed
while (usb_serial_jtag_ll_read_rxfifo(&c, 1)==0) ;
return c;
}
void esp_gdbstub_putchar(int c)
{
uint8_t cc=c;
//retry the write until we succeed
while (usb_serial_jtag_ll_write_txfifo(&cc, 1)<1) ;
}
void esp_gdbstub_flush()
{
usb_serial_jtag_ll_txfifo_flush();
}
#else
//assume UART gdbstub channel
int esp_gdbstub_getchar()
{
while (REG_GET_FIELD(UART_STATUS_REG(UART_NUM), UART_RXFIFO_CNT) == 0) {
@ -76,6 +105,13 @@ void esp_gdbstub_putchar(int c)
REG_WRITE(UART_FIFO_AHB_REG(UART_NUM), c);
}
void esp_gdbstub_flush()
{
//not needed for uart
}
#endif
int esp_gdbstub_readmem(intptr_t addr)
{
if (!check_inside_valid_region(addr)) {

5
components/esp_gdbstub/esp32s2/gdbstub_esp32s2.c
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@ -39,6 +39,11 @@ void esp_gdbstub_putchar(int c)
REG_WRITE(UART_FIFO_AHB_REG(UART_NUM), c);
}
void esp_gdbstub_flush()
{
//not needed for uart
}
int esp_gdbstub_readmem(intptr_t addr)
{
if (addr < 0x20000000 || addr >= 0x80000000) {

5
components/esp_gdbstub/esp32s3/gdbstub_esp32s3.c
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@ -39,6 +39,11 @@ void esp_gdbstub_putchar(int c)
REG_WRITE(UART_FIFO_AHB_REG(UART_NUM), c);
}
void esp_gdbstub_flush()
{
//not needed for uart
}
int esp_gdbstub_readmem(intptr_t addr)
{
if (addr < 0x20000000 || addr >= 0x80000000) {

5
components/esp_gdbstub/private_include/esp_gdbstub_common.h
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@ -119,6 +119,11 @@ void esp_gdbstub_putchar(int c);
*/
int esp_gdbstub_readmem(intptr_t addr);
/**
* Make sure all bytes sent using putchar() end up at the host.
* (Usually stubbed for UART, but can be useful for other channels)
*/
void esp_gdbstub_flush(void);
/**** GDB packet related functions ****/

1
components/esp_gdbstub/src/packet.c
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@ -64,6 +64,7 @@ void esp_gdbstub_send_end(void)
{
esp_gdbstub_putchar('#');
esp_gdbstub_send_hex(s_chsum, 8);
esp_gdbstub_flush();
}
// Send a packet with a string as content

8
components/esp_system/Kconfig
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@ -169,9 +169,12 @@ menu "ESP System Settings"
- If "None" is selected, there will be no console output on any UART, except
for initial output from ROM bootloader. This ROM output can be suppressed by
GPIO strapping or EFUSE, refer to chip datasheet for details.
- On chips with USB peripheral, "USB CDC" option redirects output to the
- On chips with USB OTG peripheral, "USB CDC" option redirects output to the
CDC port. This option uses the CDC driver in the chip ROM.
This option is incompatible with TinyUSB stack.
- On chips with an USB serial/JTAG debug controller, selecting the option
for that redirects output to the CDC/ACM (serial port emulation) component
of that device.
config ESP_CONSOLE_UART_DEFAULT
bool "Default: UART0"
config ESP_CONSOLE_USB_CDC
@ -179,6 +182,9 @@ menu "ESP System Settings"
# The naming is confusing: USB_ENABLED means that TinyUSB driver is enabled, not USB in general.
# && !USB_ENABLED is because the ROM CDC driver is currently incompatible with TinyUSB.
depends on (IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3) && !USB_ENABLED
config ESP_CONSOLE_USB_SERIAL_JTAG
bool "USB Serial/JTAG Controller"
depends on IDF_TARGET_ESP32C3
config ESP_CONSOLE_UART_CUSTOM
bool "Custom UART"
config ESP_CONSOLE_NONE

91
components/esp_system/panic.c
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@ -30,6 +30,7 @@
#include "esp_private/panic_internal.h"
#include "port/panic_funcs.h"
#include "esp_rom_sys.h"
#include "sdkconfig.h"
@ -58,6 +59,10 @@
#include "esp_gdbstub.h"
#endif
#if CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
#include "hal/usb_serial_jtag_ll.h"
#endif
bool g_panic_abort = false;
static char *s_panic_abort_details = NULL;
@ -68,13 +73,13 @@ static wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1
#if !CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT
#if CONFIG_ESP_CONSOLE_UART
static uart_hal_context_t s_panic_uart = { .dev = CONFIG_ESP_CONSOLE_UART_NUM == 0 ? &UART0 : &UART1 };
static uart_hal_context_t s_panic_uart = { .dev = CONFIG_ESP_CONSOLE_UART_NUM == 0 ? &UART0 :&UART1 };
void panic_print_char(const char c)
{
uint32_t sz = 0;
while(!uart_hal_get_txfifo_len(&s_panic_uart));
uart_hal_write_txfifo(&s_panic_uart, (uint8_t*) &c, 1, &sz);
while (!uart_hal_get_txfifo_len(&s_panic_uart));
uart_hal_write_txfifo(&s_panic_uart, (uint8_t *) &c, 1, &sz);
}
#endif // CONFIG_ESP_CONSOLE_UART
@ -87,6 +92,27 @@ void panic_print_char(const char c)
}
#endif // CONFIG_ESP_CONSOLE_USB_CDC
#if CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
//Timeout; if there's no host listening, the txfifo won't ever
//be writable after the first packet.
#define USBSERIAL_TIMEOUT_MAX_US 50000
static int s_usbserial_timeout = 0;
void panic_print_char(const char c)
{
while (!usb_serial_jtag_ll_txfifo_writable() && s_usbserial_timeout < (USBSERIAL_TIMEOUT_MAX_US / 100)) {
esp_rom_delay_us(100);
s_usbserial_timeout++;
}
if (usb_serial_jtag_ll_txfifo_writable()) {
usb_serial_jtag_ll_write_txfifo((const uint8_t *)&c, 1);
s_usbserial_timeout = 0;
}
}
#endif //CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
#if CONFIG_ESP_CONSOLE_NONE
void panic_print_char(const char c)
{
@ -96,7 +122,7 @@ void panic_print_char(const char c)
void panic_print_str(const char *str)
{
for(int i = 0; str[i] != 0; i++) {
for (int i = 0; str[i] != 0; i++) {
panic_print_char(str[i]);
}
}
@ -145,7 +171,7 @@ static void reconfigure_all_wdts(void)
//Reconfigure TWDT (Timer Group 0)
wdt_hal_init(&wdt0_context, WDT_MWDT0, MWDT0_TICK_PRESCALER, false); //Prescaler: wdt counts in ticks of TG0_WDT_TICK_US
wdt_hal_write_protect_disable(&wdt0_context);
wdt_hal_config_stage(&wdt0_context, 0, 1000*1000/MWDT0_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM); //1 second before reset
wdt_hal_config_stage(&wdt0_context, 0, 1000 * 1000 / MWDT0_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM); //1 second before reset
wdt_hal_enable(&wdt0_context);
wdt_hal_write_protect_enable(&wdt0_context);
@ -190,29 +216,29 @@ void esp_panic_handler(panic_info_t *info)
info->exception = PANIC_EXCEPTION_ABORT;
}
/*
* For any supported chip, the panic handler prints the contents of panic_info_t in the following format:
*
*
* Guru Meditation Error: Core <core> (<exception>). <description>
* <details>
*
* <state>
*
* <elf_info>
*
*
* ----------------------------------------------------------------------------------------
* core - core where exception was triggered
* exception - what kind of exception occured
* description - a short description regarding the exception that occured
* details - more details about the exception
* state - processor state like register contents, and backtrace
* elf_info - details about the image currently running
*
* NULL fields in panic_info_t are not printed.
*
* */
/*
* For any supported chip, the panic handler prints the contents of panic_info_t in the following format:
*
*
* Guru Meditation Error: Core <core> (<exception>). <description>
* <details>
*
* <state>
*
* <elf_info>
*
*
* ----------------------------------------------------------------------------------------
* core - core where exception was triggered
* exception - what kind of exception occured
* description - a short description regarding the exception that occured
* details - more details about the exception
* state - processor state like register contents, and backtrace
* elf_info - details about the image currently running
*
* NULL fields in panic_info_t are not printed.
*
* */
if (info->reason) {
panic_print_str("Guru Meditation Error: Core ");
panic_print_dec(info->core);
@ -296,7 +322,7 @@ void esp_panic_handler(panic_info_t *info)
wdt_hal_disable(&rtc_wdt_ctx);
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
panic_print_str("Entering gdb stub now.\r\n");
esp_gdbstub_panic_handler((esp_gdbstub_frame_t*)info->frame);
esp_gdbstub_panic_handler((esp_gdbstub_frame_t *)info->frame);
#else
#if CONFIG_ESP_COREDUMP_ENABLE
static bool s_dumping_core;
@ -321,8 +347,7 @@ void esp_panic_handler(panic_info_t *info)
#if CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT || CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT
if (esp_reset_reason_get_hint() == ESP_RST_UNKNOWN) {
switch (info->exception)
{
switch (info->exception) {
case PANIC_EXCEPTION_IWDT:
esp_reset_reason_set_hint(ESP_RST_INT_WDT);
break;
@ -351,7 +376,7 @@ void esp_panic_handler(panic_info_t *info)
void __attribute__((noreturn,no_sanitize_undefined)) panic_abort(const char *details)
{
g_panic_abort = true;
s_panic_abort_details = (char*) details;
s_panic_abort_details = (char *) details;
#if CONFIG_APPTRACE_ENABLE
#if CONFIG_SYSVIEW_ENABLE
@ -363,7 +388,7 @@ void __attribute__((noreturn,no_sanitize_undefined)) panic_abort(const char *det
#endif
*((int *) 0) = 0; // NOLINT(clang-analyzer-core.NullDereference) should be an invalid operation on targets
while(1);
while (1);
}
/* Weak versions of reset reason hint functions.

5
components/esp_system/startup.c
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@ -59,6 +59,7 @@
#include "esp_pthread.h"
#include "esp_private/usb_console.h"
#include "esp_vfs_cdcacm.h"
#include "esp_vfs_usb_serial_jtag.h"
#include "brownout.h"
@ -264,6 +265,10 @@ static void do_core_init(void)
ESP_ERROR_CHECK(esp_vfs_dev_cdcacm_register());
const char *default_stdio_dev = "/dev/cdcacm";
#endif // CONFIG_ESP_CONSOLE_USB_CDC
#ifdef CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
ESP_ERROR_CHECK(esp_vfs_dev_usb_serial_jtag_register());
const char *default_stdio_dev = "/dev/usbserjtag";
#endif // CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
#endif // CONFIG_VFS_SUPPORT_IO
#if defined(CONFIG_VFS_SUPPORT_IO) && !defined(CONFIG_ESP_CONSOLE_NONE)

169
components/hal/esp32c3/include/hal/usb_serial_jtag_ll.h 100644
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@ -0,0 +1,169 @@
// Copyright 2021 Espressif Systems (Shanghai)
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// The LL layer of the USB-serial-jtag controller
#pragma once
#include "soc/usb_serial_jtag_reg.h"
#include "soc/usb_serial_jtag_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
//The in and out endpoints are this long.
#define USB_SERIAL_JTAG_PACKET_SZ_BYTES 64
#define USB_SERIAL_JTAG_LL_INTR_MASK (0x7ffff) //All interrupt mask
// Define USB_SERIAL_JTAG interrupts
// Note the hardware has more interrupts, but they're only useful for debugging
// the hardware.
typedef enum {
USB_SERIAL_JTAG_INTR_SOF = (1 << 1),
USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT = (1 << 2),
USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY = (1 << 3),
USB_SERIAL_JTAG_INTR_TOKEN_REC_IN_EP1 = (1 << 8),
USB_SERIAL_JTAG_INTR_BUS_RESET = (1 << 9),
USB_SERIAL_JTAG_INTR_EP1_ZERO_PAYLOAD = (1 << 10),
} usb_serial_jtag_intr_t;
/**
* @brief Enable the USB_SERIAL_JTAG interrupt based on the given mask.
*
* @param mask The bitmap of the interrupts need to be enabled.
*
* @return None
*/
static inline void usb_serial_jtag_ll_ena_intr_mask(uint32_t mask)
{
USB_SERIAL_JTAG.int_ena.val |= mask;
}
/**
* @brief Disable the USB_SERIAL_JTAG interrupt based on the given mask.
*
* @param mask The bitmap of the interrupts need to be disabled.
*
* @return None
*/
static inline void usb_serial_jtag_ll_disable_intr_mask(uint32_t mask)
{
USB_SERIAL_JTAG.int_ena.val &= (~mask);
}
/**
* @brief Get the USB_SERIAL_JTAG interrupt status.
*
* @return The USB_SERIAL_JTAG interrupt status.
*/
static inline uint32_t usb_serial_jtag_ll_get_intsts_mask(void)
{
return USB_SERIAL_JTAG.int_st.val;
}
/**
* @brief Clear the USB_SERIAL_JTAG interrupt status based on the given mask.
*
* @param mask The bitmap of the interrupts need to be cleared.
*
* @return None
*/
static inline void usb_serial_jtag_ll_clr_intsts_mask(uint32_t mask)
{
USB_SERIAL_JTAG.int_clr.val = mask;
}
/**
* @brief Get status of enabled interrupt.
*
* @return interrupt enable value
*/
static inline uint32_t usb_serial_jtag_ll_get_intr_ena_status(void)
{
return USB_SERIAL_JTAG.int_ena.val;
}
/**
* @brief Read the bytes from the USB_SERIAL_JTAG rxfifo.
*
* @param buf The data buffer.
* @param rd_len The data length needs to be read.
*
* @return amount of bytes read
*/
static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len)
{
int i;
for (i = 0; i < (int)rd_len; i++) {
if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break;
buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte;
}
return i;
}
/**
* @brief Write byte to the USB_SERIAL_JTAG txfifo. Only writes bytes as long / if there
* is room in the buffer.
*
* @param buf The data buffer.
* @param wr_len The data length needs to be writen.
*
* @return Amount of bytes actually written. May be less than wr_len.
*/
static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t wr_len)
{
int i;
for (i = 0; i < (int)wr_len; i++) {
if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break;
USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i];
}
return i;
}
/**
* @brief Returns 1 if the USB_SERIAL_JTAG rxfifo has data available.
*
* @return 0 if no data available, 1 if data available
*/
static inline int usb_serial_jtag_ll_rxfifo_data_available(void)
{
return USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail;
}
/**
* @brief Returns 1 if the USB_SERIAL_JTAG txfifo has room.
*
* @return 0 if no data available, 1 if data available
*/
static inline int usb_serial_jtag_ll_txfifo_writable(void)
{
return USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free;
}
/**
* @brief Flushes the TX buffer, that is, make it available for the
* host to pick up.
*
* @return na
*/
static inline void usb_serial_jtag_ll_txfifo_flush(void)
{
USB_SERIAL_JTAG.ep1_conf.wr_done=1;
}
#ifdef __cplusplus
}
#endif

15
components/soc/esp32c3/include/soc/soc_caps.h
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@ -5,13 +5,14 @@
#pragma once
#define SOC_CPU_CORES_NUM 1
#define SOC_GDMA_SUPPORTED 1
#define SOC_TWAI_SUPPORTED 1
#define SOC_BT_SUPPORTED 1
#define SOC_DIG_SIGN_SUPPORTED 1
#define SOC_HMAC_SUPPORTED 1
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
#define SOC_CPU_CORES_NUM 1
#define SOC_GDMA_SUPPORTED 1
#define SOC_TWAI_SUPPORTED 1
#define SOC_BT_SUPPORTED 1
#define SOC_DIG_SIGN_SUPPORTED 1
#define SOC_HMAC_SUPPORTED 1
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
#define SOC_USB_SERIAL_JTAG_SUPPORTED 1
#include "i2c_caps.h"
#include "mpu_caps.h"

993
components/soc/esp32c3/include/soc/usb_serial_jtag_reg.h 100644
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@ -0,0 +1,993 @@
/** Copyright 2021 Espressif Systems (Shanghai) Co. Ltd.
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** Configuration Registers */
/** USB_SERIAL_JTAG_EP1_REG register
* USB_SERIAL_JTAG_EP1_REG.
*/
#define USB_SERIAL_JTAG_EP1_REG (SOC_DPORT_USB_BASE + 0x0)
/* USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [8:0]; default: 0;
* Write and read byte data to/from UART Tx/Rx FIFO through this field.
* When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set then user can write
* data (up to 64 bytes) into UART Tx FIFO. When
* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check
* USB_SERIAL_JTAG_OUT_EP1_WR_ADDR and USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to
* know how many data is received, then read that amount of data from UART
* Rx
* FIFO.
*/
#define USB_SERIAL_JTAG_RDWR_BYTE 0x000000FF
#define USB_SERIAL_JTAG_RDWR_BYTE_M (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S)
#define USB_SERIAL_JTAG_RDWR_BYTE_V 0x000000FF
#define USB_SERIAL_JTAG_RDWR_BYTE_S 0
/** USB_SERIAL_JTAG_CONF0_REG register
* USB_SERIAL_JTAG_CONF0_REG.
*/
#define USB_SERIAL_JTAG_CONF0_REG (SOC_DPORT_USB_BASE + 0x18)
/* USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
* Select internal/external PHY. 1’b0: internal PHY, 1’b1: external
* PHY
*/
#define USB_SERIAL_JTAG_PHY_SEL (BIT(0))
#define USB_SERIAL_JTAG_PHY_SEL_M (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S)
#define USB_SERIAL_JTAG_PHY_SEL_V 0x00000001
#define USB_SERIAL_JTAG_PHY_SEL_S 0
/* USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0;
* Enable software control USB D+ D-
* exchange
*/
#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE (BIT(1))
#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S)
#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V 0x00000001
#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S 1
/* USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0;
* USB D+ D-
* exchange
*/
#define USB_SERIAL_JTAG_EXCHG_PINS (BIT(2))
#define USB_SERIAL_JTAG_EXCHG_PINS_M (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S)
#define USB_SERIAL_JTAG_EXCHG_PINS_V 0x00000001
#define USB_SERIAL_JTAG_EXCHG_PINS_S 2
/* USB_SERIAL_JTAG_VREFL : R/W; bitpos: [5:3]; default: 0;
* Control single-end input high threshold. 1.76V to 2V, step
* 80mV
*/
#define USB_SERIAL_JTAG_VREFL 0x00000003
#define USB_SERIAL_JTAG_VREFL_M (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S)
#define USB_SERIAL_JTAG_VREFL_V 0x00000003
#define USB_SERIAL_JTAG_VREFL_S 3
/* USB_SERIAL_JTAG_VREFH : R/W; bitpos: [7:5]; default: 0;
* Control single-end input low threshold. 0.8V to 1.04V, step
* 80mV
*/
#define USB_SERIAL_JTAG_VREFH 0x00000003
#define USB_SERIAL_JTAG_VREFH_M (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S)
#define USB_SERIAL_JTAG_VREFH_V 0x00000003
#define USB_SERIAL_JTAG_VREFH_S 5
/* USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0;
* Enable software control input
* threshold
*/
#define USB_SERIAL_JTAG_VREF_OVERRIDE (BIT(7))
#define USB_SERIAL_JTAG_VREF_OVERRIDE_M (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S)
#define USB_SERIAL_JTAG_VREF_OVERRIDE_V 0x00000001
#define USB_SERIAL_JTAG_VREF_OVERRIDE_S 7
/* USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0;
* Enable software control USB D+ D- pullup
* pulldown
*/
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8))
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S)
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x00000001
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8
/* USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1;
* Control USB D+ pull
* up.
*/
#define USB_SERIAL_JTAG_DP_PULLUP (BIT(9))
#define USB_SERIAL_JTAG_DP_PULLUP_M (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S)
#define USB_SERIAL_JTAG_DP_PULLUP_V 0x00000001
#define USB_SERIAL_JTAG_DP_PULLUP_S 9
/* USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0;
* Control USB D+ pull
* down.
*/
#define USB_SERIAL_JTAG_DP_PULLDOWN (BIT(10))
#define USB_SERIAL_JTAG_DP_PULLDOWN_M (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S)
#define USB_SERIAL_JTAG_DP_PULLDOWN_V 0x00000001
#define USB_SERIAL_JTAG_DP_PULLDOWN_S 10
/* USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0;
* Control USB D- pull
* up.
*/
#define USB_SERIAL_JTAG_DM_PULLUP (BIT(11))
#define USB_SERIAL_JTAG_DM_PULLUP_M (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S)
#define USB_SERIAL_JTAG_DM_PULLUP_V 0x00000001
#define USB_SERIAL_JTAG_DM_PULLUP_S 11
/* USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0;
* Control USB D- pull
* down.
*/
#define USB_SERIAL_JTAG_DM_PULLDOWN (BIT(12))
#define USB_SERIAL_JTAG_DM_PULLDOWN_M (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S)
#define USB_SERIAL_JTAG_DM_PULLDOWN_V 0x00000001
#define USB_SERIAL_JTAG_DM_PULLDOWN_S 12
/* USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0;
* Control pull up
* value.
*/
#define USB_SERIAL_JTAG_PULLUP_VALUE (BIT(13))
#define USB_SERIAL_JTAG_PULLUP_VALUE_M (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S)
#define USB_SERIAL_JTAG_PULLUP_VALUE_V 0x00000001
#define USB_SERIAL_JTAG_PULLUP_VALUE_S 13
/* USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1;
* Enable USB pad
* function.
*/
#define USB_SERIAL_JTAG_USB_PAD_ENABLE (BIT(14))
#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S)
#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V 0x00000001
#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S 14
/** USB_SERIAL_JTAG_TEST_REG register
* USB_SERIAL_JTAG_TEST_REG.
*/
#define USB_SERIAL_JTAG_TEST_REG (SOC_DPORT_USB_BASE + 0x1c)
/* USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
* Enable test of the USB
* pad
*/
#define USB_SERIAL_JTAG_TEST_ENABLE (BIT(0))
#define USB_SERIAL_JTAG_TEST_ENABLE_M (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S)
#define USB_SERIAL_JTAG_TEST_ENABLE_V 0x00000001
#define USB_SERIAL_JTAG_TEST_ENABLE_S 0
/* USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0;
* USB pad oen in
* test
*/
#define USB_SERIAL_JTAG_TEST_USB_OE (BIT(1))
#define USB_SERIAL_JTAG_TEST_USB_OE_M (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S)
#define USB_SERIAL_JTAG_TEST_USB_OE_V 0x00000001
#define USB_SERIAL_JTAG_TEST_USB_OE_S 1
/* USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
* USB D+ tx value in
* test
*/
#define USB_SERIAL_JTAG_TEST_TX_DP (BIT(2))
#define USB_SERIAL_JTAG_TEST_TX_DP_M (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S)
#define USB_SERIAL_JTAG_TEST_TX_DP_V 0x00000001
#define USB_SERIAL_JTAG_TEST_TX_DP_S 2
/* USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
* USB D- tx value in
* test
*/
#define USB_SERIAL_JTAG_TEST_TX_DM (BIT(3))
#define USB_SERIAL_JTAG_TEST_TX_DM_M (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S)
#define USB_SERIAL_JTAG_TEST_TX_DM_V 0x00000001
#define USB_SERIAL_JTAG_TEST_TX_DM_S 3
/** USB_SERIAL_JTAG_MISC_CONF_REG register
* USB_SERIAL_JTAG_MISC_CONF_REG.
*/
#define USB_SERIAL_JTAG_MISC_CONF_REG (SOC_DPORT_USB_BASE + 0x44)
/* USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
* 1'h1: Force clock on for register. 1'h0: Support clock only when
* application writes
* registers.
*/
#define USB_SERIAL_JTAG_CLK_EN (BIT(0))
#define USB_SERIAL_JTAG_CLK_EN_M (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S)
#define USB_SERIAL_JTAG_CLK_EN_V 0x00000001
#define USB_SERIAL_JTAG_CLK_EN_S 0
/** USB_SERIAL_JTAG_MEM_CONF_REG register
* USB_SERIAL_JTAG_MEM_CONF_REG.
*/
#define USB_SERIAL_JTAG_MEM_CONF_REG (SOC_DPORT_USB_BASE + 0x48)
/* USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
* 1: power down usb
* memory.
*/
#define USB_SERIAL_JTAG_USB_MEM_PD (BIT(0))
#define USB_SERIAL_JTAG_USB_MEM_PD_M (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S)
#define USB_SERIAL_JTAG_USB_MEM_PD_V 0x00000001
#define USB_SERIAL_JTAG_USB_MEM_PD_S 0
/* USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1;
* 1: Force clock on for usb
* memory.
*/
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1))
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S)
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S 1
/** Status Registers */
/** USB_SERIAL_JTAG_EP1_CONF_REG register
* USB_SERIAL_JTAG_EP1_CONF_REG.
*/
#define USB_SERIAL_JTAG_EP1_CONF_REG (SOC_DPORT_USB_BASE + 0x4)
/* USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
* Set this bit to indicate writing byte data to UART Tx FIFO is done.
* This bit then stays 0 until data in UART Tx FIFO is read by the USB
* Host.
*/
#define USB_SERIAL_JTAG_WR_DONE (BIT(0))
#define USB_SERIAL_JTAG_WR_DONE_M (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S)
#define USB_SERIAL_JTAG_WR_DONE_V 0x00000001
#define USB_SERIAL_JTAG_WR_DONE_S 0
/* USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1;
* 1'b1: Indicate UART Tx FIFO is not full and data can be written into
* in. After writing USB_SERIAL_JTAG_WR_DONE, this will be 1’b0 until the
* data is sent to the USB
* Host.
*/
#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1))
#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S)
#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V 0x00000001
#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S 1
/* USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0;
* 1'b1: Indicate there is data in UART Rx
* FIFO.
*/
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2))
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S)
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2
/** USB_SERIAL_JTAG_JFIFO_ST_REG register
* USB_SERIAL_JTAG_JFIFO_ST_REG.
*/
#define USB_SERIAL_JTAG_JFIFO_ST_REG (SOC_DPORT_USB_BASE + 0x20)
/* USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [2:0]; default: 0;
* JTAG in fifo
* counter.
*/
#define USB_SERIAL_JTAG_IN_FIFO_CNT 0x00000003
#define USB_SERIAL_JTAG_IN_FIFO_CNT_M (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S)
#define USB_SERIAL_JTAG_IN_FIFO_CNT_V 0x00000003
#define USB_SERIAL_JTAG_IN_FIFO_CNT_S 0
/* USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
* 1: JTAG in fifo is
* empty.
*/
#define USB_SERIAL_JTAG_IN_FIFO_EMPTY (BIT(2))
#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S)
#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V 0x00000001
#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S 2
/* USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0;
* 1: JTAG in fifo is
* full.
*/
#define USB_SERIAL_JTAG_IN_FIFO_FULL (BIT(3))
#define USB_SERIAL_JTAG_IN_FIFO_FULL_M (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S)
#define USB_SERIAL_JTAG_IN_FIFO_FULL_V 0x00000001
#define USB_SERIAL_JTAG_IN_FIFO_FULL_S 3
/* USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [6:4]; default: 0;
* JTAT out fifo
* counter.
*/
#define USB_SERIAL_JTAG_OUT_FIFO_CNT 0x00000003
#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S)
#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V 0x00000003
#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S 4
/* USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1;
* 1: JTAG out fifo is
* empty.
*/
#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY (BIT(6))
#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S)
#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V 0x00000001
#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S 6
/* USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0;
* 1: JTAG out fifo is
* full.
*/
#define USB_SERIAL_JTAG_OUT_FIFO_FULL (BIT(7))
#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S)
#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V 0x00000001
#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S 7
/* USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0;
* Write 1 to reset JTAG in
* fifo.
*/
#define USB_SERIAL_JTAG_IN_FIFO_RESET (BIT(8))
#define USB_SERIAL_JTAG_IN_FIFO_RESET_M (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S)
#define USB_SERIAL_JTAG_IN_FIFO_RESET_V 0x00000001
#define USB_SERIAL_JTAG_IN_FIFO_RESET_S 8
/* USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0;
* Write 1 to reset JTAG out
* fifo.
*/
#define USB_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9))
#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S)
#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001
#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S 9
/** USB_SERIAL_JTAG_FRAM_NUM_REG register
* USB_SERIAL_JTAG_FRAM_NUM_REG.
*/
#define USB_SERIAL_JTAG_FRAM_NUM_REG (SOC_DPORT_USB_BASE + 0x24)
/* USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [11:0]; default: 0;
* Frame index of received SOF
* frame.
*/
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007FF
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S)
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007FF
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0
/** USB_SERIAL_JTAG_IN_EP0_ST_REG register
* USB_SERIAL_JTAG_IN_EP0_ST_REG.
*/
#define USB_SERIAL_JTAG_IN_EP0_ST_REG (SOC_DPORT_USB_BASE + 0x28)
/* USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [2:0]; default: 1;
* State of IN Endpoint
* 0.
*/
#define USB_SERIAL_JTAG_IN_EP0_STATE 0x00000003
#define USB_SERIAL_JTAG_IN_EP0_STATE_M (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S)
#define USB_SERIAL_JTAG_IN_EP0_STATE_V 0x00000003
#define USB_SERIAL_JTAG_IN_EP0_STATE_S 0
/* USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [9:2]; default: 0;
* Write data address of IN endpoint
* 0.
*/
#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR 0x0000007F
#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S)
#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S 2
/* USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [16:9]; default: 0;
* Read data address of IN endpoint
* 0.
*/
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007F
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S)
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9
/** USB_SERIAL_JTAG_IN_EP1_ST_REG register
* USB_SERIAL_JTAG_IN_EP1_ST_REG.
*/
#define USB_SERIAL_JTAG_IN_EP1_ST_REG (SOC_DPORT_USB_BASE + 0x2c)
/* USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [2:0]; default: 1;
* State of IN Endpoint
* 1.
*/
#define USB_SERIAL_JTAG_IN_EP1_STATE 0x00000003
#define USB_SERIAL_JTAG_IN_EP1_STATE_M (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S)
#define USB_SERIAL_JTAG_IN_EP1_STATE_V 0x00000003
#define USB_SERIAL_JTAG_IN_EP1_STATE_S 0
/* USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [9:2]; default: 0;
* Write data address of IN endpoint
* 1.
*/
#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR 0x0000007F
#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S)
#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S 2
/* USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [16:9]; default: 0;
* Read data address of IN endpoint
* 1.
*/
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007F
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S)
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9
/** USB_SERIAL_JTAG_IN_EP2_ST_REG register
* USB_SERIAL_JTAG_IN_EP2_ST_REG.
*/
#define USB_SERIAL_JTAG_IN_EP2_ST_REG (SOC_DPORT_USB_BASE + 0x30)
/* USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [2:0]; default: 1;
* State of IN Endpoint
* 2.
*/
#define USB_SERIAL_JTAG_IN_EP2_STATE 0x00000003
#define USB_SERIAL_JTAG_IN_EP2_STATE_M (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S)
#define USB_SERIAL_JTAG_IN_EP2_STATE_V 0x00000003
#define USB_SERIAL_JTAG_IN_EP2_STATE_S 0
/* USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [9:2]; default: 0;
* Write data address of IN endpoint
* 2.
*/
#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR 0x0000007F
#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S)
#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S 2
/* USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [16:9]; default: 0;
* Read data address of IN endpoint
* 2.
*/
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007F
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S)
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9
/** USB_SERIAL_JTAG_IN_EP3_ST_REG register
* USB_SERIAL_JTAG_IN_EP3_ST_REG.
*/
#define USB_SERIAL_JTAG_IN_EP3_ST_REG (SOC_DPORT_USB_BASE + 0x34)
/* USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [2:0]; default: 1;
* State of IN Endpoint
* 3.
*/
#define USB_SERIAL_JTAG_IN_EP3_STATE 0x00000003
#define USB_SERIAL_JTAG_IN_EP3_STATE_M (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S)
#define USB_SERIAL_JTAG_IN_EP3_STATE_V 0x00000003
#define USB_SERIAL_JTAG_IN_EP3_STATE_S 0
/* USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [9:2]; default: 0;
* Write data address of IN endpoint
* 3.
*/
#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR 0x0000007F
#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S)
#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S 2
/* USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [16:9]; default: 0;
* Read data address of IN endpoint
* 3.
*/
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007F
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S)
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9
/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
* USB_SERIAL_JTAG_OUT_EP0_ST_REG.
*/
#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (SOC_DPORT_USB_BASE + 0x38)
/* USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [2:0]; default: 0;
* State of OUT Endpoint
* 0.
*/
#define USB_SERIAL_JTAG_OUT_EP0_STATE 0x00000003
#define USB_SERIAL_JTAG_OUT_EP0_STATE_M (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S)
#define USB_SERIAL_JTAG_OUT_EP0_STATE_V 0x00000003
#define USB_SERIAL_JTAG_OUT_EP0_STATE_S 0
/* USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [9:2]; default: 0;
* Write data address of OUT endpoint 0. When
* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are
* USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT
* EP0.
*/
#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S)
#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S 2
/* USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [16:9]; default: 0;
* Read data address of OUT endpoint
* 0.
*/
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S)
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9
/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
* USB_SERIAL_JTAG_OUT_EP1_ST_REG.
*/
#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (SOC_DPORT_USB_BASE + 0x3c)
/* USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [2:0]; default: 0;
* State of OUT Endpoint
* 1.
*/
#define USB_SERIAL_JTAG_OUT_EP1_STATE 0x00000003
#define USB_SERIAL_JTAG_OUT_EP1_STATE_M (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S)
#define USB_SERIAL_JTAG_OUT_EP1_STATE_V 0x00000003
#define USB_SERIAL_JTAG_OUT_EP1_STATE_S 0
/* USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [9:2]; default: 0;
* Write data address of OUT endpoint 1. When
* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are
* USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT
* EP1.
*/
#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S)
#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S 2
/* USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [16:9]; default: 0;
* Read data address of OUT endpoint
* 1.
*/
#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S)
#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S 9
/* USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [23:16]; default: 0;
* Data count in OUT endpoint 1 when one packet is
* received.
*/
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S)
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16
/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
* USB_SERIAL_JTAG_OUT_EP2_ST_REG.
*/
#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (SOC_DPORT_USB_BASE + 0x40)
/* USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [2:0]; default: 0;
* State of OUT Endpoint
* 2.
*/
#define USB_SERIAL_JTAG_OUT_EP2_STATE 0x00000003
#define USB_SERIAL_JTAG_OUT_EP2_STATE_M (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S)
#define USB_SERIAL_JTAG_OUT_EP2_STATE_V 0x00000003
#define USB_SERIAL_JTAG_OUT_EP2_STATE_S 0
/* USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [9:2]; default: 0;
* Write data address of OUT endpoint 2. When
* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are
* USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT
* EP2.
*/
#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S)
#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S 2
/* USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [16:9]; default: 0;
* Read data address of OUT endpoint
* 2.
*/
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S)
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007F
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9
/** Interrupt Registers */
/** USB_SERIAL_JTAG_INT_RAW_REG register
* USB_SERIAL_JTAG_INT_RAW_REG.
*/
#define USB_SERIAL_JTAG_INT_RAW_REG (SOC_DPORT_USB_BASE + 0x8)
/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt bit turns to high level when a flush command is
* received for IN endpoint 2 of
* JTAG.
*/
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0))
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S)
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x00000001
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0
/* USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt bit turns to high level when a SOF frame is
* received.
*/
#define USB_SERIAL_JTAG_SOF_INT_RAW (BIT(1))
#define USB_SERIAL_JTAG_SOF_INT_RAW_M (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S)
#define USB_SERIAL_JTAG_SOF_INT_RAW_V 0x00000001
#define USB_SERIAL_JTAG_SOF_INT_RAW_S 1
/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt bit turns to high level when the Serial Port OUT
* Endpoint received one
* packet.
*/
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2))
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S)
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x00000001
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2
/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1;
* The raw interrupt bit turns to high level when the Serial Port IN
* Endpoint is
* empty.
*/
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW (BIT(3))
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S)
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V 0x00000001
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S 3
/* USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
* The raw interrupt bit turns to high level when a PID error is
* detected.
*/
#define USB_SERIAL_JTAG_PID_ERR_INT_RAW (BIT(4))
#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S)
#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V 0x00000001
#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S 4
/* USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
* The raw interrupt bit turns to high level when a CRC5 error is
* detected.
*/
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5))
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S)
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x00000001
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5
/* USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
* The raw interrupt bit turns to high level when a CRC16 error is
* detected.
*/
#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW (BIT(6))
#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S)
#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V 0x00000001
#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S 6
/* USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
* The raw interrupt bit turns to high level when a bit stuffing error is
* detected.
*/
#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW (BIT(7))
#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S)
#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V 0x00000001
#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S 7
/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
* The raw interrupt bit turns to high level when an IN token for IN
* endpoint 1 is
* received.
*/
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8))
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S)
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x00000001
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8
/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
* The raw interrupt bit turns to high level when a USB bus reset is
* detected.
*/
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW (BIT(9))
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S)
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V 0x00000001
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S 9
/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
* The raw interrupt bit turns to high level when OUT endpoint 1 received
* packet with zero
* payload.
*/
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10))
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S)
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x00000001
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10
/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
* The raw interrupt bit turns to high level when OUT endpoint 2 received
* packet with zero
* payload.
*/
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11))
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S)
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x00000001
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11
/** USB_SERIAL_JTAG_INT_ST_REG register
* USB_SERIAL_JTAG_INT_ST_REG.
*/
#define USB_SERIAL_JTAG_INT_ST_REG (SOC_DPORT_USB_BASE + 0xc)
/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0))
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S)
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x00000001
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0
/* USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_SOF_INT_ST (BIT(1))
#define USB_SERIAL_JTAG_SOF_INT_ST_M (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S)
#define USB_SERIAL_JTAG_SOF_INT_ST_V 0x00000001
#define USB_SERIAL_JTAG_SOF_INT_ST_S 1
/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0;
* The raw interrupt status bit for the
* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2))
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S)
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x00000001
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2
/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0;
* The raw interrupt status bit for the
* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3))
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S)
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x00000001
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3
/* USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4))
#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S)
#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V 0x00000001
#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S 4
/* USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5))
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S)
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x00000001
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5
/* USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6))
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S)
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x00000001
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6
/* USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7))
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S)
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x00000001
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7
/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0;
* The raw interrupt status bit for the
* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8))
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S)
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x00000001
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8
/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9))
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S)
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x00000001
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9
/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0;
* The raw interrupt status bit for the
* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10))
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S)
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x00000001
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10
/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0;
* The raw interrupt status bit for the
* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11))
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S)
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11
/** USB_SERIAL_JTAG_INT_ENA_REG register
* USB_SERIAL_JTAG_INT_ENA_REG.
*/
#define USB_SERIAL_JTAG_INT_ENA_REG (SOC_DPORT_USB_BASE + 0x10)
/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0))
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S)
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x00000001
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0
/* USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_SOF_INT_ENA (BIT(1))
#define USB_SERIAL_JTAG_SOF_INT_ENA_M (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S)
#define USB_SERIAL_JTAG_SOF_INT_ENA_V 0x00000001
#define USB_SERIAL_JTAG_SOF_INT_ENA_S 1
/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the
* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2))
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S)
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x00000001
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2
/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3))
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S)
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x00000001
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3
/* USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4))
#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S)
#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x00000001
#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S 4
/* USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5))
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S)
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x00000001
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5
/* USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6))
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S)
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x00000001
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6
/* USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7))
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S)
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x00000001
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7
/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0;
* The interrupt enable bit for the
* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8))
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S)
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x00000001
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8
/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9))
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S)
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x00000001
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9
/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0;
* The interrupt enable bit for the
* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10))
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S)
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x00000001
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10
/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0;
* The interrupt enable bit for the
* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11))
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S)
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x00000001
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11
/** USB_SERIAL_JTAG_INT_CLR_REG register
* USB_SERIAL_JTAG_INT_CLR_REG.
*/
#define USB_SERIAL_JTAG_INT_CLR_REG (SOC_DPORT_USB_BASE + 0x14)
/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0))
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S)
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x00000001
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0
/* USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_SOF_INT_CLR (BIT(1))
#define USB_SERIAL_JTAG_SOF_INT_CLR_M (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S)
#define USB_SERIAL_JTAG_SOF_INT_CLR_V 0x00000001
#define USB_SERIAL_JTAG_SOF_INT_CLR_S 1
/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2))
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S)
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x00000001
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2
/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3))
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S)
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x00000001
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3
/* USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4))
#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S)
#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x00000001
#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S 4
/* USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5))
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S)
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x00000001
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5
/* USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6))
#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S)
#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x00000001
#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6
/* USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7))
#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S)
#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x00000001
#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7
/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8))
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S)
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x00000001
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8
/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9))
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S)
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x00000001
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9
/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10))
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S)
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x00000001
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10
/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
* interrupt.
*/
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11))
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S)
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x00000001
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11
/** Version Registers */
/** USB_SERIAL_JTAG_DATE_REG register
* USB_SERIAL_JTAG_DATE_REG.
*/
#define USB_SERIAL_JTAG_DATE_REG (SOC_DPORT_USB_BASE + 0x80)
/* USB_SERIAL_JTAG_DATE : R/W; bitpos: [32:0]; default: 33583872;
* register
* version.
*/
#define USB_SERIAL_JTAG_DATE 0xFFFFFFFF
#define USB_SERIAL_JTAG_DATE_M (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S)
#define USB_SERIAL_JTAG_DATE_V 0xFFFFFFFF
#define USB_SERIAL_JTAG_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32c3/include/soc/usb_serial_jtag_struct.h 100644
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// Copyright 2021 Espressif Systems (Shanghai) Co. Ltd.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_USB_SERIAL_JTAG_STRUCT_H_
#define _SOC_USB_SERIAL_JTAG_STRUCT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
union {
struct {
uint32_t rdwr_byte : 8; /*Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR and USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know how many data is received, then read that amount of data from UART Rx FIFO. */
uint32_t reserved8 : 24; /*reserved*/
};
uint32_t val;
} ep1;
union {
struct {
uint32_t wr_done : 1; /*Set this bit to indicate writing byte data to UART Tx FIFO is done. This bit then stays 0 until data in UART Tx FIFO is read by the USB Host.*/
uint32_t serial_in_ep_data_free : 1; /*1'b1: Indicate UART Tx FIFO is not full and data can be written into in. After writing USB_SERIAL_JTAG_WR_DONE, this will be 1’b0 until the data is sent to the USB Host.*/
uint32_t serial_out_ep_data_avail : 1; /*1'b1: Indicate there is data in UART Rx FIFO.*/
uint32_t reserved3 : 29; /*reserved*/
};
uint32_t val;
} ep1_conf;
union {
struct {
uint32_t jtag_in_flush_int_raw : 1; /*The raw interrupt bit turns to high level when a flush command is received for IN endpoint 2 of JTAG.*/
uint32_t sof_int_raw : 1; /*The raw interrupt bit turns to high level when a SOF frame is received.*/
uint32_t serial_out_recv_pkt_int_raw : 1; /*The raw interrupt bit turns to high level when the Serial Port OUT Endpoint received one packet.*/
uint32_t serial_in_empty_int_raw : 1; /*The raw interrupt bit turns to high level when the Serial Port IN Endpoint is empty.*/
uint32_t pid_err_int_raw : 1; /*The raw interrupt bit turns to high level when a PID error is detected.*/
uint32_t crc5_err_int_raw : 1; /*The raw interrupt bit turns to high level when a CRC5 error is detected.*/
uint32_t crc16_err_int_raw : 1; /*The raw interrupt bit turns to high level when a CRC16 error is detected.*/
uint32_t stuff_err_int_raw : 1; /*The raw interrupt bit turns to high level when a bit stuffing error is detected.*/
uint32_t in_token_rec_in_ep1_int_raw : 1; /*The raw interrupt bit turns to high level when an IN token for IN endpoint 1 is received.*/
uint32_t usb_bus_reset_int_raw : 1; /*The raw interrupt bit turns to high level when a USB bus reset is detected.*/
uint32_t out_ep1_zero_payload_int_raw : 1; /*The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero payload.*/
uint32_t out_ep2_zero_payload_int_raw : 1; /*The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero payload.*/
uint32_t reserved12 : 20; /*reserved*/
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t jtag_in_flush_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.*/
uint32_t sof_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.*/
uint32_t serial_out_recv_pkt_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.*/
uint32_t serial_in_empty_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.*/
uint32_t pid_err_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.*/
uint32_t crc5_err_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.*/
uint32_t crc16_err_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.*/
uint32_t stuff_err_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.*/
uint32_t in_token_rec_in_ep1_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.*/
uint32_t usb_bus_reset_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.*/
uint32_t out_ep1_zero_payload_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
uint32_t out_ep2_zero_payload_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
uint32_t reserved12 : 20; /*reserved*/
};
uint32_t val;
} int_st;
union {
struct {
uint32_t jtag_in_flush_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.*/
uint32_t sof_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.*/
uint32_t serial_out_recv_pkt_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.*/
uint32_t serial_in_empty_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.*/
uint32_t pid_err_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.*/
uint32_t crc5_err_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.*/
uint32_t crc16_err_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.*/
uint32_t stuff_err_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.*/
uint32_t in_token_rec_in_ep1_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.*/
uint32_t usb_bus_reset_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.*/
uint32_t out_ep1_zero_payload_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
uint32_t out_ep2_zero_payload_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
uint32_t reserved12 : 20; /*reserved*/
};
uint32_t val;
} int_ena;
union {
struct {
uint32_t jtag_in_flush_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.*/
uint32_t sof_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.*/
uint32_t serial_out_recv_pkt_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.*/
uint32_t serial_in_empty_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.*/
uint32_t pid_err_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.*/
uint32_t crc5_err_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.*/
uint32_t crc16_err_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.*/
uint32_t stuff_err_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.*/
uint32_t in_token_rec_in_ep1_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.*/
uint32_t usb_bus_reset_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.*/
uint32_t out_ep1_zero_payload_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
uint32_t out_ep2_zero_payload_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
uint32_t reserved12 : 20; /*reserved*/
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t phy_sel : 1; /*Select internal/external PHY. 1’b0: internal PHY, 1’b1: external PHY*/
uint32_t exchg_pins_override : 1; /*Enable software control USB D+ D- exchange*/
uint32_t exchg_pins : 1; /*USB D+ D- exchange*/
uint32_t vrefh : 2; /*Control single-end input high threshold. 1.76V to 2V, step 80mV */
uint32_t vrefl : 2; /*Control single-end input low threshold. 0.8V to 1.04V, step 80mV*/
uint32_t vref_override : 1; /*Enable software control input threshold*/
uint32_t pad_pull_override : 1; /*Enable software control USB D+ D- pullup pulldown*/
uint32_t dp_pullup : 1; /*Control USB D+ pull up.*/
uint32_t dp_pulldown : 1; /*Control USB D+ pull down.*/
uint32_t dm_pullup : 1; /*Control USB D- pull up.*/
uint32_t dm_pulldown : 1; /*Control USB D- pull down.*/
uint32_t pullup_value : 1; /*Control pull up value.*/
uint32_t usb_pad_enable : 1; /*Enable USB pad function.*/
uint32_t reserved15 : 17;
};
uint32_t val;
} conf0;
union {
struct {
uint32_t test_enable : 1; /*Enable test of the USB pad*/
uint32_t test_usb_oe : 1; /*USB pad oen in test*/
uint32_t test_tx_dp : 1; /*USB D+ tx value in test*/
uint32_t test_tx_dm : 1; /*USB D- tx value in test*/
uint32_t reserved4 : 28;
};
uint32_t val;
} test;
union {
struct {
uint32_t in_fifo_cnt : 2; /*JTAG in fifo counter.*/
uint32_t in_fifo_empty : 1; /*1: JTAG in fifo is empty.*/
uint32_t in_fifo_full : 1; /*1: JTAG in fifo is full.*/
uint32_t out_fifo_cnt : 2; /*JTAT out fifo counter.*/
uint32_t out_fifo_empty : 1; /*1: JTAG out fifo is empty.*/
uint32_t out_fifo_full : 1; /*1: JTAG out fifo is full.*/
uint32_t in_fifo_reset : 1; /*Write 1 to reset JTAG in fifo.*/
uint32_t out_fifo_reset : 1; /*Write 1 to reset JTAG out fifo.*/
uint32_t reserved10 : 22;
};
uint32_t val;
} jfifo_st;
union {
struct {
uint32_t sof_frame_index : 11; /*Frame index of received SOF frame.*/
uint32_t reserved11 : 21;
};
uint32_t val;
} fram_num;
union {
struct {
uint32_t in_ep0_state : 2; /*State of IN Endpoint 0.*/
uint32_t in_ep0_wr_addr : 7; /*Write data address of IN endpoint 0.*/
uint32_t in_ep0_rd_addr : 7; /*Read data address of IN endpoint 0.*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} in_ep0_st;
union {
struct {
uint32_t in_ep1_state : 2; /*State of IN Endpoint 1.*/
uint32_t in_ep1_wr_addr : 7; /*Write data address of IN endpoint 1.*/
uint32_t in_ep1_rd_addr : 7; /*Read data address of IN endpoint 1.*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} in_ep1_st;
union {
struct {
uint32_t in_ep2_state : 2; /*State of IN Endpoint 2.*/
uint32_t in_ep2_wr_addr : 7; /*Write data address of IN endpoint 2.*/
uint32_t in_ep2_rd_addr : 7; /*Read data address of IN endpoint 2.*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} in_ep2_st;
union {
struct {
uint32_t in_ep3_state : 2; /*State of IN Endpoint 3.*/
uint32_t in_ep3_wr_addr : 7; /*Write data address of IN endpoint 3.*/
uint32_t in_ep3_rd_addr : 7; /*Read data address of IN endpoint 3.*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} in_ep3_st;
union {
struct {
uint32_t out_ep0_state : 2; /*State of OUT Endpoint 0.*/
uint32_t out_ep0_wr_addr : 7; /*Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. */
uint32_t out_ep0_rd_addr : 7; /*Read data address of OUT endpoint 0.*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} out_ep0_st;
union {
struct {
uint32_t out_ep1_state : 2; /*State of OUT Endpoint 1.*/
uint32_t out_ep1_wr_addr : 7; /*Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.*/
uint32_t out_ep1_rd_addr : 7; /*Read data address of OUT endpoint 1.*/
uint32_t out_ep1_rec_data_cnt : 7; /*Data count in OUT endpoint 1 when one packet is received.*/
uint32_t reserved23 : 9; /*reserved*/
};
uint32_t val;
} out_ep1_st;
union {
struct {
uint32_t out_ep2_state : 2; /*State of OUT Endpoint 2.*/
uint32_t out_ep2_wr_addr : 7; /*Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.*/
uint32_t out_ep2_rd_addr : 7; /*Read data address of OUT endpoint 2.*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} out_ep2_st;
union {
struct {
uint32_t clk_en : 1; /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/
uint32_t reserved1 : 31;
};
uint32_t val;
} misc_conf;
union {
struct {
uint32_t usb_mem_pd : 1; /*1: power down usb memory.*/
uint32_t usb_mem_clk_en : 1; /*1: Force clock on for usb memory.*/
uint32_t reserved2 : 30;
};
uint32_t val;
} mem_conf;
uint32_t reserved_4c;
uint32_t reserved_50;
uint32_t reserved_54;
uint32_t reserved_58;
uint32_t reserved_5c;
uint32_t reserved_60;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t date;
} usb_serial_jtag_dev_t;
extern usb_serial_jtag_dev_t USB_SERIAL_JTAG;
#ifdef __cplusplus
}
#endif
#endif /*_SOC_USB_SERIAL_JTAG_STRUCT_H_ */

4
components/vfs/CMakeLists.txt
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@ -8,6 +8,10 @@ if(CONFIG_ESP_CONSOLE_USB_CDC)
target_sources(${COMPONENT_LIB} PRIVATE "vfs_cdcacm.c")
endif()
if(CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG)
target_sources(${COMPONENT_LIB} PRIVATE "vfs_usb_serial_jtag.c")
endif()
# Some newlib syscalls are implemented in vfs.c, make sure these are always
# seen by the linker
target_link_libraries(${COMPONENT_LIB} INTERFACE "-u vfs_include_syscalls_impl")

3
components/vfs/component.mk
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@ -1,3 +1,6 @@
ifndef CONFIG_ESP_CONSOLE_USB_CDC
COMPONENT_OBJEXCLUDE := vfs_cdcacm.o
endif
ifndef CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
COMPONENT_OBJEXCLUDE := vfs_usb_serial_jtag.o
endif

66
components/vfs/include/esp_vfs_usb_serial_jtag.h 100644
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@ -0,0 +1,66 @@
// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include "esp_err.h"
#include "esp_vfs.h"
#include "esp_vfs_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief add /dev/usbserjtag virtual filesystem driver
*
* This function is called from startup code to enable console output
*/
esp_err_t esp_vfs_dev_usb_serial_jtag_register(void);
/**
* @brief Set the line endings expected to be received
*
* This specifies the conversion between line endings received and
* newlines ('\n', LF) passed into stdin:
*
* - ESP_LINE_ENDINGS_CRLF: convert CRLF to LF
* - ESP_LINE_ENDINGS_CR: convert CR to LF
* - ESP_LINE_ENDINGS_LF: no modification
*
* @note this function is not thread safe w.r.t. reading
*
* @param mode line endings expected
*/
void esp_vfs_dev_usb_serial_jtag_set_rx_line_endings(esp_line_endings_t mode);
/**
* @brief Set the line endings to sent
*
* This specifies the conversion between newlines ('\n', LF) on stdout and line
* endings sent:
*
* - ESP_LINE_ENDINGS_CRLF: convert LF to CRLF
* - ESP_LINE_ENDINGS_CR: convert LF to CR
* - ESP_LINE_ENDINGS_LF: no modification
*
* @note this function is not thread safe w.r.t. writing
*
* @param mode line endings to send
*/
void esp_vfs_dev_usb_serial_jtag_set_tx_line_endings(esp_line_endings_t mode);
#ifdef __cplusplus
}
#endif

385
components/vfs/vfs_usb_serial_jtag.c 100644
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@ -0,0 +1,385 @@
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//This is a simple non-blocking (well, tx may spin for a bit if the buffer
//is full) USB-serial-jtag driver. Select etc is not supported yet.
#include <string.h>
#include <stdbool.h>
#include <stdarg.h>
#include <sys/errno.h>
#include <sys/lock.h>
#include <sys/fcntl.h>
#include <sys/param.h>
#include "esp_timer.h"
#include "esp_vfs.h"
#include "esp_vfs_dev.h"
#include "esp_attr.h"
#include "sdkconfig.h"
#include "soc/soc_caps.h"
#include "hal/usb_serial_jtag_ll.h"
// Token signifying that no character is available
#define NONE -1
#if CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF
# define DEFAULT_TX_MODE ESP_LINE_ENDINGS_CRLF
#elif CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR
# define DEFAULT_TX_MODE ESP_LINE_ENDINGS_CR
#else
# define DEFAULT_TX_MODE ESP_LINE_ENDINGS_LF
#endif
#if CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF
# define DEFAULT_RX_MODE ESP_LINE_ENDINGS_CRLF
#elif CONFIG_NEWLIB_STDIN_LINE_ENDING_CR
# define DEFAULT_RX_MODE ESP_LINE_ENDINGS_CR
#else
# define DEFAULT_RX_MODE ESP_LINE_ENDINGS_LF
#endif
// write bytes function type
typedef void (*tx_func_t)(int, int);
// read bytes function type
typedef int (*rx_func_t)(int);
// Basic functions for sending and receiving bytes
static void usb_serial_jtag_tx_char(int fd, int c);
static int usb_serial_jtag_rx_char(int fd);
//If no host is listening to the CDCACM port, the TX buffer
//will never be able to flush to the host. Instead of the Tx
//routines waiting forever, if the buffer hasn't been flushed
//to the host the tx routine will fail fast. (Note that as
//soon as something starts listening, the CDCACM port will
//start working as normal again.)
#define TX_FLUSH_TIMEOUT_US (50*1000LL)
//(As a reference, you'd expect an unloaded usb bus to try to
//pick up tx data once every USB frame, aka every 1ms. We take a
//longer timeout to allow for a loaded bus.)
typedef struct {
// One-character buffer used for newline conversion code
int peek_char;
// Read and write locks, lazily initialized
_lock_t read_lock;
_lock_t write_lock;
// Non-blocking flag. Note: default implementation does not honor this
// flag, all reads are non-blocking. ToDo: implement driver that honours this.
bool non_blocking;
// Newline conversion mode when transmitting
esp_line_endings_t tx_mode;
// Newline conversion mode when receiving
esp_line_endings_t rx_mode;
// Functions used to write bytes to port. Default to "basic" functions.
tx_func_t tx_func;
// Functions used to read bytes from port. Default to "basic" functions.
rx_func_t rx_func;
// Timestamp of last time we managed to write something to the tx buffer
int64_t last_tx_ts;
} vfs_usb_serial_jtag_context_t;
//If the context should be dynamically initialized, remove this structure
//and point s_ctx to allocated data.
static vfs_usb_serial_jtag_context_t s_ctx = {
.peek_char = NONE,
.tx_mode = DEFAULT_TX_MODE,
.rx_mode = DEFAULT_RX_MODE,
.tx_func = usb_serial_jtag_tx_char,
.rx_func = usb_serial_jtag_rx_char
};
static int usb_serial_jtag_open(const char * path, int flags, int mode)
{
s_ctx.non_blocking = ((flags & O_NONBLOCK) == O_NONBLOCK);
return 0;
}
static void usb_serial_jtag_tx_char(int fd, int c)
{
uint8_t cc=(uint8_t)c;
if (usb_serial_jtag_ll_txfifo_writable()) {
//We can write to the buffer. Immediately do so.
usb_serial_jtag_ll_write_txfifo(&cc, 1);
s_ctx.last_tx_ts = esp_timer_get_time();
} else {
//Try to write to the buffer as long as we still expect the buffer to have
//a chance of being emptied by an active host. Just drop the data if there's
//no chance anymore.
while ((esp_timer_get_time() - s_ctx.last_tx_ts) < TX_FLUSH_TIMEOUT_US) {
if (usb_serial_jtag_ll_txfifo_writable()) {
//Woohoo, we can write again. Do so and exit the while loop.
usb_serial_jtag_ll_write_txfifo(&cc, 1);
s_ctx.last_tx_ts = esp_timer_get_time();
break;
}
}
}
}
static int usb_serial_jtag_rx_char(int fd)
{
uint8_t c;
int l = usb_serial_jtag_ll_read_rxfifo(&c, 1);
if (l == 0) {
return NONE;
}
return c;
}
static ssize_t usb_serial_jtag_write(int fd, const void * data, size_t size)
{
const char *data_c = (const char *)data;
/* Even though newlib does stream locking on each individual stream, we need
* a dedicated lock if two streams (stdout and stderr) point to the
* same port.
*/
_lock_acquire_recursive(&s_ctx.write_lock);
for (size_t i = 0; i < size; i++) {
int c = data_c[i];
if (c == '\n' && s_ctx.tx_mode != ESP_LINE_ENDINGS_LF) {
s_ctx.tx_func(fd, '\r');
if (s_ctx.tx_mode == ESP_LINE_ENDINGS_CR) {
continue;
}
}
s_ctx.tx_func(fd, c);
if (c == '\n') {
//Make sure line doesn't linger in fifo
usb_serial_jtag_ll_txfifo_flush();
}
}
_lock_release_recursive(&s_ctx.write_lock);
return size;
}
/* Helper function which returns a previous character or reads a new one from
* the port. Previous character can be returned ("pushed back") using
* usb_serial_jtag_return_char function.
*/
static int usb_serial_jtag_read_char(int fd)
{
/* return character from peek buffer, if it is there */
if (s_ctx.peek_char != NONE) {
int c = s_ctx.peek_char;
s_ctx.peek_char = NONE;
return c;
}
return s_ctx.rx_func(fd);
}
/* Push back a character; it will be returned by next call to usb_serial_jtag_read_char */
static void usb_serial_jtag_return_char(int fd, int c)
{
assert(s_ctx.peek_char == NONE);
s_ctx.peek_char = c;
}
static ssize_t usb_serial_jtag_read(int fd, void* data, size_t size)
{
char *data_c = (char *) data;
size_t received = 0;
_lock_acquire_recursive(&s_ctx.read_lock);
while (received < size) {
int c = usb_serial_jtag_read_char(fd);
if (c == '\r') {
if (s_ctx.rx_mode == ESP_LINE_ENDINGS_CR) {
c = '\n';
} else if (s_ctx.rx_mode == ESP_LINE_ENDINGS_CRLF) {
/* look ahead */
int c2 = usb_serial_jtag_read_char(fd);
if (c2 == NONE) {
/* could not look ahead, put the current character back */
usb_serial_jtag_return_char(fd, c);
break;
}
if (c2 == '\n') {
/* this was \r\n sequence. discard \r, return \n */
c = '\n';
} else {
/* \r followed by something else. put the second char back,
* it will be processed on next iteration. return \r now.
*/
usb_serial_jtag_return_char(fd, c2);
}
}
} else if (c == NONE) {
break;
}
data_c[received] = (char) c;
++received;
if (c == '\n') {
break;
}
}
_lock_release_recursive(&s_ctx.read_lock);
if (received > 0) {
return received;
}
errno = EWOULDBLOCK;
return -1;
}
static int usb_serial_jtag_fstat(int fd, struct stat * st)
{
memset(st, 0, sizeof(*st));
st->st_mode = S_IFCHR;
return 0;
}
static int usb_serial_jtag_close(int fd)
{
return 0;
}
static int usb_serial_jtag_fcntl(int fd, int cmd, int arg)
{
int result = 0;
if (cmd == F_GETFL) {
if (s_ctx.non_blocking) {
result |= O_NONBLOCK;
}
} else if (cmd == F_SETFL) {
s_ctx.non_blocking = (arg & O_NONBLOCK) != 0;
} else {
// unsupported operation
result = -1;
errno = ENOSYS;
}
return result;
}
static int usb_serial_jtag_fsync(int fd)
{
_lock_acquire_recursive(&s_ctx.write_lock);
usb_serial_jtag_ll_txfifo_flush();
//Wait for the host to have picked up the buffer, but honour the timeout in
//case the host is not listening.
while ((esp_timer_get_time() - s_ctx.last_tx_ts) < TX_FLUSH_TIMEOUT_US) {
if (usb_serial_jtag_ll_txfifo_writable()) {
s_ctx.last_tx_ts = esp_timer_get_time();
break;
}
}
_lock_release_recursive(&s_ctx.write_lock);
return 0;
}
#ifdef CONFIG_VFS_SUPPORT_TERMIOS
static int usb_serial_jtag_tcsetattr(int fd, int optional_actions, const struct termios *p)
{
if (p == NULL) {
errno = EINVAL;
return -1;
}
switch (optional_actions) {
case TCSANOW:
// nothing to do
break;
case TCSADRAIN:
usb_serial_jtag_fsync(fd);
break;
case TCSAFLUSH:
// Not applicable.
break;
default:
errno = EINVAL;
return -1;
}
if (p->c_iflag & IGNCR) {
s_ctx.rx_mode = ESP_LINE_ENDINGS_CRLF;
} else if (p->c_iflag & ICRNL) {
s_ctx.rx_mode = ESP_LINE_ENDINGS_CR;
} else {
s_ctx.rx_mode = ESP_LINE_ENDINGS_LF;
}
return 0;
}
static int usb_serial_jtag_tcgetattr(int fd, struct termios *p)
{
if (p == NULL) {
errno = EINVAL;
return -1;
}
memset(p, 0, sizeof(struct termios));
if (s_ctx.rx_mode == ESP_LINE_ENDINGS_CRLF) {
p->c_iflag |= IGNCR;
} else if (s_ctx.rx_mode == ESP_LINE_ENDINGS_CR) {
p->c_iflag |= ICRNL;
}
//Dummy values that vaguely make sense on a not-actually-rs232 port.
//Should be good enough to keep software that expects an actual
//serial port happy.
p->c_cflag &= (~CSIZE);
p->c_cflag |= CS8;
p->c_ispeed = p->c_ospeed = 1000000;
return 0;
}
static int usb_serial_jtag_tcdrain(int fd)
{
usb_serial_jtag_fsync(fd);
return 0;
}
static int usb_serial_jtag_tcflush(int fd, int select)
{
//Flushing is not supported.
errno = EINVAL;
return -1;
}
#endif // CONFIG_VFS_SUPPORT_TERMIOS
void esp_vfs_dev_usb_serial_jtag_set_tx_line_endings(esp_line_endings_t mode)
{
s_ctx.tx_mode = mode;
}
void esp_vfs_dev_usb_serial_jtag_set_rx_line_endings(esp_line_endings_t mode)
{
s_ctx.rx_mode = mode;
}
esp_err_t esp_vfs_dev_usb_serial_jtag_register(void)
{
esp_vfs_t vfs = {
.flags = ESP_VFS_FLAG_DEFAULT,
.write = &usb_serial_jtag_write,
.open = &usb_serial_jtag_open,
.fstat = &usb_serial_jtag_fstat,
.close = &usb_serial_jtag_close,
.read = &usb_serial_jtag_read,
.fcntl = &usb_serial_jtag_fcntl,
.fsync = &usb_serial_jtag_fsync,
#ifdef CONFIG_VFS_SUPPORT_TERMIOS
.tcsetattr = &usb_serial_jtag_tcsetattr,
.tcgetattr = &usb_serial_jtag_tcgetattr,
.tcdrain = &usb_serial_jtag_tcdrain,
.tcflush = &usb_serial_jtag_tcflush,
#endif // CONFIG_VFS_SUPPORT_TERMIOS
};
// "/dev/usb_serial_jtag" unfortunately is too long for vfs
return esp_vfs_register("/dev/usbserjtag", &vfs, NULL);
}

9
docs/conf_common.py
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@ -163,12 +163,13 @@ LEGACY_DOCS = ['api-guides/build-system-legacy.rst',
'get-started-legacy/**']
USB_DOCS = ['api-reference/peripherals/usb.rst',
'api-guides/usb-console.rst',
'api-guides/usb-otg-console.rst',
'api-guides/dfu.rst']
FTDI_JTAG_DOCS = ['api-guides/jtag-debugging/configure-ft2232h-jtag.rst']
BUILTIN_JTAG_DOCS = ['api-guides/jtag-debugging/configure-builtin-jtag.rst']
USB_SERIAL_JTAG_DOCS = ['api-guides/jtag-debugging/configure-builtin-jtag.rst',
'api-guides/usb-serial-jtag-console.rst']
ULP_DOCS = ['api-guides/ulp.rst', 'api-guides/ulp_macros.rst']
@ -200,7 +201,8 @@ ESP32S2_DOCS = ['hw-reference/esp32s2/**',
'api-reference/peripherals/touch_element.rst',
'api-reference/peripherals/dac.rst'] + FTDI_JTAG_DOCS
ESP32C3_DOCS = ['hw-reference/esp32c3/**'] + BUILTIN_JTAG_DOCS
# No JTAG docs for this one as it gets gated on SOC_USB_SERIAL_JTAG_SUPPORTED down below.
ESP32C3_DOCS = ['hw-reference/esp32c3/**']
# format: {tag needed to include: documents to included}, tags are parsed from sdkconfig and peripheral_caps.h headers
conditional_include_dict = {'SOC_BT_SUPPORTED':BT_DOCS,
@ -208,6 +210,7 @@ conditional_include_dict = {'SOC_BT_SUPPORTED':BT_DOCS,
'SOC_SDIO_SLAVE_SUPPORTED':SDIO_SLAVE_DOCS,
'SOC_MCPWM_SUPPORTED':MCPWM_DOCS,
'SOC_USB_SUPPORTED':USB_DOCS,
'SOC_USB_SERIAL_JTAG_SUPPORTED':USB_SERIAL_JTAG_DOCS,
'SOC_DEDICATED_GPIO_SUPPORTED':DEDIC_GPIO_DOCS,
'SOC_SPIRAM_SUPPORTED':SPIRAM_DOCS,
'SOC_PCNT_SUPPORTED':PCNT_DOCS,

3
docs/en/api-guides/index.rst
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@ -41,5 +41,6 @@ API Guides
Unit Testing (Target) <unit-tests>
Unit Testing (Linux Host) <linux-host-testing>
:esp32: Unit Testing (Legacy GNU Make) <unit-tests-legacy>
:SOC_USB_SUPPORTED: USB Console <usb-console>
:SOC_USB_SUPPORTED: USB OTG Console <usb-otg-console>
:SOC_USB_SERIAL_JTAG_SUPPORTED: USB Serial/JTAG Controller Console <usb-serial-jtag-console>
WiFi Driver <wifi>

8
docs/en/api-guides/usb-console.rst → docs/en/api-guides/usb-otg-console.rst
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@ -1,6 +1,6 @@
***********
USB Console
***********
***************
USB OTG Console
***************
On chips with an integrated USB peripheral, it is possible to use USB Communication Device Class (CDC) to implement the serial console, instead of using UART with an external USB-UART bridge chip. {IDF_TARGET_NAME} ROM code contains a USB CDC implementation, which supports for some basic functionality without requiring the application to include the USB stack:
@ -15,7 +15,7 @@ On chips with an integrated USB peripheral, it is possible to use USB Communicat
Hardware Requirements
=====================
Connect ESP32-S2 to the USB port as follows
Connect {IDF_TARGET_NAME} to the USB port as follows
+------+-------------+
| GPIO | USB |

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**********************************
USB Serial/JTAG Controller Console
**********************************
On chips with an integrated USB Serial/JTAG Controller, it is possible to use the part of this controller that implements a serial port (CDC) to implement the serial console, instead of using UART with an external USB-UART bridge chip. {IDF_TARGET_NAME} contains this controller, providing the following functions:
* Bidirectional serial console, which can be used with :doc:`IDF Monitor <tools/idf-monitor>` or another serial monitor
* Flashing using ``esptool.py`` and ``idf.py flash``.
* JTAG debugging using e.g. OpenOCD, simultaneous with serial operations
Note that, in contrast with the USB OTG peripheral found in some Espressif chips, the USB Serial/JTAG Controller is a fixed function device, implemented entirely in hardware. This means it cannot be reconfigured to perform any function other than to provide a serial channel and JTAG debugging functionality.
Hardware Requirements
=====================
Connect {IDF_TARGET_NAME} to the USB port as follows:
+------+-------------+
| GPIO | USB |
+======+=============+
| 19 | D+ (green) |
+------+-------------+
| 18 | D- (white) |
+------+-------------+
| GND | GND (black) |
+------+-------------+
| | +5V (red) |
+------+-------------+
Some development boards may offer a USB connector for the USB Serial/JTAG Controller — in that case, no extra connections are required.
Software Configuration
======================
USB console feature can be enabled using ``CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG`` option in menuconfig tool (see :ref:`CONFIG_ESP_CONSOLE_UART`).
Once the option is enabled, build the project as usual.
Uploading the Application
=========================
The USB Serial/JTAG Controller is able to put the {IDF_TARGET_NAME} into download mode automatically. Simply flash as usual, but specify the USB Serial/JTAG Controller port on your system: ``idf.py flash -p PORT`` where ``PORT`` is the name of the proper port.
Limitations
===========
There are several limitations to the USB console feature. These may or may not be significant, depending on the type of application being developed, and the development workflow.
1. If the application accidentally reconfigures the USB peripheral pins, or disables the USB Serial/JTAG Controller, the device will disappear from the system. After fixing the issue in the application, you will need to manually put the {IDF_TARGET_NAME} into download mode by pulling low GPIO0 and resetting the chip.
2. If the application enters light sleep (including automatic light sleep) or deep sleep mode, USB CDC device will disappear from the system.
3. The behaviour between an actual USB-to-serial bridge chip and the USB Serial/JTAG Controller is slightly different if the ESP-IDF application does not listen for incoming bytes. An USB-to-serial bridge chip will just send the bytes to a (not listening) chip, while the USB Serial/JTAG Controller will block until the application reads the bytes. This can lead to a non-responsive looking terminal program.

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@ -41,5 +41,6 @@ API 指南
单元测试 (Target) <unit-tests>
单元测试 (Linux Host) <linux-host-testing>
:esp32: 单元测试 (传统 GNU Make) <unit-tests-legacy>
:esp32s2: USB 控制台 <usb-console>
:SOC_USB_SUPPORTED: USB 控制台 <usb-otg-console>
:SOC_USB_SERIAL_JTAG_SUPPORTED: USB Serial/JTAG Controller Console <usb-serial-jtag-console>
Wi-Fi 驱动 <wifi>

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.. include:: ../../en/api-guides/usb-console.rst

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.. include:: ../../en/api-guides/usb-otg-console.rst

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.. include:: ../../en/api-guides/usb-serial-jtag-console.rst

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CONFIG_IDF_TARGET="esp32c3"
CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y