If a windowoverflow8 happened after changing the SP, the exception handler would look for
the extra save area by looking at the previous frame's SP. This SP would be a garbage value
and could cause the windowoverflow exception to write to invalid memory ares.
The Xtensa FreeRTOS port does not save the threadptr register when
doing a voluntary yield. This can result in a crash when multiple
tasks used the threadptr register and call "taskYIELD()".
This commit adds the threadptr register to the solicited stack frame.
The compiler was not informed that the assembly block should be
treated as a memory barrier and could optimize out the initialization
of local arrays which could be used as semihosting arguments.
This resulted in garbage values being passed as semihosting call
arguments.
Additionally this commit changes the approach for placing values into
specific register. Instead of clobbers, local register variables are
used. This results in simpler generated code, since the compiler is
able to place values directly into the registers used for semihosting
arguments, avoiding additional moves.
From LX7_ESP32_S3_MP_linux_redist.tgz with SHA256:
63f305a982b2ee94cc78e5c20e3e3eb8bf0edeeaf703af0227a418bc34f7b848
copied from xtensa-elf/arch/include/xtensa/config/ with changes:
1) pre-commit fixes applied
2) re-added CONFIGID0 and CONFIGID1 in specreg.h
* Patched longjmp to be context-switch safe
longjmp modifies the windowbase and windowstart
registers, which isn't safe if a context switch
occurs during the modification. After a context
switch, windowstart and windowbase will be
different, leading to a wrongly set windowstart
bit due to longjmp writing it based on the
windowbase before the context switch. This
corrupts the registers at the next window
overflow reaching that wrongly set bit.
The solution is to disable interrupts during
this code. It is only 6 instructions long,
the impact shouldn't be significant.
The fix is implemented as a wrapper which
replaces the original first instructions of
longjmp which are buggy. Then, it jumps back
to execute the rest of the original longjmp
function.
Added a comparably reliable test to the
test apps.
* Functions for setting and clearing interrupts
as well as function to read interrupt mask
should be clearer now.
* Using hal layer interrupt set and clear
functions in esp_wifi component
Enable shared stack watchpoint for overflow detection
Enable unit tests:
* "test printf using shared buffer stack" for C3
* "Test vTaskDelayUntil" for S2
* "UART can do poll()" for C3
esp_system: removed repeated interrupt allocator code and moved common code to esp_system
xtens: moved xtensa specific code from freertos to the xtensa component
hal/interrupt_controller: added interrupt controller hal and ll files
docs: update the doxyfile with new location of esp_itr_alloc.h file
xtensa: fixed dangerous relocation problem after moving xtensa interrupt files out of freertos
docs: removed Xtensa reference from intr_allocator api-reference
xtensa: pushed the interrupt function that manages non iram interrupts to the xtensa layer
esp_system/test: fixed platform dependent setting for intr_allocator tests
hal: rename the functions used to manage non iram interrupt mask.
esp_common/shared_stack: refactored the implemenation of shared stack function (still not working properly)
esp_expression_with_stack: refactored the shared stack function calling mechanism and updated the documentation
If esp_restart_noos() is run and the stack address points to external memory (SPIRAM)
then Cache_Read_Disable() raises up the error "Cache disabled but cached memory region accessed"
to fix this we switch stack to internal RAM before disable cache.
Added unit tests.
Closes: https://github.com/espressif/esp-idf/issues/5107
Omar Chebib