esp32h2: add some more fixes and TODOs

2021-06-28 17:51:48 +08:00 · 2021-06-28 17:51:48 +08:00 · 75bd02bd46
commit 75bd02bd46
--- a/2
+++ b/2
@ -68,7 +68,7 @@ mainmenu "Espressif IoT Development Framework Configuration"
        default 0x0002 if IDF_TARGET_ESP32S2
        default 0x0005 if IDF_TARGET_ESP32C3
        default 0x0009 if IDF_TARGET_ESP32S3
-        default 0x000A if IDF_TARGET_ESP32H2
+        default 0x000A if IDF_TARGET_ESP32H2 # ESP32H2-TODO: IDF-3475
        default 0xFFFF

    menu "SDK tool configuration"
--- a/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld
+++ b/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld
@ -170,7 +170,6 @@ SECTIONS

 }

-/* ESP32H2-TODO: IDF-3466 */
 /**
 *  Appendix: Memory Usage of ROM bootloader
 *
--- a/components/bootloader_support/include/esp_app_format.h
+++ b/components/bootloader_support/include/esp_app_format.h
@ -16,7 +16,7 @@ typedef enum {
    ESP_CHIP_ID_ESP32S2 = 0x0002,  /*!< chip ID: ESP32-S2 */
    ESP_CHIP_ID_ESP32C3 = 0x0005, /*!< chip ID: ESP32-C3 */
    ESP_CHIP_ID_ESP32S3 = 0x0009, /*!< chip ID: ESP32-S3 */
-    ESP_CHIP_ID_ESP32H2 = 0x000A, /*!< chip ID: ESP32-H2 */
+    ESP_CHIP_ID_ESP32H2 = 0x000A, /*!< chip ID: ESP32-H2 */  // ESP32H2-TODO: IDF-3475
    ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */
 } __attribute__((packed)) esp_chip_id_t;

--- a/components/esp_event/event_send.c
+++ b/components/esp_event/event_send.c
@ -28,6 +28,7 @@ esp_err_t esp_event_send_noop(system_event_t *event)
    return ESP_OK;
 }

+#if CONFIG_ESP32_WIFI_ENABLED
 static system_event_id_t esp_event_legacy_wifi_event_id(int32_t event_id)
 {
    switch (event_id) {
@ -102,6 +103,7 @@ static system_event_id_t esp_event_legacy_wifi_event_id(int32_t event_id)
        return SYSTEM_EVENT_MAX;
    }
 }
+#endif // CONFIG_ESP32_WIFI_ENABLED

 static system_event_id_t esp_event_legacy_ip_event_id(int32_t event_id)
 {
@ -133,9 +135,13 @@ static system_event_id_t esp_event_legacy_ip_event_id(int32_t event_id)

 static system_event_id_t esp_event_legacy_event_id(esp_event_base_t event_base, int32_t event_id)
 {
+#if CONFIG_ESP32_WIFI_ENABLED
    if (event_base == WIFI_EVENT) {
        return esp_event_legacy_wifi_event_id(event_id);
-    } else if (event_base == IP_EVENT) {
+    }
+#endif
+
+	if (event_base == IP_EVENT) {
        return esp_event_legacy_ip_event_id(event_id);
    } else {
        ESP_LOGE(TAG, "invalid event base %s", event_base);
--- a/components/esp_wifi/Kconfig
+++ b/components/esp_wifi/Kconfig
@ -8,7 +8,7 @@ menu "Wi-Fi"

    config ESP32_WIFI_SW_COEXIST_ENABLE
        bool "Software controls WiFi/Bluetooth coexistence"
-        depends on BT_ENABLED
+        depends on ESP32_WIFI_ENABLED && BT_ENABLED
        default y
        help
            If enabled, WiFi & Bluetooth coexistence is controlled by software rather than hardware.
--- a/components/hal/esp32h2/include/hal/adc_ll.h
+++ b/components/hal/esp32h2/include/hal/adc_ll.h
@ -444,7 +444,8 @@ static inline void adc_ll_digi_reset(void)
 static inline void adc_ll_pwdet_set_cct(uint32_t cct)
 {
    /* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */
-    // RTCCNTL.sensor_ctrl.sar2_pwdet_cct = cct; // ESP32H2-TODO: IDF-3389
+    // RTCCNTL.sensor_ctrl.sar2_pwdet_cct = cct;
+    abort();  // ESP32H2-TODO: IDF-3389
 }

 /**
@ -457,7 +458,8 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
 {
    /* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */
    // return RTCCNTL.sensor_ctrl.sar2_pwdet_cct;
-    return 0; // ESP32H2-TODO: IDF-3389
+    abort();  // ESP32H2-TODO: IDF-3389
+    return 0;
 }

 /**
--- a/components/hal/esp32h2/include/hal/rmt_ll.h
+++ b/components/hal/esp32h2/include/hal/rmt_ll.h
@ -15,8 +15,8 @@

 #include <stdint.h>
 #include <stdbool.h>
+#include <stddef.h>
 #include "soc/rmt_struct.h"
-#include "soc/soc_caps.h"

 #ifdef __cplusplus
 extern "C" {
@ -279,6 +279,15 @@ static inline uint32_t rmt_ll_rx_get_limit(rmt_dev_t *dev, uint32_t channel)
    return dev->rx_lim[channel].rx_lim;
 }

+static inline void rmt_ll_enable_interrupt(rmt_dev_t *dev, uint32_t mask, bool enable)
+{
+    if (enable) {
+        dev->int_ena.val |= mask;
+    } else {
+        dev->int_ena.val &= ~mask;
+    }
+}
+
 static inline void rmt_ll_enable_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
 {
    if (enable) {
@ -469,12 +478,14 @@ static inline void rmt_ll_tx_set_carrier_always_on(rmt_dev_t *dev, uint32_t chan
    dev->tx_conf[channel].carrier_eff_en = !enable;
 }

-//Writes items to the specified TX channel memory with the given offset and writen length.
+//Writes items to the specified TX channel memory with the given offset and length.
 //the caller should ensure that (length + off) <= (memory block * SOC_RMT_MEM_WORDS_PER_CHANNEL)
-static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const rmt_item32_t *data, uint32_t length, uint32_t off)
+static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const void *data, size_t length_in_words, size_t off)
 {
-    for (uint32_t i = 0; i < length; i++) {
-        mem->chan[channel].data32[i + off].val = data[i].val;
+    volatile uint32_t *to = (volatile uint32_t *)&mem->chan[channel].data32[off];
+    uint32_t *from = (uint32_t *)data;
+    while (length_in_words--) {
+        *to++ = *from++;
    }
 }

@ -483,20 +494,6 @@ static inline void rmt_ll_rx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, b
    dev->rx_conf[channel].conf1.mem_rx_wrap_en = enable;
 }

-/************************************************************************************************
- * Following Low Level APIs only used for backward compatible, will be deprecated in the IDF v5.0
- ***********************************************************************************************/
-
-static inline void rmt_ll_set_intr_enable_mask(uint32_t mask)
-{
-    RMT.int_ena.val |= mask;
-}
-
-static inline void rmt_ll_clr_intr_enable_mask(uint32_t mask)
-{
-    RMT.int_ena.val &= (~mask);
-}
-
 #ifdef __cplusplus
 }
 #endif
--- a/components/idf_test/include/esp32h2/idf_performance_target.h
+++ b/components/idf_test/include/esp32h2/idf_performance_target.h
@ -37,7 +37,7 @@
 #endif

 #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_WR_4B
-#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_WR_4B                      27400
+#define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_WR_4B                      0
 #endif
 #ifndef IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_RD_4B
 #define IDF_PERFORMANCE_MIN_FLASH_SPEED_BYTE_PER_SEC_RD_4B                      53600
--- a/components/riscv/CMakeLists.txt
+++ b/components/riscv/CMakeLists.txt
@ -1,5 +1,6 @@
 idf_build_get_property(target IDF_TARGET)

+# should test arch here not target: IDF-1754
 if(NOT "${target}" STREQUAL "esp32c3" AND NOT "${target}" STREQUAL "esp32h2")
    return()
 endif()
--- a/components/soc/esp32c3/include/soc/soc.h
+++ b/components/soc/esp32c3/include/soc/soc.h
@ -315,9 +315,7 @@
 #define ETS_FRC1_INUM                           22
 #define ETS_T1_WDT_INUM                         24
 #define ETS_CACHEERR_INUM                       25
-#ifdef CONFIG_IDF_TARGET_ESP32C3
 #define ETS_MEMPROT_ERR_INUM                    26
-#endif
 #define ETS_DPORT_INUM                          28

 //CPU0 Max valid interrupt number
--- a/components/soc/esp32h2/include/soc/soc.h
+++ b/components/soc/esp32h2/include/soc/soc.h
@ -346,9 +346,7 @@
 #define ETS_FRC1_INUM                           22
 #define ETS_T1_WDT_INUM                         24
 #define ETS_CACHEERR_INUM                       25
-#ifdef CONFIG_IDF_TARGET_ESP32H2
 #define ETS_MEMPROT_ERR_INUM                    26
-#endif
 #define ETS_DPORT_INUM                          28

 //CPU0 Max valid interrupt number
--- a/components/soc/esp32h2/rmt_periph.c
+++ b/components/soc/esp32h2/rmt_periph.c
@ -16,24 +16,28 @@
 #include "soc/gpio_sig_map.h"

 const rmt_signal_conn_t rmt_periph_signals = {
-    .module = PERIPH_RMT_MODULE,
-    .irq = ETS_RMT_INTR_SOURCE,
-    .channels = {
+    .groups = {
        [0] = {
-            .tx_sig = RMT_SIG_OUT0_IDX,
-            .rx_sig = -1
-        },
-        [1] = {
-            .tx_sig = RMT_SIG_OUT1_IDX,
-            .rx_sig = -1
-        },
-        [2] = {
-            .tx_sig = -1,
-            .rx_sig = RMT_SIG_IN0_IDX
-        },
-        [3] = {
-            .tx_sig = -1,
-            .rx_sig = RMT_SIG_IN1_IDX
-        },
+            .module = PERIPH_RMT_MODULE,
+            .irq = ETS_RMT_INTR_SOURCE,
+            .channels = {
+                [0] = {
+                    .tx_sig = RMT_SIG_OUT0_IDX,
+                    .rx_sig = -1
+                },
+                [1] = {
+                    .tx_sig = RMT_SIG_OUT1_IDX,
+                    .rx_sig = -1
+                },
+                [2] = {
+                    .tx_sig = -1,
+                    .rx_sig = RMT_SIG_IN0_IDX
+                },
+                [3] = {
+                    .tx_sig = -1,
+                    .rx_sig = RMT_SIG_IN1_IDX
+                },
+            }
+        }
    }
 };
--- a/components/xtensa/CMakeLists.txt
+++ b/components/xtensa/CMakeLists.txt
@ -1,5 +1,6 @@
 idf_build_get_property(target IDF_TARGET)

+# should test arch here not target: IDF-1754
 if("${target}" STREQUAL "esp32c3" OR "${target}" STREQUAL "esp32h2")
    return()
 endif()
--- a/tools/cmake/uf2.cmake
+++ b/tools/cmake/uf2.cmake
@ -11,7 +11,7 @@ function(__add_uf2_targets)
    elseif("${target}" STREQUAL "esp32s3")
        set(uf2_family_id "0xc47e5767")
    elseif("${target}" STREQUAL "esp32h2")
-        set(uf2_family_id "0xd42ba06c")
+        set(uf2_family_id "0xd42ba06c") # ESP32H2-TODO: IDF-3487
    elseif("${target}" STREQUAL "linux")
        return()
    else()
--- a/tools/idf_py_actions/constants.py
+++ b/tools/idf_py_actions/constants.py
@ -36,6 +36,6 @@ GENERATORS = collections.OrderedDict([
    })
 ])

-SUPPORTED_TARGETS = ['esp32', 'esp32s2', 'esp32c3', 'esp32s3', 'esp32h2']
+SUPPORTED_TARGETS = ['esp32', 'esp32s2', 'esp32c3', 'esp32s3']

-PREVIEW_TARGETS = ['linux']
+PREVIEW_TARGETS = ['linux', 'esp32h2']