kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'bugfix/i2c_timeout_issue_v4.4' into 'release/v4.4'
I2C: patch for solving watchdog timeout issue(backport v4.4) See merge request espressif/esp-idf!18130pull/9239/head
commit
f86be6141b
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@ -476,6 +476,14 @@ static void IRAM_ATTR i2c_isr_handler_default(void *arg)
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{
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{
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i2c_obj_t *p_i2c = (i2c_obj_t *) arg;
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i2c_obj_t *p_i2c = (i2c_obj_t *) arg;
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int i2c_num = p_i2c->i2c_num;
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int i2c_num = p_i2c->i2c_num;
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// Interrupt protection.
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// On C3 and S3 targets, the I2C may trigger a spurious interrupt,
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// in order to detect these false positive, check the I2C's hardware interrupt mask
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uint32_t int_mask;
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i2c_hal_get_intsts_mask(&(i2c_context[i2c_num].hal), &int_mask);
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if (int_mask == 0) {
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return;
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}
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i2c_intr_event_t evt_type = I2C_INTR_EVENT_ERR;
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i2c_intr_event_t evt_type = I2C_INTR_EVENT_ERR;
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portBASE_TYPE HPTaskAwoken = pdFALSE;
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portBASE_TYPE HPTaskAwoken = pdFALSE;
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if (p_i2c->mode == I2C_MODE_MASTER) {
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if (p_i2c->mode == I2C_MODE_MASTER) {
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@ -499,6 +507,9 @@ static void IRAM_ATTR i2c_isr_handler_default(void *arg)
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if (p_i2c->status != I2C_STATUS_ACK_ERROR && p_i2c->status != I2C_STATUS_IDLE) {
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if (p_i2c->status != I2C_STATUS_ACK_ERROR && p_i2c->status != I2C_STATUS_IDLE) {
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i2c_master_cmd_begin_static(i2c_num);
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i2c_master_cmd_begin_static(i2c_num);
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}
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}
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} else {
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// Do nothing if there is no proper event.
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return;
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}
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}
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i2c_cmd_evt_t evt = {
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i2c_cmd_evt_t evt = {
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.type = I2C_CMD_EVT_ALIVE
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.type = I2C_CMD_EVT_ALIVE
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@ -596,6 +607,8 @@ static esp_err_t i2c_master_clear_bus(i2c_port_t i2c_num)
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**/
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**/
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static esp_err_t i2c_hw_fsm_reset(i2c_port_t i2c_num)
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static esp_err_t i2c_hw_fsm_reset(i2c_port_t i2c_num)
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{
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{
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// A workaround for avoiding cause timeout issue when using
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// hardware reset.
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#if !SOC_I2C_SUPPORT_HW_FSM_RST
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#if !SOC_I2C_SUPPORT_HW_FSM_RST
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int scl_low_period, scl_high_period;
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int scl_low_period, scl_high_period;
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int scl_start_hold, scl_rstart_setup;
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int scl_start_hold, scl_rstart_setup;
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@ -127,7 +127,7 @@
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#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
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#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
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#define SOC_I2C_SUPPORT_HW_FSM_RST (1)
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// FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined.
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#define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
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#define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
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#define SOC_I2C_SUPPORT_XTAL (1)
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#define SOC_I2C_SUPPORT_XTAL (1)
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@ -115,7 +115,7 @@
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#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
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#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
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#define SOC_I2C_SUPPORT_HW_FSM_RST (1)
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// FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined.
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#define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
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#define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
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#define SOC_I2C_SUPPORT_XTAL (1)
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#define SOC_I2C_SUPPORT_XTAL (1)
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@ -128,8 +128,7 @@
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#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
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#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
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//ESP32-S2 support hardware FSM reset
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// FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined.
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#define SOC_I2C_SUPPORT_HW_FSM_RST (1)
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//ESP32-S2 support hardware clear bus
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//ESP32-S2 support hardware clear bus
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#define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
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#define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
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@ -23,8 +23,7 @@ extern "C" {
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#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
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#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
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//ESP32-S3 support hardware FSM reset
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// FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined.
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#define SOC_I2C_SUPPORT_HW_FSM_RST (1)
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//ESP32-S3 support hardware clear bus
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//ESP32-S3 support hardware clear bus
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#define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
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#define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
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