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ci(sdspi): re-enable probe/rw tests for slot 1 

These tests were disabled since SDMMC_FREQ_HIGHSPEED with sdspi didn't
work on ESP32 and ESP32-S3. However we don't have other tests for
slot 1, meaning that we weren't running probe and perf tests at all.

This commit re-enables the tests, keeping them with SDMMC_FREQ_DEFAULT
pull/13854/head
Ivan Grokhotkov 2024-05-02 16:39:39 +02:00
rodzic e672d49db7
commit f355ecac40
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ID klucza GPG: 1E050E141B280628
2 zmienionych plików z 8 dodań i 14 usunięć
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8
components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/sdmmc_test_probe_spi.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -40,11 +40,9 @@ TEST_CASE("sdspi probe, slot 1", "[sdspi]")
do_one_sdspi_probe(SLOT_1, SDMMC_FREQ_CUSTOM_10M);
}
#if !CONFIG_IDF_TARGET_ESP32 && !CONFIG_IDF_TARGET_ESP32S3
//TODO: IDF-8749
//here freq should be changed to SDMMC_FREQ_HIGHSPEED after fixing IDF-8749
TEST_CASE("sdspi probe, slot 1, HS", "[sdspi]")
{
//TODO: IDF-8749
//here freq should be changed to SDMMC_FREQ_HIGHSPEED after fixing IDF-8749
do_one_sdspi_probe(SLOT_1, SDMMC_FREQ_DEFAULT);
}
#endif

14
components/esp_driver_sdspi/test_apps/sdspi/components/sdspi_tests/sdmmc_test_rw_spi.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -26,14 +26,12 @@ TEST_CASE("sdspi read/write performance, slot 0", "[sdspi]")
do_one_sdspi_perf_test(SLOT_0, SDMMC_FREQ_HIGHSPEED);
}
#if !CONFIG_IDF_TARGET_ESP32 && !CONFIG_IDF_TARGET_ESP32S3
//TODO: IDF-8749
//here freq should be changed to SDMMC_FREQ_HIGHSPEED after fixing IDF-8749
TEST_CASE("sdspi read/write performance, slot 1", "[sdspi]")
{
//TODO: IDF-8749
//here freq should be changed to SDMMC_FREQ_HIGHSPEED after fixing IDF-8749
do_one_sdspi_perf_test(SLOT_1, SDMMC_FREQ_DEFAULT);
}
#endif
/* ========== Read/write tests with offset, SPI ========== */
@ -52,14 +50,12 @@ TEST_CASE("sdspi read/write performance with offset, slot 0", "[sdspi]")
do_one_sdspi_rw_test_with_offset(SLOT_0, SDMMC_FREQ_HIGHSPEED);
}
#if !CONFIG_IDF_TARGET_ESP32 && !CONFIG_IDF_TARGET_ESP32S3
//TODO: IDF-8749
//here freq should be changed to SDMMC_FREQ_HIGHSPEED after fixing IDF-8749
TEST_CASE("sdspi read/write performance with offset, slot 1", "[sdspi]")
{
//TODO: IDF-8749
//here freq should be changed to SDMMC_FREQ_HIGHSPEED after fixing IDF-8749
do_one_sdspi_rw_test_with_offset(SLOT_1, SDMMC_FREQ_DEFAULT);
}
#endif
/* ========== Read/write tests with unaligned source/destination buffer, SPI ========== */