kopia lustrzana https://github.com/espressif/esp-idf
rtc: add rtc related changes from feature/support_7.2.7_soc
rodzic
2aead8ba57
commit
e83d213c56
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@ -40,7 +40,7 @@ static const char *TAG = "rtc_clk";
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#define DELAY_RTC_CLK_SWITCH 5
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// Current PLL frequency, in MHZ (320 or 480). Zero if PLL is not enabled.
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static uint32_t s_cur_pll_freq = RTC_PLL_FREQ_480M;
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static uint32_t s_cur_pll_freq;
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static void rtc_clk_cpu_freq_to_8m(void);
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@ -306,7 +306,8 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
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REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3);
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REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
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REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias);
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REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DHREF_SEL, 2);
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REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, 1);
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s_cur_pll_freq = pll_freq;
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}
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@ -25,7 +25,6 @@
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#include "regi2c_ulp.h"
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#include "soc_log.h"
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#define RTC_CNTL_MEM_FORCE_PU (RTC_CNTL_SLOWMEM_FORCE_PU | RTC_CNTL_FASTMEM_FORCE_PU)
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#define RTC_CNTL_MEM_FORCE_NOISO (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO)
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static char *TAG = "rtcinit";
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@ -47,15 +46,22 @@ void rtc_init(rtc_config_t cfg)
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rtc_init_config_t rtc_init_cfg = RTC_INIT_CONFIG_DEFAULT();
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REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, rtc_init_cfg.wifi_powerup_cycles);
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REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, rtc_init_cfg.wifi_wait_cycles);
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// set bt timer
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REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_BT_POWERUP_TIMER, rtc_init_cfg.bt_powerup_cycles);
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REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_BT_WAIT_TIMER, rtc_init_cfg.bt_wait_cycles);
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REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_CPU_TOP_POWERUP_TIMER, rtc_init_cfg.cpu_top_powerup_cycles);
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REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_CPU_TOP_WAIT_TIMER, rtc_init_cfg.cpu_top_wait_cycles);
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// set rtc peri timer
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REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_POWERUP_TIMER, rtc_init_cfg.rtc_powerup_cycles);
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REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_WAIT_TIMER, rtc_init_cfg.rtc_wait_cycles);
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// set digital wrap timer
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REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_POWERUP_TIMER, rtc_init_cfg.dg_wrap_powerup_cycles);
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REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_WAIT_TIMER, rtc_init_cfg.dg_wrap_wait_cycles);
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// set rtc memory timer
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REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTLMEM_POWERUP_TIMER, rtc_init_cfg.rtc_mem_powerup_cycles);
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REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTLMEM_WAIT_TIMER, rtc_init_cfg.rtc_mem_wait_cycles);
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REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_POWERUP_TIMER, rtc_init_cfg.dg_peri_powerup_cycles);
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REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_WAIT_TIMER, rtc_init_cfg.dg_peri_wait_cycles);
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/* Reset RTC bias to default value (needed if waking up from deep sleep) */
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, RTC_CNTL_DBIAS_1V10);
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@ -64,10 +70,6 @@ void rtc_init(rtc_config_t cfg)
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if (cfg.clkctl_init) {
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//clear CMMU clock force on
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CLEAR_PERI_REG_MASK(EXTMEM_CACHE_MMU_POWER_CTRL_REG, EXTMEM_CACHE_MMU_MEM_FORCE_ON);
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//clear rom clock force on
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REG_SET_FIELD(SYSCON_CLKGATE_FORCE_ON_REG, SYSCON_ROM_CLKGATE_FORCE_ON, 0);
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//clear sram clock force on
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REG_SET_FIELD(SYSCON_CLKGATE_FORCE_ON_REG, SYSCON_SRAM_CLKGATE_FORCE_ON, 0);
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//clear tag clock force on
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CLEAR_PERI_REG_MASK(EXTMEM_DCACHE_TAG_POWER_CTRL_REG, EXTMEM_DCACHE_TAG_MEM_FORCE_ON);
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CLEAR_PERI_REG_MASK(EXTMEM_ICACHE_TAG_POWER_CTRL_REG, EXTMEM_ICACHE_TAG_MEM_FORCE_ON);
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@ -89,6 +91,9 @@ void rtc_init(rtc_config_t cfg)
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CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU);
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SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
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//open sar_i2c protect function to avoid sar_i2c reset when rtc_ldo is low.
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CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_I2C_RESET_POR_FORCE_PD);
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//cancel bbpll force pu if setting no force power up
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if (!cfg.bbpll_fpu) {
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CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU);
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@ -104,9 +109,7 @@ void rtc_init(rtc_config_t cfg)
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CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PU);
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//combine two rtc memory options
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CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_NOISO);
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CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO);
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if (cfg.rtc_dboost_fpd) {
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SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD);
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@ -114,11 +117,6 @@ void rtc_init(rtc_config_t cfg)
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CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD);
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}
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//cancel digital pu force
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CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_I2C_RESET_POR_FORCE_PD);
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/* If this mask is enabled, all soc memories cannot enter power down mode */
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/* We should control soc memory power down mode from RTC, so we will not touch this register any more */
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CLEAR_PERI_REG_MASK(SYSTEM_MEM_PD_MASK_REG, SYSTEM_LSLP_MEM_PD_MASK);
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@ -129,12 +127,19 @@ void rtc_init(rtc_config_t cfg)
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_WRAP_FORCE_NOISO);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO);
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CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_NOISO);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_NOISO);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_TOP_FORCE_NOISO);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PERI_FORCE_NOISO);
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//cancel digital PADS force no iso
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if (cfg.cpu_waiti_clk_gate) {
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SET_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON);
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CLEAR_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON);
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} else {
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SET_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON);
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}
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@ -37,7 +37,6 @@ void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
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{
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REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu);
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REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu);
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REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_LPU, cfg.rtc_fpu);
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REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_DC_MEM_FORCE_PU, cfg.fe_fpu);
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REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_PBUS_MEM_FORCE_PU, cfg.fe_fpu);
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REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_AGC_MEM_FORCE_PU, cfg.fe_fpu);
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@ -74,22 +73,14 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
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}
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if (cfg.rtc_fastmem_pd_en) {
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SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN);
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CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO);
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} else {
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CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN);
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SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU);
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SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO);
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}
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if (cfg.rtc_slowmem_pd_en) {
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SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN);
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CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_NOISO);
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} else {
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CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN);
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SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU);
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SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_NOISO);
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}
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@ -105,6 +96,22 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
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}
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if (cfg.bt_pd_en) {
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SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN);
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} else {
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN);
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}
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if (cfg.cpu_pd_en) {
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SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_PD_EN);
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} else {
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_PD_EN);
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}
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if (cfg.dig_peri_pd_en) {
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SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN);
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} else {
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN);
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}
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, RTC_CNTL_BIASSLP_MONITOR_DEFAULT);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, RTC_CNTL_BIASSLP_SLEEP_DEFAULT);
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@ -249,10 +249,16 @@ typedef struct {
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typedef struct {
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uint16_t wifi_powerup_cycles : 7;
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uint16_t wifi_wait_cycles : 9;
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uint16_t bt_powerup_cycles : 7;
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uint16_t bt_wait_cycles : 9;
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uint16_t rtc_powerup_cycles : 7;
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uint16_t rtc_wait_cycles : 9;
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uint16_t cpu_top_powerup_cycles : 7;
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uint16_t cpu_top_wait_cycles : 9;
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uint16_t dg_wrap_powerup_cycles : 7;
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uint16_t dg_wrap_wait_cycles : 9;
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uint16_t dg_peri_powerup_cycles : 7;
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uint16_t dg_peri_wait_cycles : 9;
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uint16_t rtc_mem_powerup_cycles : 7;
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uint16_t rtc_mem_wait_cycles : 9;
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} rtc_init_config_t;
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@ -633,6 +639,9 @@ typedef struct {
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uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory
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uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals
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uint32_t wifi_pd_en : 1; //!< power down WiFi
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uint32_t bt_pd_en : 1; //!< power down BT
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uint32_t cpu_pd_en : 1; //!< power down CPU, but not restart when lightsleep.
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uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals
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uint32_t deep_slp : 1; //!< power down digital domain
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uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode
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uint32_t dig_dbias_wak : 5; //!< set bias for digital domain, in active mode
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