diff --git a/components/esp_hw_support/port/esp32s3/rtc_clk.c b/components/esp_hw_support/port/esp32s3/rtc_clk.c index 71b208a6a0..5477eeb5f4 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_clk.c +++ b/components/esp_hw_support/port/esp32s3/rtc_clk.c @@ -40,7 +40,7 @@ static const char *TAG = "rtc_clk"; #define DELAY_RTC_CLK_SWITCH 5 // Current PLL frequency, in MHZ (320 or 480). Zero if PLL is not enabled. -static uint32_t s_cur_pll_freq = RTC_PLL_FREQ_480M; +static uint32_t s_cur_pll_freq; static void rtc_clk_cpu_freq_to_8m(void); @@ -306,7 +306,8 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq) REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3); REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur); REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias); - + REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DHREF_SEL, 2); + REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, 1); s_cur_pll_freq = pll_freq; } diff --git a/components/esp_hw_support/port/esp32s3/rtc_init.c b/components/esp_hw_support/port/esp32s3/rtc_init.c index acccd64745..ff8f0e7e88 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_init.c +++ b/components/esp_hw_support/port/esp32s3/rtc_init.c @@ -25,7 +25,6 @@ #include "regi2c_ulp.h" #include "soc_log.h" -#define RTC_CNTL_MEM_FORCE_PU (RTC_CNTL_SLOWMEM_FORCE_PU | RTC_CNTL_FASTMEM_FORCE_PU) #define RTC_CNTL_MEM_FORCE_NOISO (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO) static char *TAG = "rtcinit"; @@ -47,15 +46,22 @@ void rtc_init(rtc_config_t cfg) rtc_init_config_t rtc_init_cfg = RTC_INIT_CONFIG_DEFAULT(); REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, rtc_init_cfg.wifi_powerup_cycles); REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, rtc_init_cfg.wifi_wait_cycles); + // set bt timer + REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_BT_POWERUP_TIMER, rtc_init_cfg.bt_powerup_cycles); + REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_BT_WAIT_TIMER, rtc_init_cfg.bt_wait_cycles); + + REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_CPU_TOP_POWERUP_TIMER, rtc_init_cfg.cpu_top_powerup_cycles); + REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_CPU_TOP_WAIT_TIMER, rtc_init_cfg.cpu_top_wait_cycles); + // set rtc peri timer REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_POWERUP_TIMER, rtc_init_cfg.rtc_powerup_cycles); REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_WAIT_TIMER, rtc_init_cfg.rtc_wait_cycles); // set digital wrap timer REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_POWERUP_TIMER, rtc_init_cfg.dg_wrap_powerup_cycles); REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_WAIT_TIMER, rtc_init_cfg.dg_wrap_wait_cycles); - // set rtc memory timer - REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTLMEM_POWERUP_TIMER, rtc_init_cfg.rtc_mem_powerup_cycles); - REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTLMEM_WAIT_TIMER, rtc_init_cfg.rtc_mem_wait_cycles); + + REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_POWERUP_TIMER, rtc_init_cfg.dg_peri_powerup_cycles); + REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_WAIT_TIMER, rtc_init_cfg.dg_peri_wait_cycles); /* Reset RTC bias to default value (needed if waking up from deep sleep) */ REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, RTC_CNTL_DBIAS_1V10); @@ -64,10 +70,6 @@ void rtc_init(rtc_config_t cfg) if (cfg.clkctl_init) { //clear CMMU clock force on CLEAR_PERI_REG_MASK(EXTMEM_CACHE_MMU_POWER_CTRL_REG, EXTMEM_CACHE_MMU_MEM_FORCE_ON); - //clear rom clock force on - REG_SET_FIELD(SYSCON_CLKGATE_FORCE_ON_REG, SYSCON_ROM_CLKGATE_FORCE_ON, 0); - //clear sram clock force on - REG_SET_FIELD(SYSCON_CLKGATE_FORCE_ON_REG, SYSCON_SRAM_CLKGATE_FORCE_ON, 0); //clear tag clock force on CLEAR_PERI_REG_MASK(EXTMEM_DCACHE_TAG_POWER_CTRL_REG, EXTMEM_DCACHE_TAG_MEM_FORCE_ON); CLEAR_PERI_REG_MASK(EXTMEM_ICACHE_TAG_POWER_CTRL_REG, EXTMEM_ICACHE_TAG_MEM_FORCE_ON); @@ -89,6 +91,9 @@ void rtc_init(rtc_config_t cfg) CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU); SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); + //open sar_i2c protect function to avoid sar_i2c reset when rtc_ldo is low. + CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_I2C_RESET_POR_FORCE_PD); + //cancel bbpll force pu if setting no force power up if (!cfg.bbpll_fpu) { CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU); @@ -104,9 +109,7 @@ void rtc_init(rtc_config_t cfg) CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PU); - //combine two rtc memory options - CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU); - CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_NOISO); + CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO); if (cfg.rtc_dboost_fpd) { SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD); @@ -114,11 +117,6 @@ void rtc_init(rtc_config_t cfg) CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD); } - //cancel digital pu force - CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU); - - CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_I2C_RESET_POR_FORCE_PD); - /* If this mask is enabled, all soc memories cannot enter power down mode */ /* We should control soc memory power down mode from RTC, so we will not touch this register any more */ CLEAR_PERI_REG_MASK(SYSTEM_MEM_PD_MASK_REG, SYSTEM_LSLP_MEM_PD_MASK); @@ -129,12 +127,19 @@ void rtc_init(rtc_config_t cfg) CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_FORCE_PU); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU); + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PU); + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_FORCE_PU); + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_FORCE_PU); + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_WRAP_FORCE_NOISO); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO); CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_NOISO); + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_NOISO); + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_TOP_FORCE_NOISO); + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PERI_FORCE_NOISO); //cancel digital PADS force no iso if (cfg.cpu_waiti_clk_gate) { - SET_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON); + CLEAR_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON); } else { SET_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON); } diff --git a/components/esp_hw_support/port/esp32s3/rtc_sleep.c b/components/esp_hw_support/port/esp32s3/rtc_sleep.c index 1a180813cf..ccdfdb9d08 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32s3/rtc_sleep.c @@ -37,7 +37,6 @@ void rtc_sleep_pu(rtc_sleep_pu_config_t cfg) { REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu); REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu); - REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_LPU, cfg.rtc_fpu); REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_DC_MEM_FORCE_PU, cfg.fe_fpu); REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_PBUS_MEM_FORCE_PU, cfg.fe_fpu); REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_AGC_MEM_FORCE_PU, cfg.fe_fpu); @@ -74,22 +73,14 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) } if (cfg.rtc_fastmem_pd_en) { - SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN); - CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU); CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO); } else { - CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN); - SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU); SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO); } if (cfg.rtc_slowmem_pd_en) { - SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN); - CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU); CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_NOISO); } else { - CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN); - SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU); SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_NOISO); } @@ -105,6 +96,22 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN); } + if (cfg.bt_pd_en) { + SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN); + } else { + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN); + } + if (cfg.cpu_pd_en) { + SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_PD_EN); + } else { + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_PD_EN); + } + if (cfg.dig_peri_pd_en) { + SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN); + } else { + CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN); + } + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, RTC_CNTL_BIASSLP_MONITOR_DEFAULT); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, RTC_CNTL_BIASSLP_SLEEP_DEFAULT); diff --git a/components/soc/esp32s3/include/soc/rtc.h b/components/soc/esp32s3/include/soc/rtc.h index d754d01da6..6add0bf89a 100644 --- a/components/soc/esp32s3/include/soc/rtc.h +++ b/components/soc/esp32s3/include/soc/rtc.h @@ -249,10 +249,16 @@ typedef struct { typedef struct { uint16_t wifi_powerup_cycles : 7; uint16_t wifi_wait_cycles : 9; + uint16_t bt_powerup_cycles : 7; + uint16_t bt_wait_cycles : 9; uint16_t rtc_powerup_cycles : 7; uint16_t rtc_wait_cycles : 9; + uint16_t cpu_top_powerup_cycles : 7; + uint16_t cpu_top_wait_cycles : 9; uint16_t dg_wrap_powerup_cycles : 7; uint16_t dg_wrap_wait_cycles : 9; + uint16_t dg_peri_powerup_cycles : 7; + uint16_t dg_peri_wait_cycles : 9; uint16_t rtc_mem_powerup_cycles : 7; uint16_t rtc_mem_wait_cycles : 9; } rtc_init_config_t; @@ -633,6 +639,9 @@ typedef struct { uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals uint32_t wifi_pd_en : 1; //!< power down WiFi + uint32_t bt_pd_en : 1; //!< power down BT + uint32_t cpu_pd_en : 1; //!< power down CPU, but not restart when lightsleep. + uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals uint32_t deep_slp : 1; //!< power down digital domain uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode uint32_t dig_dbias_wak : 5; //!< set bias for digital domain, in active mode diff --git a/components/soc/esp32s3/include/soc/rtc_cntl_reg.h b/components/soc/esp32s3/include/soc/rtc_cntl_reg.h index 4d2bae6b25..f6f46572bd 100644 --- a/components/soc/esp32s3/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32s3/include/soc/rtc_cntl_reg.h @@ -14,7 +14,6 @@ #ifndef _SOC_RTC_CNTL_REG_H_ #define _SOC_RTC_CNTL_REG_H_ - #ifdef __cplusplus extern "C" { #endif @@ -34,2088 +33,1964 @@ extern "C" { #define RTC_WDT_RESET_LENGTH_800_NS 5 #define RTC_WDT_RESET_LENGTH_1600_NS 6 #define RTC_WDT_RESET_LENGTH_3200_NS 7 -#define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG -#define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG +#define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG +#define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG -#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0) +#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0000) /* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */ -/*description: SW system reset.*/ -#define RTC_CNTL_SW_SYS_RST (BIT(31)) +/*description: SW system reset*/ +#define RTC_CNTL_SW_SYS_RST (BIT(31)) #define RTC_CNTL_SW_SYS_RST_M (BIT(31)) #define RTC_CNTL_SW_SYS_RST_V 0x1 #define RTC_CNTL_SW_SYS_RST_S 31 /* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: digital core force no reset in deep sleep.*/ -#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) +/*description: digital core force no reset in deep sleep*/ +#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) #define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30)) #define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x1 #define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 /* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: digital wrap force reset in deep sleep.*/ -#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) +/*description: digital wrap force reset in deep sleep*/ +#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) #define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29)) #define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x1 #define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 /* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */ -/*description: .*/ -#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) +/*description: */ +#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) #define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28)) #define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x1 #define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 /* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ -/*description: .*/ -#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) +/*description: */ +#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) #define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27)) #define RTC_CNTL_PLL_FORCE_NOISO_V 0x1 #define RTC_CNTL_PLL_FORCE_NOISO_S 27 /* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */ -/*description: .*/ -#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) +/*description: */ +#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) #define RTC_CNTL_XTL_FORCE_NOISO_M (BIT(26)) #define RTC_CNTL_XTL_FORCE_NOISO_V 0x1 #define RTC_CNTL_XTL_FORCE_NOISO_S 26 /* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */ -/*description: .*/ -#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) +/*description: */ +#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) #define RTC_CNTL_ANALOG_FORCE_ISO_M (BIT(25)) #define RTC_CNTL_ANALOG_FORCE_ISO_V 0x1 #define RTC_CNTL_ANALOG_FORCE_ISO_S 25 /* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ -/*description: .*/ -#define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) +/*description: */ +#define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) #define RTC_CNTL_PLL_FORCE_ISO_M (BIT(24)) #define RTC_CNTL_PLL_FORCE_ISO_V 0x1 #define RTC_CNTL_PLL_FORCE_ISO_S 24 /* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */ -/*description: .*/ -#define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) +/*description: */ +#define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) #define RTC_CNTL_XTL_FORCE_ISO_M (BIT(23)) #define RTC_CNTL_XTL_FORCE_ISO_V 0x1 #define RTC_CNTL_XTL_FORCE_ISO_S 23 /* RTC_CNTL_XTL_EN_WAIT : R/W ;bitpos:[17:14] ;default: 4'd2 ; */ -/*description: wait bias_sleep and current source wakeup.*/ -#define RTC_CNTL_XTL_EN_WAIT 0x0000000F +/*description: wait bias_sleep and current source wakeup*/ +#define RTC_CNTL_XTL_EN_WAIT 0x0000000F #define RTC_CNTL_XTL_EN_WAIT_M ((RTC_CNTL_XTL_EN_WAIT_V)<<(RTC_CNTL_XTL_EN_WAIT_S)) #define RTC_CNTL_XTL_EN_WAIT_V 0xF #define RTC_CNTL_XTL_EN_WAIT_S 14 /* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */ -/*description: crystall force power up.*/ -#define RTC_CNTL_XTL_FORCE_PU (BIT(13)) +/*description: crystall force power up*/ +#define RTC_CNTL_XTL_FORCE_PU (BIT(13)) #define RTC_CNTL_XTL_FORCE_PU_M (BIT(13)) #define RTC_CNTL_XTL_FORCE_PU_V 0x1 #define RTC_CNTL_XTL_FORCE_PU_S 13 /* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: crystall force power down.*/ -#define RTC_CNTL_XTL_FORCE_PD (BIT(12)) +/*description: crystall force power down*/ +#define RTC_CNTL_XTL_FORCE_PD (BIT(12)) #define RTC_CNTL_XTL_FORCE_PD_M (BIT(12)) #define RTC_CNTL_XTL_FORCE_PD_V 0x1 #define RTC_CNTL_XTL_FORCE_PD_S 12 /* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: BB_PLL force power up.*/ -#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) +/*description: BB_PLL force power up*/ +#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) #define RTC_CNTL_BBPLL_FORCE_PU_M (BIT(11)) #define RTC_CNTL_BBPLL_FORCE_PU_V 0x1 #define RTC_CNTL_BBPLL_FORCE_PU_S 11 /* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: BB_PLL force power down.*/ -#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) +/*description: BB_PLL force power down*/ +#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) #define RTC_CNTL_BBPLL_FORCE_PD_M (BIT(10)) #define RTC_CNTL_BBPLL_FORCE_PD_V 0x1 #define RTC_CNTL_BBPLL_FORCE_PD_S 10 /* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: BB_PLL_I2C force power up.*/ -#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) +/*description: BB_PLL_I2C force power up*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) #define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9)) #define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1 #define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 /* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: BB_PLL _I2C force power down.*/ -#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) +/*description: BB_PLL _I2C force power down*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) #define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (BIT(8)) #define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x1 #define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 /* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: BB_I2C force power up.*/ -#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) +/*description: BB_I2C force power up*/ +#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) #define RTC_CNTL_BB_I2C_FORCE_PU_M (BIT(7)) #define RTC_CNTL_BB_I2C_FORCE_PU_V 0x1 #define RTC_CNTL_BB_I2C_FORCE_PU_S 7 /* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: BB_I2C force power down.*/ -#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) +/*description: BB_I2C force power down*/ +#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) #define RTC_CNTL_BB_I2C_FORCE_PD_M (BIT(6)) #define RTC_CNTL_BB_I2C_FORCE_PD_V 0x1 #define RTC_CNTL_BB_I2C_FORCE_PD_S 6 /* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: PRO CPU SW reset.*/ -#define RTC_CNTL_SW_PROCPU_RST (BIT(5)) +/*description: PRO CPU SW reset*/ +#define RTC_CNTL_SW_PROCPU_RST (BIT(5)) #define RTC_CNTL_SW_PROCPU_RST_M (BIT(5)) #define RTC_CNTL_SW_PROCPU_RST_V 0x1 #define RTC_CNTL_SW_PROCPU_RST_S 5 /* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: APP CPU SW reset.*/ -#define RTC_CNTL_SW_APPCPU_RST (BIT(4)) +/*description: APP CPU SW reset*/ +#define RTC_CNTL_SW_APPCPU_RST (BIT(4)) #define RTC_CNTL_SW_APPCPU_RST_M (BIT(4)) #define RTC_CNTL_SW_APPCPU_RST_V 0x1 #define RTC_CNTL_SW_APPCPU_RST_S 4 /* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ -/*description: {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall P -RO CPU.*/ -#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 +/*description: {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == + 0x86 will stall PRO CPU*/ +#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 #define RTC_CNTL_SW_STALL_PROCPU_C0_M ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S)) #define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x3 #define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 /* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall A -PP CPU.*/ -#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 +/*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == + 0x86 will stall APP CPU*/ +#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 #define RTC_CNTL_SW_STALL_APPCPU_C0_M ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S)) #define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x3 #define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 -#define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) +#define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x0004) /* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF +/*description: */ +#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF #define RTC_CNTL_SLP_VAL_LO_M ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S)) #define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF #define RTC_CNTL_SLP_VAL_LO_S 0 -#define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8) +#define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x0008) /* RTC_CNTL_MAIN_TIMER_ALARM_EN : WO ;bitpos:[16] ;default: 1'h0 ; */ -/*description: timer alarm enable bit.*/ -#define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) +/*description: timer alarm enable bit*/ +#define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) #define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16)) #define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x1 #define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 /* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: RTC sleep timer high 16 bits.*/ -#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF +/*description: RTC sleep timer high 16 bits*/ +#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF #define RTC_CNTL_SLP_VAL_HI_M ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S)) #define RTC_CNTL_SLP_VAL_HI_V 0xFFFF #define RTC_CNTL_SLP_VAL_HI_S 0 -#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xC) +#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0x000C) /* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */ -/*description: Set 1: to update register with RTC timer.*/ -#define RTC_CNTL_TIME_UPDATE (BIT(31)) +/*description: Set 1: to update register with RTC timer*/ +#define RTC_CNTL_TIME_UPDATE (BIT(31)) #define RTC_CNTL_TIME_UPDATE_M (BIT(31)) #define RTC_CNTL_TIME_UPDATE_V 0x1 #define RTC_CNTL_TIME_UPDATE_S 31 /* RTC_CNTL_TIMER_SYS_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: enable to record system reset time.*/ -#define RTC_CNTL_TIMER_SYS_RST (BIT(29)) +/*description: enable to record system reset time*/ +#define RTC_CNTL_TIMER_SYS_RST (BIT(29)) #define RTC_CNTL_TIMER_SYS_RST_M (BIT(29)) #define RTC_CNTL_TIMER_SYS_RST_V 0x1 #define RTC_CNTL_TIMER_SYS_RST_S 29 /* RTC_CNTL_TIMER_XTL_OFF : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Enable to record 40M XTAL OFF time.*/ -#define RTC_CNTL_TIMER_XTL_OFF (BIT(28)) +/*description: Enable to record 40M XTAL OFF time*/ +#define RTC_CNTL_TIMER_XTL_OFF (BIT(28)) #define RTC_CNTL_TIMER_XTL_OFF_M (BIT(28)) #define RTC_CNTL_TIMER_XTL_OFF_V 0x1 #define RTC_CNTL_TIMER_XTL_OFF_S 28 /* RTC_CNTL_TIMER_SYS_STALL : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Enable to record system stall time.*/ -#define RTC_CNTL_TIMER_SYS_STALL (BIT(27)) +/*description: Enable to record system stall time*/ +#define RTC_CNTL_TIMER_SYS_STALL (BIT(27)) #define RTC_CNTL_TIMER_SYS_STALL_M (BIT(27)) #define RTC_CNTL_TIMER_SYS_STALL_V 0x1 #define RTC_CNTL_TIMER_SYS_STALL_S 27 -#define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x10) +#define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x0010) /* RTC_CNTL_TIMER_VALUE0_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: RTC timer low 32 bits.*/ -#define RTC_CNTL_TIMER_VALUE0_LOW 0xFFFFFFFF +/*description: RTC timer low 32 bits*/ +#define RTC_CNTL_TIMER_VALUE0_LOW 0xFFFFFFFF #define RTC_CNTL_TIMER_VALUE0_LOW_M ((RTC_CNTL_TIMER_VALUE0_LOW_V)<<(RTC_CNTL_TIMER_VALUE0_LOW_S)) #define RTC_CNTL_TIMER_VALUE0_LOW_V 0xFFFFFFFF #define RTC_CNTL_TIMER_VALUE0_LOW_S 0 -#define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x14) +#define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x0014) /* RTC_CNTL_TIMER_VALUE0_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: RTC timer high 16 bits.*/ -#define RTC_CNTL_TIMER_VALUE0_HIGH 0x0000FFFF +/*description: RTC timer high 16 bits*/ +#define RTC_CNTL_TIMER_VALUE0_HIGH 0x0000FFFF #define RTC_CNTL_TIMER_VALUE0_HIGH_M ((RTC_CNTL_TIMER_VALUE0_HIGH_V)<<(RTC_CNTL_TIMER_VALUE0_HIGH_S)) #define RTC_CNTL_TIMER_VALUE0_HIGH_V 0xFFFF #define RTC_CNTL_TIMER_VALUE0_HIGH_S 0 -#define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18) +#define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x0018) /* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: sleep enable bit.*/ -#define RTC_CNTL_SLEEP_EN (BIT(31)) +/*description: sleep enable bit*/ +#define RTC_CNTL_SLEEP_EN (BIT(31)) #define RTC_CNTL_SLEEP_EN_M (BIT(31)) #define RTC_CNTL_SLEEP_EN_V 0x1 #define RTC_CNTL_SLEEP_EN_S 31 /* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: leep reject bit.*/ -#define RTC_CNTL_SLP_REJECT (BIT(30)) +/*description: leep reject bit*/ +#define RTC_CNTL_SLP_REJECT (BIT(30)) #define RTC_CNTL_SLP_REJECT_M (BIT(30)) #define RTC_CNTL_SLP_REJECT_V 0x1 #define RTC_CNTL_SLP_REJECT_S 30 /* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: leep wakeup bit.*/ -#define RTC_CNTL_SLP_WAKEUP (BIT(29)) +/*description: leep wakeup bit*/ +#define RTC_CNTL_SLP_WAKEUP (BIT(29)) #define RTC_CNTL_SLP_WAKEUP_M (BIT(29)) #define RTC_CNTL_SLP_WAKEUP_V 0x1 #define RTC_CNTL_SLP_WAKEUP_S 29 /* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */ -/*description: SDIO active indication.*/ -#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) +/*description: SDIO active indication*/ +#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) #define RTC_CNTL_SDIO_ACTIVE_IND_M (BIT(28)) #define RTC_CNTL_SDIO_ACTIVE_IND_V 0x1 #define RTC_CNTL_SDIO_ACTIVE_IND_S 28 /* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: 1: APB to RTC using bridge.*/ -#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) +/*description: 1: APB to RTC using bridge*/ +#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) #define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (BIT(22)) #define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x1 #define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 /* RTC_CNTL_SLP_REJECT_CAUSE_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: clear rtc sleep reject cause.*/ -#define RTC_CNTL_SLP_REJECT_CAUSE_CLR (BIT(1)) +/*description: clear rtc sleep reject cause*/ +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR (BIT(1)) #define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M (BIT(1)) #define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V 0x1 #define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S 1 /* RTC_CNTL_SW_CPU_INT : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: rtc software interrupt to main cpu.*/ -#define RTC_CNTL_SW_CPU_INT (BIT(0)) +/*description: rtc software interrupt to main cpu*/ +#define RTC_CNTL_SW_CPU_INT (BIT(0)) #define RTC_CNTL_SW_CPU_INT_M (BIT(0)) #define RTC_CNTL_SW_CPU_INT_V 0x1 #define RTC_CNTL_SW_CPU_INT_S 0 -#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1C) +#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x001C) /* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */ -/*description: PLL wait cycles in slow_clk_rtc.*/ -#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF +/*description: PLL wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF #define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S)) #define RTC_CNTL_PLL_BUF_WAIT_V 0xFF #define RTC_CNTL_PLL_BUF_WAIT_S 24 /* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */ -/*description: XTAL wait cycles in slow_clk_rtc.*/ -#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF +/*description: XTAL wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF #define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) #define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF #define RTC_CNTL_XTL_BUF_WAIT_S 14 /* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ -/*description: CK8M wait cycles in slow_clk_rtc.*/ -#define RTC_CNTL_CK8M_WAIT 0x000000FF +/*description: CK8M wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_CK8M_WAIT 0x000000FF #define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) #define RTC_CNTL_CK8M_WAIT_V 0xFF #define RTC_CNTL_CK8M_WAIT_S 6 /* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ -/*description: CPU stall wait cycles in fast_clk_rtc.*/ -#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F +/*description: CPU stall wait cycles in fast_clk_rtc*/ +#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F #define RTC_CNTL_CPU_STALL_WAIT_M ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S)) #define RTC_CNTL_CPU_STALL_WAIT_V 0x1F #define RTC_CNTL_CPU_STALL_WAIT_S 1 /* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ -/*description: CPU stall enable bit.*/ -#define RTC_CNTL_CPU_STALL_EN (BIT(0)) +/*description: CPU stall enable bit*/ +#define RTC_CNTL_CPU_STALL_EN (BIT(0)) #define RTC_CNTL_CPU_STALL_EN_M (BIT(0)) #define RTC_CNTL_CPU_STALL_EN_V 0x1 #define RTC_CNTL_CPU_STALL_EN_S 0 -#define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20) +#define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x0020) /* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */ -/*description: minimal cycles in slow_clk_rtc for CK8M in power down state.*/ -#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF +/*description: minimal cycles in slow_clk_rtc for CK8M in power down state*/ +#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF #define RTC_CNTL_MIN_TIME_CK8M_OFF_M ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S)) #define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0xFF #define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 /* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W ;bitpos:[23:15] ;default: 9'h10 ; */ -/*description: wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to w -ork.*/ -#define RTC_CNTL_ULPCP_TOUCH_START_WAIT 0x000001FF +/*description: wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller + start to work*/ +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT 0x000001FF #define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M ((RTC_CNTL_ULPCP_TOUCH_START_WAIT_V)<<(RTC_CNTL_ULPCP_TOUCH_START_WAIT_S)) #define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V 0x1FF #define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S 15 -#define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24) -/* RTC_CNTL_ROM_RAM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'd10 ; */ -/*description: .*/ -#define RTC_CNTL_ROM_RAM_POWERUP_TIMER 0x0000007F -#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_M ((RTC_CNTL_ROM_RAM_POWERUP_TIMER_V)<<(RTC_CNTL_ROM_RAM_POWERUP_TIMER_S)) -#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_V 0x7F -#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_S 25 -/* RTC_CNTL_ROM_RAM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h16 ; */ -/*description: .*/ -#define RTC_CNTL_ROM_RAM_WAIT_TIMER 0x000001FF -#define RTC_CNTL_ROM_RAM_WAIT_TIMER_M ((RTC_CNTL_ROM_RAM_WAIT_TIMER_V)<<(RTC_CNTL_ROM_RAM_WAIT_TIMER_S)) -#define RTC_CNTL_ROM_RAM_WAIT_TIMER_V 0x1FF -#define RTC_CNTL_ROM_RAM_WAIT_TIMER_S 16 +#define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x0024) +/* RTC_CNTL_BT_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'd10 ; */ +/*description: */ +#define RTC_CNTL_BT_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_BT_POWERUP_TIMER_M ((RTC_CNTL_BT_POWERUP_TIMER_V)<<(RTC_CNTL_BT_POWERUP_TIMER_S)) +#define RTC_CNTL_BT_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_BT_POWERUP_TIMER_S 25 +/* RTC_CNTL_BT_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h16 ; */ +/*description: */ +#define RTC_CNTL_BT_WAIT_TIMER 0x000001FF +#define RTC_CNTL_BT_WAIT_TIMER_M ((RTC_CNTL_BT_WAIT_TIMER_V)<<(RTC_CNTL_BT_WAIT_TIMER_S)) +#define RTC_CNTL_BT_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_BT_WAIT_TIMER_S 16 /* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ -/*description: .*/ -#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F +/*description: */ +#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F #define RTC_CNTL_WIFI_POWERUP_TIMER_M ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S)) #define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x7F #define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 /* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ -/*description: .*/ -#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF +/*description: */ +#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF #define RTC_CNTL_WIFI_WAIT_TIMER_M ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S)) #define RTC_CNTL_WIFI_WAIT_TIMER_V 0x1FF #define RTC_CNTL_WIFI_WAIT_TIMER_S 0 -#define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x28) +#define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x0028) /* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ -/*description: .*/ -#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F +/*description: */ +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S)) #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x7F #define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 /* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ -/*description: .*/ -#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF +/*description: */ +#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF #define RTC_CNTL_DG_WRAP_WAIT_TIMER_M ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S)) #define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x1FF #define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 /* RTC_CNTL_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ -/*description: .*/ -#define RTC_CNTL_POWERUP_TIMER 0x0000007F +/*description: */ +#define RTC_CNTL_POWERUP_TIMER 0x0000007F #define RTC_CNTL_POWERUP_TIMER_M ((RTC_CNTL_POWERUP_TIMER_V)<<(RTC_CNTL_POWERUP_TIMER_S)) #define RTC_CNTL_POWERUP_TIMER_V 0x7F #define RTC_CNTL_POWERUP_TIMER_S 9 /* RTC_CNTL_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ -/*description: .*/ -#define RTC_CNTL_WAIT_TIMER 0x000001FF +/*description: */ +#define RTC_CNTL_WAIT_TIMER 0x000001FF #define RTC_CNTL_WAIT_TIMER_M ((RTC_CNTL_WAIT_TIMER_V)<<(RTC_CNTL_WAIT_TIMER_S)) #define RTC_CNTL_WAIT_TIMER_V 0x1FF #define RTC_CNTL_WAIT_TIMER_S 0 -#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x2C) -/* RTC_CNTLMEM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h9 ; */ -/*description: .*/ -#define RTC_CNTLMEM_POWERUP_TIMER 0x0000007F -#define RTC_CNTLMEM_POWERUP_TIMER_M ((RTC_CNTLMEM_POWERUP_TIMER_V)<<(RTC_CNTLMEM_POWERUP_TIMER_S)) -#define RTC_CNTLMEM_POWERUP_TIMER_V 0x7F -#define RTC_CNTLMEM_POWERUP_TIMER_S 25 -/* RTC_CNTLMEM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h14 ; */ -/*description: .*/ -#define RTC_CNTLMEM_WAIT_TIMER 0x000001FF -#define RTC_CNTLMEM_WAIT_TIMER_M ((RTC_CNTLMEM_WAIT_TIMER_V)<<(RTC_CNTLMEM_WAIT_TIMER_S)) -#define RTC_CNTLMEM_WAIT_TIMER_V 0x1FF -#define RTC_CNTLMEM_WAIT_TIMER_S 16 +#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x002C) /* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */ -/*description: minimal sleep cycles in slow_clk_rtc.*/ -#define RTC_CNTL_MIN_SLP_VAL 0x000000FF +/*description: minimal sleep cycles in slow_clk_rtc*/ +#define RTC_CNTL_MIN_SLP_VAL 0x000000FF #define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S)) #define RTC_CNTL_MIN_SLP_VAL_V 0xFF #define RTC_CNTL_MIN_SLP_VAL_S 8 #define RTC_CNTL_MIN_SLP_VAL_MIN 2 -#define RTC_CNTL_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x30) -/* RTC_CNTL_DG_DCDC_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ -/*description: .*/ -#define RTC_CNTL_DG_DCDC_POWERUP_TIMER 0x0000007F -#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_M ((RTC_CNTL_DG_DCDC_POWERUP_TIMER_V)<<(RTC_CNTL_DG_DCDC_POWERUP_TIMER_S)) -#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_V 0x7F -#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_S 25 -/* RTC_CNTL_DG_DCDC_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ -/*description: .*/ -#define RTC_CNTL_DG_DCDC_WAIT_TIMER 0x000001FF -#define RTC_CNTL_DG_DCDC_WAIT_TIMER_M ((RTC_CNTL_DG_DCDC_WAIT_TIMER_V)<<(RTC_CNTL_DG_DCDC_WAIT_TIMER_S)) -#define RTC_CNTL_DG_DCDC_WAIT_TIMER_V 0x1FF -#define RTC_CNTL_DG_DCDC_WAIT_TIMER_S 16 +#define RTC_CNTL_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x0030) +/* RTC_CNTL_DG_PERI_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ +/*description: */ +#define RTC_CNTL_DG_PERI_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_DG_PERI_POWERUP_TIMER_M ((RTC_CNTL_DG_PERI_POWERUP_TIMER_V)<<(RTC_CNTL_DG_PERI_POWERUP_TIMER_S)) +#define RTC_CNTL_DG_PERI_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_DG_PERI_POWERUP_TIMER_S 25 +/* RTC_CNTL_DG_PERI_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ +/*description: */ +#define RTC_CNTL_DG_PERI_WAIT_TIMER 0x000001FF +#define RTC_CNTL_DG_PERI_WAIT_TIMER_M ((RTC_CNTL_DG_PERI_WAIT_TIMER_V)<<(RTC_CNTL_DG_PERI_WAIT_TIMER_S)) +#define RTC_CNTL_DG_PERI_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_DG_PERI_WAIT_TIMER_S 16 +/* RTC_CNTL_CPU_TOP_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ +/*description: */ +#define RTC_CNTL_CPU_TOP_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_M ((RTC_CNTL_CPU_TOP_POWERUP_TIMER_V)<<(RTC_CNTL_CPU_TOP_POWERUP_TIMER_S)) +#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_S 9 +/* RTC_CNTL_CPU_TOP_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ +/*description: */ +#define RTC_CNTL_CPU_TOP_WAIT_TIMER 0x000001FF +#define RTC_CNTL_CPU_TOP_WAIT_TIMER_M ((RTC_CNTL_CPU_TOP_WAIT_TIMER_V)<<(RTC_CNTL_CPU_TOP_WAIT_TIMER_S)) +#define RTC_CNTL_CPU_TOP_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_CPU_TOP_WAIT_TIMER_S 0 -#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x34) +#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0034) /* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: .*/ -#define RTC_CNTL_PLL_I2C_PU (BIT(31)) +/*description: */ +#define RTC_CNTL_PLL_I2C_PU (BIT(31)) #define RTC_CNTL_PLL_I2C_PU_M (BIT(31)) #define RTC_CNTL_PLL_I2C_PU_V 0x1 #define RTC_CNTL_PLL_I2C_PU_S 31 /* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: 1: CKGEN_I2C power up.*/ -#define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) +/*description: 1: CKGEN_I2C power up*/ +#define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) #define RTC_CNTL_CKGEN_I2C_PU_M (BIT(30)) #define RTC_CNTL_CKGEN_I2C_PU_V 0x1 #define RTC_CNTL_CKGEN_I2C_PU_S 30 /* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: 1: RFRX_PBUS power up.*/ -#define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) +/*description: 1: RFRX_PBUS power up*/ +#define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) #define RTC_CNTL_RFRX_PBUS_PU_M (BIT(28)) #define RTC_CNTL_RFRX_PBUS_PU_V 0x1 #define RTC_CNTL_RFRX_PBUS_PU_S 28 /* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */ -/*description: 1: TXRF_I2C power up.*/ -#define RTC_CNTL_TXRF_I2C_PU (BIT(27)) +/*description: 1: TXRF_I2C power up*/ +#define RTC_CNTL_TXRF_I2C_PU (BIT(27)) #define RTC_CNTL_TXRF_I2C_PU_M (BIT(27)) #define RTC_CNTL_TXRF_I2C_PU_V 0x1 #define RTC_CNTL_TXRF_I2C_PU_S 27 /* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: 1: PVTMON power up.*/ -#define RTC_CNTL_PVTMON_PU (BIT(26)) +/*description: 1: PVTMON power up*/ +#define RTC_CNTL_PVTMON_PU (BIT(26)) #define RTC_CNTL_PVTMON_PU_M (BIT(26)) #define RTC_CNTL_PVTMON_PU_V 0x1 #define RTC_CNTL_PVTMON_PU_S 26 /* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: start BBPLL calibration during sleep.*/ -#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) +/*description: start BBPLL calibration during sleep*/ +#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) #define RTC_CNTL_BBPLL_CAL_SLP_START_M (BIT(25)) #define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x1 #define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 /* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: PLLA force power up.*/ -#define RTC_CNTL_PLLA_FORCE_PU (BIT(24)) +/*description: PLLA force power up*/ +#define RTC_CNTL_PLLA_FORCE_PU (BIT(24)) #define RTC_CNTL_PLLA_FORCE_PU_M (BIT(24)) #define RTC_CNTL_PLLA_FORCE_PU_V 0x1 #define RTC_CNTL_PLLA_FORCE_PU_S 24 /* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */ -/*description: PLLA force power down.*/ -#define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) +/*description: PLLA force power down*/ +#define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) #define RTC_CNTL_PLLA_FORCE_PD_M (BIT(23)) #define RTC_CNTL_PLLA_FORCE_PD_V 0x1 #define RTC_CNTL_PLLA_FORCE_PD_S 23 /* RTC_CNTL_SAR_I2C_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: PLLA force power up.*/ -#define RTC_CNTL_SAR_I2C_PU (BIT(22)) +/*description: PLLA force power up*/ +#define RTC_CNTL_SAR_I2C_PU (BIT(22)) #define RTC_CNTL_SAR_I2C_PU_M (BIT(22)) #define RTC_CNTL_SAR_I2C_PU_V 0x1 #define RTC_CNTL_SAR_I2C_PU_S 22 /* RTC_CNTL_GLITCH_RST_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_GLITCH_RST_EN (BIT(20)) +/*description: */ +#define RTC_CNTL_GLITCH_RST_EN (BIT(20)) #define RTC_CNTL_GLITCH_RST_EN_M (BIT(20)) #define RTC_CNTL_GLITCH_RST_EN_V 0x1 #define RTC_CNTL_GLITCH_RST_EN_S 20 /* RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19)) +/*description: */ +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19)) #define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M (BIT(19)) #define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V 0x1 #define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S 19 /* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b1 ; */ -/*description: .*/ -#define RTC_CNTL_I2C_RESET_POR_FORCE_PD (BIT(18)) +/*description: */ +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD (BIT(18)) #define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M (BIT(18)) #define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V 0x1 #define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S 18 -#define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x38) +#define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x0038) /* RTC_CNTL_PRO_DRESET_MASK : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_PRO_DRESET_MASK (BIT(25)) +/*description: */ +#define RTC_CNTL_PRO_DRESET_MASK (BIT(25)) #define RTC_CNTL_PRO_DRESET_MASK_M (BIT(25)) #define RTC_CNTL_PRO_DRESET_MASK_V 0x1 #define RTC_CNTL_PRO_DRESET_MASK_S 25 /* RTC_CNTL_APP_DRESET_MASK : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_APP_DRESET_MASK (BIT(24)) +/*description: */ +#define RTC_CNTL_APP_DRESET_MASK (BIT(24)) #define RTC_CNTL_APP_DRESET_MASK_M (BIT(24)) #define RTC_CNTL_APP_DRESET_MASK_V 0x1 #define RTC_CNTL_APP_DRESET_MASK_S 24 /* RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR (BIT(23)) +/*description: */ +#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR (BIT(23)) #define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_M (BIT(23)) #define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_V 0x1 #define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_S 23 /* RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR (BIT(22)) +/*description: */ +#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR (BIT(22)) #define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_M (BIT(22)) #define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_V 0x1 #define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_S 22 /* RTC_CNTL_RESET_FLAG_JTAG_APPCPU : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU (BIT(21)) +/*description: */ +#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU (BIT(21)) #define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_M (BIT(21)) #define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_V 0x1 #define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_S 21 /* RTC_CNTL_RESET_FLAG_JTAG_PROCPU : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU (BIT(20)) +/*description: */ +#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU (BIT(20)) #define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_M (BIT(20)) #define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_V 0x1 #define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_S 20 /* RTC_CNTL_PROCPU_OCD_HALT_ON_RESET : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: PROCPU OcdHaltOnReset.*/ -#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET (BIT(19)) +/*description: PROCPU OcdHaltOnReset*/ +#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET (BIT(19)) #define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_M (BIT(19)) #define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_V 0x1 #define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_S 19 /* RTC_CNTL_APPCPU_OCD_HALT_ON_RESET : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: APPCPU OcdHaltOnReset.*/ -#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET (BIT(18)) +/*description: APPCPU OcdHaltOnReset*/ +#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET (BIT(18)) #define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_M (BIT(18)) #define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_V 0x1 #define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_S 18 /* RTC_CNTL_RESET_FLAG_APPCPU_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: clear APP CPU reset flag.*/ -#define RTC_CNTL_RESET_FLAG_APPCPU_CLR (BIT(17)) +/*description: clear APP CPU reset flag*/ +#define RTC_CNTL_RESET_FLAG_APPCPU_CLR (BIT(17)) #define RTC_CNTL_RESET_FLAG_APPCPU_CLR_M (BIT(17)) #define RTC_CNTL_RESET_FLAG_APPCPU_CLR_V 0x1 #define RTC_CNTL_RESET_FLAG_APPCPU_CLR_S 17 /* RTC_CNTL_RESET_FLAG_PROCPU_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: clear PRO CPU reset_flag.*/ -#define RTC_CNTL_RESET_FLAG_PROCPU_CLR (BIT(16)) +/*description: clear PRO CPU reset_flag*/ +#define RTC_CNTL_RESET_FLAG_PROCPU_CLR (BIT(16)) #define RTC_CNTL_RESET_FLAG_PROCPU_CLR_M (BIT(16)) #define RTC_CNTL_RESET_FLAG_PROCPU_CLR_V 0x1 #define RTC_CNTL_RESET_FLAG_PROCPU_CLR_S 16 /* RTC_CNTL_RESET_FLAG_APPCPU : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: APP CPU reset flag.*/ -#define RTC_CNTL_RESET_FLAG_APPCPU (BIT(15)) +/*description: APP CPU reset flag*/ +#define RTC_CNTL_RESET_FLAG_APPCPU (BIT(15)) #define RTC_CNTL_RESET_FLAG_APPCPU_M (BIT(15)) #define RTC_CNTL_RESET_FLAG_APPCPU_V 0x1 #define RTC_CNTL_RESET_FLAG_APPCPU_S 15 /* RTC_CNTL_RESET_FLAG_PROCPU : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: PRO CPU reset_flag.*/ -#define RTC_CNTL_RESET_FLAG_PROCPU (BIT(14)) +/*description: PRO CPU reset_flag*/ +#define RTC_CNTL_RESET_FLAG_PROCPU (BIT(14)) #define RTC_CNTL_RESET_FLAG_PROCPU_M (BIT(14)) #define RTC_CNTL_RESET_FLAG_PROCPU_V 0x1 #define RTC_CNTL_RESET_FLAG_PROCPU_S 14 /* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: PRO CPU state vector sel.*/ -#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13)) +/*description: PRO CPU state vector sel*/ +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13)) #define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M (BIT(13)) #define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V 0x1 #define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13 /* RTC_CNTL_APPCPU_STAT_VECTOR_SEL : R/W ;bitpos:[12] ;default: 1'b1 ; */ -/*description: APP CPU state vector sel.*/ -#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12)) +/*description: APP CPU state vector sel*/ +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12)) #define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M (BIT(12)) #define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V 0x1 #define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12 /* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */ -/*description: reset cause of APP CPU.*/ -#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F +/*description: reset cause of APP CPU*/ +#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F #define RTC_CNTL_RESET_CAUSE_APPCPU_M ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S)) #define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x3F #define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 /* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */ -/*description: reset cause of PRO CPU.*/ -#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F +/*description: reset cause of PRO CPU*/ +#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F #define RTC_CNTL_RESET_CAUSE_PROCPU_M ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S)) #define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x3F #define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 -#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x3C) +#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x003C) /* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[31:15] ;default: 17'b1100 ; */ -/*description: wakeup enable bitmap.*/ -#define RTC_CNTL_WAKEUP_ENA 0x0001FFFF +/*description: wakeup enable bitmap*/ +#define RTC_CNTL_WAKEUP_ENA 0x0001FFFF #define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S)) #define RTC_CNTL_WAKEUP_ENA_V 0x1FFFF #define RTC_CNTL_WAKEUP_ENA_S 15 -#define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x40) +#define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x0040) /* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA (BIT(20)) +/*description: */ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA (BIT(20)) #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_M (BIT(20)) #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V 0x1 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S 20 /* RTC_CNTL_GLITCH_DET_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: enbale gitch det interrupt.*/ -#define RTC_CNTL_GLITCH_DET_INT_ENA (BIT(19)) +/*description: enbale gitch det interrupt*/ +#define RTC_CNTL_GLITCH_DET_INT_ENA (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ENA_M (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ENA_V 0x1 #define RTC_CNTL_GLITCH_DET_INT_ENA_S 19 /* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: enable touch timeout interrupt.*/ -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA (BIT(18)) +/*description: enable touch timeout interrupt*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA (BIT(18)) #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_M (BIT(18)) #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_V 0x1 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_S 18 /* RTC_CNTL_COCPU_TRAP_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: enable cocpu trap interrupt.*/ -#define RTC_CNTL_COCPU_TRAP_INT_ENA (BIT(17)) +/*description: enable cocpu trap interrupt*/ +#define RTC_CNTL_COCPU_TRAP_INT_ENA (BIT(17)) #define RTC_CNTL_COCPU_TRAP_INT_ENA_M (BIT(17)) #define RTC_CNTL_COCPU_TRAP_INT_ENA_V 0x1 #define RTC_CNTL_COCPU_TRAP_INT_ENA_S 17 /* RTC_CNTL_XTAL32K_DEAD_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: enable xtal32k_dead interrupt.*/ -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA (BIT(16)) +/*description: enable xtal32k_dead interrupt*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA (BIT(16)) #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M (BIT(16)) #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V 0x1 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S 16 /* RTC_CNTL_SWD_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: enable super watch dog interrupt.*/ -#define RTC_CNTL_SWD_INT_ENA (BIT(15)) +/*description: enable super watch dog interrupt*/ +#define RTC_CNTL_SWD_INT_ENA (BIT(15)) #define RTC_CNTL_SWD_INT_ENA_M (BIT(15)) #define RTC_CNTL_SWD_INT_ENA_V 0x1 #define RTC_CNTL_SWD_INT_ENA_S 15 /* RTC_CNTL_SARADC2_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: enable saradc2 interrupt.*/ -#define RTC_CNTL_SARADC2_INT_ENA (BIT(14)) +/*description: enable saradc2 interrupt*/ +#define RTC_CNTL_SARADC2_INT_ENA (BIT(14)) #define RTC_CNTL_SARADC2_INT_ENA_M (BIT(14)) #define RTC_CNTL_SARADC2_INT_ENA_V 0x1 #define RTC_CNTL_SARADC2_INT_ENA_S 14 /* RTC_CNTL_COCPU_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: enable riscV cocpu interrupt.*/ -#define RTC_CNTL_COCPU_INT_ENA (BIT(13)) +/*description: enable riscV cocpu interrupt*/ +#define RTC_CNTL_COCPU_INT_ENA (BIT(13)) #define RTC_CNTL_COCPU_INT_ENA_M (BIT(13)) #define RTC_CNTL_COCPU_INT_ENA_V 0x1 #define RTC_CNTL_COCPU_INT_ENA_S 13 /* RTC_CNTL_TSENS_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: enable tsens interrupt.*/ -#define RTC_CNTL_TSENS_INT_ENA (BIT(12)) +/*description: enable tsens interrupt*/ +#define RTC_CNTL_TSENS_INT_ENA (BIT(12)) #define RTC_CNTL_TSENS_INT_ENA_M (BIT(12)) #define RTC_CNTL_TSENS_INT_ENA_V 0x1 #define RTC_CNTL_TSENS_INT_ENA_S 12 /* RTC_CNTL_SARADC1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: enable saradc1 interrupt.*/ -#define RTC_CNTL_SARADC1_INT_ENA (BIT(11)) +/*description: enable saradc1 interrupt*/ +#define RTC_CNTL_SARADC1_INT_ENA (BIT(11)) #define RTC_CNTL_SARADC1_INT_ENA_M (BIT(11)) #define RTC_CNTL_SARADC1_INT_ENA_V 0x1 #define RTC_CNTL_SARADC1_INT_ENA_S 11 /* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: enable RTC main timer interrupt.*/ -#define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(10)) +/*description: enable RTC main timer interrupt*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(10)) #define RTC_CNTL_MAIN_TIMER_INT_ENA_M (BIT(10)) #define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x1 #define RTC_CNTL_MAIN_TIMER_INT_ENA_S 10 /* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: enable brown out interrupt.*/ -#define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(9)) +/*description: enable brown out interrupt*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(9)) #define RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(9)) #define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x1 #define RTC_CNTL_BROWN_OUT_INT_ENA_S 9 /* RTC_CNTL_TOUCH_INACTIVE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: enable touch inactive interrupt.*/ -#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA (BIT(8)) +/*description: enable touch inactive interrupt*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_M (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_V 0x1 #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_S 8 /* RTC_CNTL_TOUCH_ACTIVE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: enable touch active interrupt.*/ -#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA (BIT(7)) +/*description: enable touch active interrupt*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA (BIT(7)) #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_M (BIT(7)) #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_V 0x1 #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_S 7 /* RTC_CNTL_TOUCH_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: enable touch done interrupt.*/ -#define RTC_CNTL_TOUCH_DONE_INT_ENA (BIT(6)) +/*description: enable touch done interrupt*/ +#define RTC_CNTL_TOUCH_DONE_INT_ENA (BIT(6)) #define RTC_CNTL_TOUCH_DONE_INT_ENA_M (BIT(6)) #define RTC_CNTL_TOUCH_DONE_INT_ENA_V 0x1 #define RTC_CNTL_TOUCH_DONE_INT_ENA_S 6 /* RTC_CNTL_ULP_CP_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: enable ULP-coprocessor interrupt.*/ -#define RTC_CNTL_ULP_CP_INT_ENA (BIT(5)) +/*description: enable ULP-coprocessor interrupt*/ +#define RTC_CNTL_ULP_CP_INT_ENA (BIT(5)) #define RTC_CNTL_ULP_CP_INT_ENA_M (BIT(5)) #define RTC_CNTL_ULP_CP_INT_ENA_V 0x1 #define RTC_CNTL_ULP_CP_INT_ENA_S 5 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: enable touch scan done interrupt.*/ -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA (BIT(4)) +/*description: enable touch scan done interrupt*/ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA (BIT(4)) #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_M (BIT(4)) #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_V 0x1 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_S 4 /* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: enable RTC WDT interrupt.*/ -#define RTC_CNTL_WDT_INT_ENA (BIT(3)) +/*description: enable RTC WDT interrupt*/ +#define RTC_CNTL_WDT_INT_ENA (BIT(3)) #define RTC_CNTL_WDT_INT_ENA_M (BIT(3)) #define RTC_CNTL_WDT_INT_ENA_V 0x1 #define RTC_CNTL_WDT_INT_ENA_S 3 /* RTC_CNTL_SDIO_IDLE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: enable SDIO idle interrupt.*/ -#define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2)) +/*description: enable SDIO idle interrupt*/ +#define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2)) #define RTC_CNTL_SDIO_IDLE_INT_ENA_M (BIT(2)) #define RTC_CNTL_SDIO_IDLE_INT_ENA_V 0x1 #define RTC_CNTL_SDIO_IDLE_INT_ENA_S 2 /* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: enable sleep reject interrupt.*/ -#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) +/*description: enable sleep reject interrupt*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) #define RTC_CNTL_SLP_REJECT_INT_ENA_M (BIT(1)) #define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x1 #define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 /* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: enable sleep wakeup interrupt.*/ -#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) +/*description: enable sleep wakeup interrupt*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) #define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (BIT(0)) #define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x1 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 -#define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x44) +#define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x0044) /* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW (BIT(20)) +/*description: */ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW (BIT(20)) #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_M (BIT(20)) #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V 0x1 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S 20 /* RTC_CNTL_GLITCH_DET_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: glitch_det_interrupt_raw.*/ -#define RTC_CNTL_GLITCH_DET_INT_RAW (BIT(19)) +/*description: glitch_det_interrupt_raw*/ +#define RTC_CNTL_GLITCH_DET_INT_RAW (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_RAW_M (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_RAW_V 0x1 #define RTC_CNTL_GLITCH_DET_INT_RAW_S 19 /* RTC_CNTL_TOUCH_TIMEOUT_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: touch timeout interrupt raw.*/ -#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW (BIT(18)) +/*description: touch timeout interrupt raw*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW (BIT(18)) #define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_M (BIT(18)) #define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_V 0x1 #define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_S 18 /* RTC_CNTL_COCPU_TRAP_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: cocpu trap interrupt raw.*/ -#define RTC_CNTL_COCPU_TRAP_INT_RAW (BIT(17)) +/*description: cocpu trap interrupt raw*/ +#define RTC_CNTL_COCPU_TRAP_INT_RAW (BIT(17)) #define RTC_CNTL_COCPU_TRAP_INT_RAW_M (BIT(17)) #define RTC_CNTL_COCPU_TRAP_INT_RAW_V 0x1 #define RTC_CNTL_COCPU_TRAP_INT_RAW_S 17 /* RTC_CNTL_XTAL32K_DEAD_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: xtal32k dead detection interrupt raw.*/ -#define RTC_CNTL_XTAL32K_DEAD_INT_RAW (BIT(16)) +/*description: xtal32k dead detection interrupt raw*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW (BIT(16)) #define RTC_CNTL_XTAL32K_DEAD_INT_RAW_M (BIT(16)) #define RTC_CNTL_XTAL32K_DEAD_INT_RAW_V 0x1 #define RTC_CNTL_XTAL32K_DEAD_INT_RAW_S 16 /* RTC_CNTL_SWD_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: super watch dog interrupt raw.*/ -#define RTC_CNTL_SWD_INT_RAW (BIT(15)) +/*description: super watch dog interrupt raw*/ +#define RTC_CNTL_SWD_INT_RAW (BIT(15)) #define RTC_CNTL_SWD_INT_RAW_M (BIT(15)) #define RTC_CNTL_SWD_INT_RAW_V 0x1 #define RTC_CNTL_SWD_INT_RAW_S 15 /* RTC_CNTL_SARADC2_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: saradc2 interrupt raw.*/ -#define RTC_CNTL_SARADC2_INT_RAW (BIT(14)) +/*description: saradc2 interrupt raw*/ +#define RTC_CNTL_SARADC2_INT_RAW (BIT(14)) #define RTC_CNTL_SARADC2_INT_RAW_M (BIT(14)) #define RTC_CNTL_SARADC2_INT_RAW_V 0x1 #define RTC_CNTL_SARADC2_INT_RAW_S 14 /* RTC_CNTL_COCPU_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: riscV cocpu interrupt raw.*/ -#define RTC_CNTL_COCPU_INT_RAW (BIT(13)) +/*description: riscV cocpu interrupt raw*/ +#define RTC_CNTL_COCPU_INT_RAW (BIT(13)) #define RTC_CNTL_COCPU_INT_RAW_M (BIT(13)) #define RTC_CNTL_COCPU_INT_RAW_V 0x1 #define RTC_CNTL_COCPU_INT_RAW_S 13 /* RTC_CNTL_TSENS_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: tsens interrupt raw.*/ -#define RTC_CNTL_TSENS_INT_RAW (BIT(12)) +/*description: tsens interrupt raw*/ +#define RTC_CNTL_TSENS_INT_RAW (BIT(12)) #define RTC_CNTL_TSENS_INT_RAW_M (BIT(12)) #define RTC_CNTL_TSENS_INT_RAW_V 0x1 #define RTC_CNTL_TSENS_INT_RAW_S 12 /* RTC_CNTL_SARADC1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: saradc1 interrupt raw.*/ -#define RTC_CNTL_SARADC1_INT_RAW (BIT(11)) +/*description: saradc1 interrupt raw*/ +#define RTC_CNTL_SARADC1_INT_RAW (BIT(11)) #define RTC_CNTL_SARADC1_INT_RAW_M (BIT(11)) #define RTC_CNTL_SARADC1_INT_RAW_V 0x1 #define RTC_CNTL_SARADC1_INT_RAW_S 11 /* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: RTC main timer interrupt raw.*/ -#define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(10)) +/*description: RTC main timer interrupt raw*/ +#define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(10)) #define RTC_CNTL_MAIN_TIMER_INT_RAW_M (BIT(10)) #define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x1 #define RTC_CNTL_MAIN_TIMER_INT_RAW_S 10 /* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: brown out interrupt raw.*/ -#define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(9)) +/*description: brown out interrupt raw*/ +#define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(9)) #define RTC_CNTL_BROWN_OUT_INT_RAW_M (BIT(9)) #define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x1 #define RTC_CNTL_BROWN_OUT_INT_RAW_S 9 /* RTC_CNTL_TOUCH_INACTIVE_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: touch inactive interrupt raw.*/ -#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW (BIT(8)) +/*description: touch inactive interrupt raw*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_M (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_V 0x1 #define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_S 8 /* RTC_CNTL_TOUCH_ACTIVE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: touch active interrupt raw.*/ -#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW (BIT(7)) +/*description: touch active interrupt raw*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW (BIT(7)) #define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_M (BIT(7)) #define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_V 0x1 #define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_S 7 /* RTC_CNTL_TOUCH_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: touch interrupt raw.*/ -#define RTC_CNTL_TOUCH_DONE_INT_RAW (BIT(6)) +/*description: touch interrupt raw*/ +#define RTC_CNTL_TOUCH_DONE_INT_RAW (BIT(6)) #define RTC_CNTL_TOUCH_DONE_INT_RAW_M (BIT(6)) #define RTC_CNTL_TOUCH_DONE_INT_RAW_V 0x1 #define RTC_CNTL_TOUCH_DONE_INT_RAW_S 6 /* RTC_CNTL_ULP_CP_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: ULP-coprocessor interrupt raw.*/ -#define RTC_CNTL_ULP_CP_INT_RAW (BIT(5)) +/*description: ULP-coprocessor interrupt raw*/ +#define RTC_CNTL_ULP_CP_INT_RAW (BIT(5)) #define RTC_CNTL_ULP_CP_INT_RAW_M (BIT(5)) #define RTC_CNTL_ULP_CP_INT_RAW_V 0x1 #define RTC_CNTL_ULP_CP_INT_RAW_S 5 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW (BIT(4)) +/*description: */ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW (BIT(4)) #define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_M (BIT(4)) #define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_V 0x1 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_S 4 /* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: RTC WDT interrupt raw.*/ -#define RTC_CNTL_WDT_INT_RAW (BIT(3)) +/*description: RTC WDT interrupt raw*/ +#define RTC_CNTL_WDT_INT_RAW (BIT(3)) #define RTC_CNTL_WDT_INT_RAW_M (BIT(3)) #define RTC_CNTL_WDT_INT_RAW_V 0x1 #define RTC_CNTL_WDT_INT_RAW_S 3 /* RTC_CNTL_SDIO_IDLE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: SDIO idle interrupt raw.*/ -#define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2)) +/*description: SDIO idle interrupt raw*/ +#define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2)) #define RTC_CNTL_SDIO_IDLE_INT_RAW_M (BIT(2)) #define RTC_CNTL_SDIO_IDLE_INT_RAW_V 0x1 #define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2 /* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: sleep reject interrupt raw.*/ -#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) +/*description: sleep reject interrupt raw*/ +#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) #define RTC_CNTL_SLP_REJECT_INT_RAW_M (BIT(1)) #define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x1 #define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 /* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: sleep wakeup interrupt raw.*/ -#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) +/*description: sleep wakeup interrupt raw*/ +#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) #define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (BIT(0)) #define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x1 #define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 -#define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x48) +#define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x0048) /* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST (BIT(20)) +/*description: */ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST (BIT(20)) #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_M (BIT(20)) #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_V 0x1 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_S 20 /* RTC_CNTL_GLITCH_DET_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: glitch_det_interrupt state.*/ -#define RTC_CNTL_GLITCH_DET_INT_ST (BIT(19)) +/*description: glitch_det_interrupt state*/ +#define RTC_CNTL_GLITCH_DET_INT_ST (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ST_M (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ST_V 0x1 #define RTC_CNTL_GLITCH_DET_INT_ST_S 19 /* RTC_CNTL_TOUCH_TIMEOUT_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: Touch timeout interrupt state.*/ -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST (BIT(18)) +/*description: Touch timeout interrupt state*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST (BIT(18)) #define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_M (BIT(18)) #define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_V 0x1 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_S 18 /* RTC_CNTL_COCPU_TRAP_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: cocpu trap interrupt state.*/ -#define RTC_CNTL_COCPU_TRAP_INT_ST (BIT(17)) +/*description: cocpu trap interrupt state*/ +#define RTC_CNTL_COCPU_TRAP_INT_ST (BIT(17)) #define RTC_CNTL_COCPU_TRAP_INT_ST_M (BIT(17)) #define RTC_CNTL_COCPU_TRAP_INT_ST_V 0x1 #define RTC_CNTL_COCPU_TRAP_INT_ST_S 17 /* RTC_CNTL_XTAL32K_DEAD_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: xtal32k dead detection interrupt state.*/ -#define RTC_CNTL_XTAL32K_DEAD_INT_ST (BIT(16)) +/*description: xtal32k dead detection interrupt state*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ST (BIT(16)) #define RTC_CNTL_XTAL32K_DEAD_INT_ST_M (BIT(16)) #define RTC_CNTL_XTAL32K_DEAD_INT_ST_V 0x1 #define RTC_CNTL_XTAL32K_DEAD_INT_ST_S 16 /* RTC_CNTL_SWD_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: super watch dog interrupt state.*/ -#define RTC_CNTL_SWD_INT_ST (BIT(15)) +/*description: super watch dog interrupt state*/ +#define RTC_CNTL_SWD_INT_ST (BIT(15)) #define RTC_CNTL_SWD_INT_ST_M (BIT(15)) #define RTC_CNTL_SWD_INT_ST_V 0x1 #define RTC_CNTL_SWD_INT_ST_S 15 /* RTC_CNTL_SARADC2_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: saradc2 interrupt state.*/ -#define RTC_CNTL_SARADC2_INT_ST (BIT(14)) +/*description: saradc2 interrupt state*/ +#define RTC_CNTL_SARADC2_INT_ST (BIT(14)) #define RTC_CNTL_SARADC2_INT_ST_M (BIT(14)) #define RTC_CNTL_SARADC2_INT_ST_V 0x1 #define RTC_CNTL_SARADC2_INT_ST_S 14 /* RTC_CNTL_COCPU_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: riscV cocpu interrupt state.*/ -#define RTC_CNTL_COCPU_INT_ST (BIT(13)) +/*description: riscV cocpu interrupt state*/ +#define RTC_CNTL_COCPU_INT_ST (BIT(13)) #define RTC_CNTL_COCPU_INT_ST_M (BIT(13)) #define RTC_CNTL_COCPU_INT_ST_V 0x1 #define RTC_CNTL_COCPU_INT_ST_S 13 /* RTC_CNTL_TSENS_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: tsens interrupt state.*/ -#define RTC_CNTL_TSENS_INT_ST (BIT(12)) +/*description: tsens interrupt state*/ +#define RTC_CNTL_TSENS_INT_ST (BIT(12)) #define RTC_CNTL_TSENS_INT_ST_M (BIT(12)) #define RTC_CNTL_TSENS_INT_ST_V 0x1 #define RTC_CNTL_TSENS_INT_ST_S 12 /* RTC_CNTL_SARADC1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: saradc1 interrupt state.*/ -#define RTC_CNTL_SARADC1_INT_ST (BIT(11)) +/*description: saradc1 interrupt state*/ +#define RTC_CNTL_SARADC1_INT_ST (BIT(11)) #define RTC_CNTL_SARADC1_INT_ST_M (BIT(11)) #define RTC_CNTL_SARADC1_INT_ST_V 0x1 #define RTC_CNTL_SARADC1_INT_ST_S 11 /* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: RTC main timer interrupt state.*/ -#define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(10)) +/*description: RTC main timer interrupt state*/ +#define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(10)) #define RTC_CNTL_MAIN_TIMER_INT_ST_M (BIT(10)) #define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x1 #define RTC_CNTL_MAIN_TIMER_INT_ST_S 10 /* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: brown out interrupt state.*/ -#define RTC_CNTL_BROWN_OUT_INT_ST (BIT(9)) +/*description: brown out interrupt state*/ +#define RTC_CNTL_BROWN_OUT_INT_ST (BIT(9)) #define RTC_CNTL_BROWN_OUT_INT_ST_M (BIT(9)) #define RTC_CNTL_BROWN_OUT_INT_ST_V 0x1 #define RTC_CNTL_BROWN_OUT_INT_ST_S 9 /* RTC_CNTL_TOUCH_INACTIVE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: touch inactive interrupt state.*/ -#define RTC_CNTL_TOUCH_INACTIVE_INT_ST (BIT(8)) +/*description: touch inactive interrupt state*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_ST (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_INT_ST_M (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_INT_ST_V 0x1 #define RTC_CNTL_TOUCH_INACTIVE_INT_ST_S 8 /* RTC_CNTL_TOUCH_ACTIVE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: touch active interrupt state.*/ -#define RTC_CNTL_TOUCH_ACTIVE_INT_ST (BIT(7)) +/*description: touch active interrupt state*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_ST (BIT(7)) #define RTC_CNTL_TOUCH_ACTIVE_INT_ST_M (BIT(7)) #define RTC_CNTL_TOUCH_ACTIVE_INT_ST_V 0x1 #define RTC_CNTL_TOUCH_ACTIVE_INT_ST_S 7 /* RTC_CNTL_TOUCH_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: touch done interrupt state.*/ -#define RTC_CNTL_TOUCH_DONE_INT_ST (BIT(6)) +/*description: touch done interrupt state*/ +#define RTC_CNTL_TOUCH_DONE_INT_ST (BIT(6)) #define RTC_CNTL_TOUCH_DONE_INT_ST_M (BIT(6)) #define RTC_CNTL_TOUCH_DONE_INT_ST_V 0x1 #define RTC_CNTL_TOUCH_DONE_INT_ST_S 6 /* RTC_CNTL_ULP_CP_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: ULP-coprocessor interrupt state.*/ -#define RTC_CNTL_ULP_CP_INT_ST (BIT(5)) +/*description: ULP-coprocessor interrupt state*/ +#define RTC_CNTL_ULP_CP_INT_ST (BIT(5)) #define RTC_CNTL_ULP_CP_INT_ST_M (BIT(5)) #define RTC_CNTL_ULP_CP_INT_ST_V 0x1 #define RTC_CNTL_ULP_CP_INT_ST_S 5 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST (BIT(4)) +/*description: */ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST (BIT(4)) #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_M (BIT(4)) #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_V 0x1 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_S 4 /* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: RTC WDT interrupt state.*/ -#define RTC_CNTL_WDT_INT_ST (BIT(3)) +/*description: RTC WDT interrupt state*/ +#define RTC_CNTL_WDT_INT_ST (BIT(3)) #define RTC_CNTL_WDT_INT_ST_M (BIT(3)) #define RTC_CNTL_WDT_INT_ST_V 0x1 #define RTC_CNTL_WDT_INT_ST_S 3 /* RTC_CNTL_SDIO_IDLE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: SDIO idle interrupt state.*/ -#define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2)) +/*description: SDIO idle interrupt state*/ +#define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2)) #define RTC_CNTL_SDIO_IDLE_INT_ST_M (BIT(2)) #define RTC_CNTL_SDIO_IDLE_INT_ST_V 0x1 #define RTC_CNTL_SDIO_IDLE_INT_ST_S 2 /* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: sleep reject interrupt state.*/ -#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) +/*description: sleep reject interrupt state*/ +#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) #define RTC_CNTL_SLP_REJECT_INT_ST_M (BIT(1)) #define RTC_CNTL_SLP_REJECT_INT_ST_V 0x1 #define RTC_CNTL_SLP_REJECT_INT_ST_S 1 /* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: sleep wakeup interrupt state.*/ -#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) +/*description: sleep wakeup interrupt state*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) #define RTC_CNTL_SLP_WAKEUP_INT_ST_M (BIT(0)) #define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x1 #define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 -#define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x4C) +#define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x004C) /* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR (BIT(20)) +/*description: */ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR (BIT(20)) #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_M (BIT(20)) #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V 0x1 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S 20 /* RTC_CNTL_GLITCH_DET_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Clear glitch det interrupt state.*/ -#define RTC_CNTL_GLITCH_DET_INT_CLR (BIT(19)) +/*description: Clear glitch det interrupt state*/ +#define RTC_CNTL_GLITCH_DET_INT_CLR (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_CLR_M (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_CLR_V 0x1 #define RTC_CNTL_GLITCH_DET_INT_CLR_S 19 /* RTC_CNTL_TOUCH_TIMEOUT_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: Clear touch timeout interrupt state.*/ -#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR (BIT(18)) +/*description: Clear touch timeout interrupt state*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR (BIT(18)) #define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_M (BIT(18)) #define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_V 0x1 #define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_S 18 /* RTC_CNTL_COCPU_TRAP_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Clear cocpu trap interrupt state.*/ -#define RTC_CNTL_COCPU_TRAP_INT_CLR (BIT(17)) +/*description: Clear cocpu trap interrupt state*/ +#define RTC_CNTL_COCPU_TRAP_INT_CLR (BIT(17)) #define RTC_CNTL_COCPU_TRAP_INT_CLR_M (BIT(17)) #define RTC_CNTL_COCPU_TRAP_INT_CLR_V 0x1 #define RTC_CNTL_COCPU_TRAP_INT_CLR_S 17 /* RTC_CNTL_XTAL32K_DEAD_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Clear RTC WDT interrupt state.*/ -#define RTC_CNTL_XTAL32K_DEAD_INT_CLR (BIT(16)) +/*description: Clear RTC WDT interrupt state*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR (BIT(16)) #define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M (BIT(16)) #define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V 0x1 #define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S 16 /* RTC_CNTL_SWD_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Clear super watch dog interrupt state.*/ -#define RTC_CNTL_SWD_INT_CLR (BIT(15)) +/*description: Clear super watch dog interrupt state*/ +#define RTC_CNTL_SWD_INT_CLR (BIT(15)) #define RTC_CNTL_SWD_INT_CLR_M (BIT(15)) #define RTC_CNTL_SWD_INT_CLR_V 0x1 #define RTC_CNTL_SWD_INT_CLR_S 15 /* RTC_CNTL_SARADC2_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Clear saradc2 interrupt state.*/ -#define RTC_CNTL_SARADC2_INT_CLR (BIT(14)) +/*description: Clear saradc2 interrupt state*/ +#define RTC_CNTL_SARADC2_INT_CLR (BIT(14)) #define RTC_CNTL_SARADC2_INT_CLR_M (BIT(14)) #define RTC_CNTL_SARADC2_INT_CLR_V 0x1 #define RTC_CNTL_SARADC2_INT_CLR_S 14 /* RTC_CNTL_COCPU_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Clear riscV cocpu interrupt state.*/ -#define RTC_CNTL_COCPU_INT_CLR (BIT(13)) +/*description: Clear riscV cocpu interrupt state*/ +#define RTC_CNTL_COCPU_INT_CLR (BIT(13)) #define RTC_CNTL_COCPU_INT_CLR_M (BIT(13)) #define RTC_CNTL_COCPU_INT_CLR_V 0x1 #define RTC_CNTL_COCPU_INT_CLR_S 13 /* RTC_CNTL_TSENS_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Clear tsens interrupt state.*/ -#define RTC_CNTL_TSENS_INT_CLR (BIT(12)) +/*description: Clear tsens interrupt state*/ +#define RTC_CNTL_TSENS_INT_CLR (BIT(12)) #define RTC_CNTL_TSENS_INT_CLR_M (BIT(12)) #define RTC_CNTL_TSENS_INT_CLR_V 0x1 #define RTC_CNTL_TSENS_INT_CLR_S 12 /* RTC_CNTL_SARADC1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Clear saradc1 interrupt state.*/ -#define RTC_CNTL_SARADC1_INT_CLR (BIT(11)) +/*description: Clear saradc1 interrupt state*/ +#define RTC_CNTL_SARADC1_INT_CLR (BIT(11)) #define RTC_CNTL_SARADC1_INT_CLR_M (BIT(11)) #define RTC_CNTL_SARADC1_INT_CLR_V 0x1 #define RTC_CNTL_SARADC1_INT_CLR_S 11 /* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Clear RTC main timer interrupt state.*/ -#define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(10)) +/*description: Clear RTC main timer interrupt state*/ +#define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(10)) #define RTC_CNTL_MAIN_TIMER_INT_CLR_M (BIT(10)) #define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x1 #define RTC_CNTL_MAIN_TIMER_INT_CLR_S 10 /* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Clear brown out interrupt state.*/ -#define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(9)) +/*description: Clear brown out interrupt state*/ +#define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(9)) #define RTC_CNTL_BROWN_OUT_INT_CLR_M (BIT(9)) #define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x1 #define RTC_CNTL_BROWN_OUT_INT_CLR_S 9 /* RTC_CNTL_TOUCH_INACTIVE_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Clear touch inactive interrupt state.*/ -#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR (BIT(8)) +/*description: Clear touch inactive interrupt state*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_M (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_V 0x1 #define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_S 8 /* RTC_CNTL_TOUCH_ACTIVE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Clear touch active interrupt state.*/ -#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR (BIT(7)) +/*description: Clear touch active interrupt state*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR (BIT(7)) #define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_M (BIT(7)) #define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_V 0x1 #define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_S 7 /* RTC_CNTL_TOUCH_DONE_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Clear touch done interrupt state.*/ -#define RTC_CNTL_TOUCH_DONE_INT_CLR (BIT(6)) +/*description: Clear touch done interrupt state*/ +#define RTC_CNTL_TOUCH_DONE_INT_CLR (BIT(6)) #define RTC_CNTL_TOUCH_DONE_INT_CLR_M (BIT(6)) #define RTC_CNTL_TOUCH_DONE_INT_CLR_V 0x1 #define RTC_CNTL_TOUCH_DONE_INT_CLR_S 6 /* RTC_CNTL_ULP_CP_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Clear ULP-coprocessor interrupt state.*/ -#define RTC_CNTL_ULP_CP_INT_CLR (BIT(5)) +/*description: Clear ULP-coprocessor interrupt state*/ +#define RTC_CNTL_ULP_CP_INT_CLR (BIT(5)) #define RTC_CNTL_ULP_CP_INT_CLR_M (BIT(5)) #define RTC_CNTL_ULP_CP_INT_CLR_V 0x1 #define RTC_CNTL_ULP_CP_INT_CLR_S 5 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR (BIT(4)) +/*description: */ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR (BIT(4)) #define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_M (BIT(4)) #define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_V 0x1 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_S 4 /* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Clear RTC WDT interrupt state.*/ -#define RTC_CNTL_WDT_INT_CLR (BIT(3)) +/*description: Clear RTC WDT interrupt state*/ +#define RTC_CNTL_WDT_INT_CLR (BIT(3)) #define RTC_CNTL_WDT_INT_CLR_M (BIT(3)) #define RTC_CNTL_WDT_INT_CLR_V 0x1 #define RTC_CNTL_WDT_INT_CLR_S 3 /* RTC_CNTL_SDIO_IDLE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Clear SDIO idle interrupt state.*/ -#define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2)) +/*description: Clear SDIO idle interrupt state*/ +#define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2)) #define RTC_CNTL_SDIO_IDLE_INT_CLR_M (BIT(2)) #define RTC_CNTL_SDIO_IDLE_INT_CLR_V 0x1 #define RTC_CNTL_SDIO_IDLE_INT_CLR_S 2 /* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Clear sleep reject interrupt state.*/ -#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) +/*description: Clear sleep reject interrupt state*/ +#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) #define RTC_CNTL_SLP_REJECT_INT_CLR_M (BIT(1)) #define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x1 #define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 /* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Clear sleep wakeup interrupt state.*/ -#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) +/*description: Clear sleep wakeup interrupt state*/ +#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) #define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0)) #define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1 #define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 -#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x50) +#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x0050) /* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: .*/ -#define RTC_CNTL_SCRATCH0 0xFFFFFFFF +/*description: */ +#define RTC_CNTL_SCRATCH0 0xFFFFFFFF #define RTC_CNTL_SCRATCH0_M ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S)) #define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF #define RTC_CNTL_SCRATCH0_S 0 -#define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x54) +#define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x0054) /* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: .*/ -#define RTC_CNTL_SCRATCH1 0xFFFFFFFF +/*description: */ +#define RTC_CNTL_SCRATCH1 0xFFFFFFFF #define RTC_CNTL_SCRATCH1_M ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S)) #define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF #define RTC_CNTL_SCRATCH1_S 0 -#define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x58) +#define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x0058) /* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: .*/ -#define RTC_CNTL_SCRATCH2 0xFFFFFFFF +/*description: */ +#define RTC_CNTL_SCRATCH2 0xFFFFFFFF #define RTC_CNTL_SCRATCH2_M ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S)) #define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF #define RTC_CNTL_SCRATCH2_S 0 -#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x5C) +#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x005C) /* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: .*/ -#define RTC_CNTL_SCRATCH3 0xFFFFFFFF +/*description: */ +#define RTC_CNTL_SCRATCH3 0xFFFFFFFF #define RTC_CNTL_SCRATCH3_M ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S)) #define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF #define RTC_CNTL_SCRATCH3_S 0 -#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60) +#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0060) /* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) +/*description: */ +#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) #define RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31)) #define RTC_CNTL_XTL_EXT_CTR_EN_V 0x1 #define RTC_CNTL_XTL_EXT_CTR_EN_S 31 /* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: 0: power down XTAL at high level.*/ -#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) +/*description: 0: power down XTAL at high level*/ +#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) #define RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30)) #define RTC_CNTL_XTL_EXT_CTR_LV_V 0x1 #define RTC_CNTL_XTL_EXT_CTR_LV_S 30 /* RTC_CNTL_XTAL32K_GPIO_SEL : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: XTAL_32K sel. 0: external XTAL_32K.*/ -#define RTC_CNTL_XTAL32K_GPIO_SEL (BIT(23)) +/*description: XTAL_32K sel. 0: external XTAL_32K*/ +#define RTC_CNTL_XTAL32K_GPIO_SEL (BIT(23)) #define RTC_CNTL_XTAL32K_GPIO_SEL_M (BIT(23)) #define RTC_CNTL_XTAL32K_GPIO_SEL_V 0x1 #define RTC_CNTL_XTAL32K_GPIO_SEL_S 23 /* RTC_CNTL_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */ -/*description: state of 32k_wdt.*/ -#define RTC_CNTL_WDT_STATE 0x00000007 +/*description: state of 32k_wdt*/ +#define RTC_CNTL_WDT_STATE 0x00000007 #define RTC_CNTL_WDT_STATE_M ((RTC_CNTL_WDT_STATE_V)<<(RTC_CNTL_WDT_STATE_S)) #define RTC_CNTL_WDT_STATE_V 0x7 #define RTC_CNTL_WDT_STATE_S 20 /* RTC_CNTL_DAC_XTAL_32K : R/W ;bitpos:[19:17] ;default: 3'd3 ; */ -/*description: DAC_XTAL_32K.*/ -#define RTC_CNTL_DAC_XTAL_32K 0x00000007 +/*description: DAC_XTAL_32K*/ +#define RTC_CNTL_DAC_XTAL_32K 0x00000007 #define RTC_CNTL_DAC_XTAL_32K_M ((RTC_CNTL_DAC_XTAL_32K_V)<<(RTC_CNTL_DAC_XTAL_32K_S)) #define RTC_CNTL_DAC_XTAL_32K_V 0x7 #define RTC_CNTL_DAC_XTAL_32K_S 17 /* RTC_CNTL_XPD_XTAL_32K : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: XPD_XTAL_32K.*/ -#define RTC_CNTL_XPD_XTAL_32K (BIT(16)) +/*description: XPD_XTAL_32K*/ +#define RTC_CNTL_XPD_XTAL_32K (BIT(16)) #define RTC_CNTL_XPD_XTAL_32K_M (BIT(16)) #define RTC_CNTL_XPD_XTAL_32K_V 0x1 #define RTC_CNTL_XPD_XTAL_32K_S 16 /* RTC_CNTL_DRES_XTAL_32K : R/W ;bitpos:[15:13] ;default: 3'd3 ; */ -/*description: DRES_XTAL_32K.*/ -#define RTC_CNTL_DRES_XTAL_32K 0x00000007 +/*description: DRES_XTAL_32K*/ +#define RTC_CNTL_DRES_XTAL_32K 0x00000007 #define RTC_CNTL_DRES_XTAL_32K_M ((RTC_CNTL_DRES_XTAL_32K_V)<<(RTC_CNTL_DRES_XTAL_32K_S)) #define RTC_CNTL_DRES_XTAL_32K_V 0x7 #define RTC_CNTL_DRES_XTAL_32K_S 13 /* RTC_CNTL_DGM_XTAL_32K : R/W ;bitpos:[12:10] ;default: 3'd3 ; */ -/*description: xtal_32k gm control.*/ -#define RTC_CNTL_DGM_XTAL_32K 0x00000007 +/*description: xtal_32k gm control*/ +#define RTC_CNTL_DGM_XTAL_32K 0x00000007 #define RTC_CNTL_DGM_XTAL_32K_M ((RTC_CNTL_DGM_XTAL_32K_V)<<(RTC_CNTL_DGM_XTAL_32K_S)) #define RTC_CNTL_DGM_XTAL_32K_V 0x7 #define RTC_CNTL_DGM_XTAL_32K_S 10 /* RTC_CNTL_DBUF_XTAL_32K : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: 0: single-end buffer 1: differential buffer.*/ -#define RTC_CNTL_DBUF_XTAL_32K (BIT(9)) +/*description: 0: single-end buffer 1: differential buffer*/ +#define RTC_CNTL_DBUF_XTAL_32K (BIT(9)) #define RTC_CNTL_DBUF_XTAL_32K_M (BIT(9)) #define RTC_CNTL_DBUF_XTAL_32K_V 0x1 #define RTC_CNTL_DBUF_XTAL_32K_S 9 /* RTC_CNTL_ENCKINIT_XTAL_32K : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: apply an internal clock to help xtal 32k to start.*/ -#define RTC_CNTL_ENCKINIT_XTAL_32K (BIT(8)) +/*description: apply an internal clock to help xtal 32k to start*/ +#define RTC_CNTL_ENCKINIT_XTAL_32K (BIT(8)) #define RTC_CNTL_ENCKINIT_XTAL_32K_M (BIT(8)) #define RTC_CNTL_ENCKINIT_XTAL_32K_V 0x1 #define RTC_CNTL_ENCKINIT_XTAL_32K_S 8 /* RTC_CNTL_XTAL32K_XPD_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */ -/*description: Xtal 32k xpd control by sw or fsm.*/ -#define RTC_CNTL_XTAL32K_XPD_FORCE (BIT(7)) +/*description: Xtal 32k xpd control by sw or fsm*/ +#define RTC_CNTL_XTAL32K_XPD_FORCE (BIT(7)) #define RTC_CNTL_XTAL32K_XPD_FORCE_M (BIT(7)) #define RTC_CNTL_XTAL32K_XPD_FORCE_V 0x1 #define RTC_CNTL_XTAL32K_XPD_FORCE_S 7 /* RTC_CNTL_XTAL32K_AUTO_RETURN : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: xtal 32k switch back xtal when xtal is restarted.*/ -#define RTC_CNTL_XTAL32K_AUTO_RETURN (BIT(6)) +/*description: xtal 32k switch back xtal when xtal is restarted*/ +#define RTC_CNTL_XTAL32K_AUTO_RETURN (BIT(6)) #define RTC_CNTL_XTAL32K_AUTO_RETURN_M (BIT(6)) #define RTC_CNTL_XTAL32K_AUTO_RETURN_V 0x1 #define RTC_CNTL_XTAL32K_AUTO_RETURN_S 6 /* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: xtal 32k restart xtal when xtal is dead.*/ -#define RTC_CNTL_XTAL32K_AUTO_RESTART (BIT(5)) +/*description: xtal 32k restart xtal when xtal is dead*/ +#define RTC_CNTL_XTAL32K_AUTO_RESTART (BIT(5)) #define RTC_CNTL_XTAL32K_AUTO_RESTART_M (BIT(5)) #define RTC_CNTL_XTAL32K_AUTO_RESTART_V 0x1 #define RTC_CNTL_XTAL32K_AUTO_RESTART_S 5 /* RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: xtal 32k switch to back up clock when xtal is dead.*/ -#define RTC_CNTL_XTAL32K_AUTO_BACKUP (BIT(4)) +/*description: xtal 32k switch to back up clock when xtal is dead*/ +#define RTC_CNTL_XTAL32K_AUTO_BACKUP (BIT(4)) #define RTC_CNTL_XTAL32K_AUTO_BACKUP_M (BIT(4)) #define RTC_CNTL_XTAL32K_AUTO_BACKUP_V 0x1 #define RTC_CNTL_XTAL32K_AUTO_BACKUP_S 4 /* RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: xtal 32k external xtal clock force on.*/ -#define RTC_CNTL_XTAL32K_EXT_CLK_FO (BIT(3)) +/*description: xtal 32k external xtal clock force on*/ +#define RTC_CNTL_XTAL32K_EXT_CLK_FO (BIT(3)) #define RTC_CNTL_XTAL32K_EXT_CLK_FO_M (BIT(3)) #define RTC_CNTL_XTAL32K_EXT_CLK_FO_V 0x1 #define RTC_CNTL_XTAL32K_EXT_CLK_FO_S 3 /* RTC_CNTL_XTAL32K_WDT_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: xtal 32k watch dog sw reset.*/ -#define RTC_CNTL_XTAL32K_WDT_RESET (BIT(2)) +/*description: xtal 32k watch dog sw reset*/ +#define RTC_CNTL_XTAL32K_WDT_RESET (BIT(2)) #define RTC_CNTL_XTAL32K_WDT_RESET_M (BIT(2)) #define RTC_CNTL_XTAL32K_WDT_RESET_V 0x1 #define RTC_CNTL_XTAL32K_WDT_RESET_S 2 /* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: xtal 32k watch dog clock force on.*/ -#define RTC_CNTL_XTAL32K_WDT_CLK_FO (BIT(1)) +/*description: xtal 32k watch dog clock force on*/ +#define RTC_CNTL_XTAL32K_WDT_CLK_FO (BIT(1)) #define RTC_CNTL_XTAL32K_WDT_CLK_FO_M (BIT(1)) #define RTC_CNTL_XTAL32K_WDT_CLK_FO_V 0x1 #define RTC_CNTL_XTAL32K_WDT_CLK_FO_S 1 /* RTC_CNTL_XTAL32K_WDT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: xtal 32k watch dog enable.*/ -#define RTC_CNTL_XTAL32K_WDT_EN (BIT(0)) +/*description: xtal 32k watch dog enable*/ +#define RTC_CNTL_XTAL32K_WDT_EN (BIT(0)) #define RTC_CNTL_XTAL32K_WDT_EN_M (BIT(0)) #define RTC_CNTL_XTAL32K_WDT_EN_V 0x1 #define RTC_CNTL_XTAL32K_WDT_EN_S 0 -#define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x64) +#define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0064) /* RTC_CNTL_EXT_WAKEUP1_LV : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31)) +/*description: */ +#define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31)) #define RTC_CNTL_EXT_WAKEUP1_LV_M (BIT(31)) #define RTC_CNTL_EXT_WAKEUP1_LV_V 0x1 #define RTC_CNTL_EXT_WAKEUP1_LV_S 31 /* RTC_CNTL_EXT_WAKEUP0_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: 0: external wakeup at low level.*/ -#define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30)) +/*description: 0: external wakeup at low level*/ +#define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30)) #define RTC_CNTL_EXT_WAKEUP0_LV_M (BIT(30)) #define RTC_CNTL_EXT_WAKEUP0_LV_V 0x1 #define RTC_CNTL_EXT_WAKEUP0_LV_S 30 /* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: enable filter for gpio wakeup event.*/ -#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(29)) +/*description: enable filter for gpio wakeup event*/ +#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(29)) #define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(29)) #define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 #define RTC_CNTL_GPIO_WAKEUP_FILTER_S 29 -#define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x68) +#define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0068) /* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: enable reject for deep sleep.*/ -#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(31)) +/*description: enable reject for deep sleep*/ +#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(31)) #define RTC_CNTL_DEEP_SLP_REJECT_EN_M (BIT(31)) #define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x1 #define RTC_CNTL_DEEP_SLP_REJECT_EN_S 31 /* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: enable reject for light sleep.*/ -#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(30)) +/*description: enable reject for light sleep*/ +#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(30)) #define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(30)) #define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1 #define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 30 /* RTC_CNTL_SLEEP_REJECT_ENA : R/W ;bitpos:[29:12] ;default: 17'd0 ; */ -/*description: sleep reject enable.*/ -#define RTC_CNTL_SLEEP_REJECT_ENA 0x0003FFFF +/*description: sleep reject enable*/ +#define RTC_CNTL_SLEEP_REJECT_ENA 0x0003FFFF #define RTC_CNTL_SLEEP_REJECT_ENA_M ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S)) #define RTC_CNTL_SLEEP_REJECT_ENA_V 0x3FFFF #define RTC_CNTL_SLEEP_REJECT_ENA_S 12 -#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6C) +#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x006C) /* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */ -/*description: .*/ -#define RTC_CNTL_CPUPERIOD_SEL 0x00000003 +/*description: */ +#define RTC_CNTL_CPUPERIOD_SEL 0x00000003 #define RTC_CNTL_CPUPERIOD_SEL_M ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S)) #define RTC_CNTL_CPUPERIOD_SEL_V 0x3 #define RTC_CNTL_CPUPERIOD_SEL_S 30 /* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: CPU sel option.*/ -#define RTC_CNTL_CPUSEL_CONF (BIT(29)) +/*description: CPU sel option*/ +#define RTC_CNTL_CPUSEL_CONF (BIT(29)) #define RTC_CNTL_CPUSEL_CONF_M (BIT(29)) #define RTC_CNTL_CPUSEL_CONF_V 0x1 #define RTC_CNTL_CPUSEL_CONF_S 29 -#define RTC_CNTL_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70) +#define RTC_CNTL_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0070) /* RTC_CNTL_SDIO_ACT_DNUM : R/W ;bitpos:[31:22] ;default: 10'b0 ; */ -/*description: .*/ -#define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF +/*description: */ +#define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF #define RTC_CNTL_SDIO_ACT_DNUM_M ((RTC_CNTL_SDIO_ACT_DNUM_V)<<(RTC_CNTL_SDIO_ACT_DNUM_S)) #define RTC_CNTL_SDIO_ACT_DNUM_V 0x3FF #define RTC_CNTL_SDIO_ACT_DNUM_S 22 -#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74) +#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0074) /* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ -/*description: .*/ -#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 +/*description: */ +#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 #define RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S)) #define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3 #define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 /* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: fast_clk_rtc sel. 0: XTAL div 4.*/ -#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) +/*description: fast_clk_rtc sel. 0: XTAL div 4*/ +#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) #define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29)) #define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1 #define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 /* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ -/*description: CK8M force power up.*/ -#define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) +/*description: CK8M force power up*/ +#define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) #define RTC_CNTL_CK8M_FORCE_PU_M (BIT(26)) #define RTC_CNTL_CK8M_FORCE_PU_V 0x1 #define RTC_CNTL_CK8M_FORCE_PU_S 26 /* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ -/*description: CK8M force power down.*/ -#define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) +/*description: CK8M force power down*/ +#define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) #define RTC_CNTL_CK8M_FORCE_PD_M (BIT(25)) #define RTC_CNTL_CK8M_FORCE_PD_V 0x1 #define RTC_CNTL_CK8M_FORCE_PD_S 25 /* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd172 ; */ -/*description: CK8M_DFREQ.*/ -#define RTC_CNTL_CK8M_DFREQ 0x000000FF +/*description: CK8M_DFREQ*/ +#define RTC_CNTL_CK8M_DFREQ 0x000000FF #define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) #define RTC_CNTL_CK8M_DFREQ_V 0xFF #define RTC_CNTL_CK8M_DFREQ_S 17 /* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: CK8M force no gating during sleep.*/ -#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) +/*description: CK8M force no gating during sleep*/ +#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) #define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16)) #define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1 #define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 /* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: XTAL force no gating during sleep.*/ -#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) +/*description: XTAL force no gating during sleep*/ +#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) #define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(15)) #define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1 #define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 /* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd3 ; */ -/*description: divider = reg_ck8m_div_sel + 1.*/ -#define RTC_CNTL_CK8M_DIV_SEL 0x00000007 +/*description: divider = reg_ck8m_div_sel + 1*/ +#define RTC_CNTL_CK8M_DIV_SEL 0x00000007 #define RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S)) #define RTC_CNTL_CK8M_DIV_SEL_V 0x7 #define RTC_CNTL_CK8M_DIV_SEL_S 12 /* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: enable CK8M for digital core (no relationship with RTC core).*/ -#define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) +/*description: enable CK8M for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) #define RTC_CNTL_DIG_CLK8M_EN_M (BIT(10)) #define RTC_CNTL_DIG_CLK8M_EN_V 0x1 #define RTC_CNTL_DIG_CLK8M_EN_S 10 /* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ -/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core).*/ -#define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) +/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) #define RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9)) #define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x1 #define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 /* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core).*/ -#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) +/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) #define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(8)) #define RTC_CNTL_DIG_XTAL32K_EN_V 0x1 #define RTC_CNTL_DIG_XTAL32K_EN_S 8 /* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: 1: CK8M_D256_OUT is actually CK8M.*/ -#define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) +/*description: 1: CK8M_D256_OUT is actually CK8M*/ +#define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) #define RTC_CNTL_ENB_CK8M_DIV_M (BIT(7)) #define RTC_CNTL_ENB_CK8M_DIV_V 0x1 #define RTC_CNTL_ENB_CK8M_DIV_S 7 /* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */ -/*description: disable CK8M and CK8M_D256_OUT.*/ -#define RTC_CNTL_ENB_CK8M (BIT(6)) +/*description: disable CK8M and CK8M_D256_OUT*/ +#define RTC_CNTL_ENB_CK8M (BIT(6)) #define RTC_CNTL_ENB_CK8M_M (BIT(6)) #define RTC_CNTL_ENB_CK8M_V 0x1 #define RTC_CNTL_ENB_CK8M_S 6 /* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */ -/*description: CK8M_D256_OUT divider. 00: div128.*/ -#define RTC_CNTL_CK8M_DIV 0x00000003 +/*description: CK8M_D256_OUT divider. 00: div128*/ +#define RTC_CNTL_CK8M_DIV 0x00000003 #define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S)) #define RTC_CNTL_CK8M_DIV_V 0x3 #define RTC_CNTL_CK8M_DIV_S 4 /* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel.*/ -#define RTC_CNTL_CK8M_DIV_SEL_VLD (BIT(3)) +/*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/ +#define RTC_CNTL_CK8M_DIV_SEL_VLD (BIT(3)) #define RTC_CNTL_CK8M_DIV_SEL_VLD_M (BIT(3)) #define RTC_CNTL_CK8M_DIV_SEL_VLD_V 0x1 #define RTC_CNTL_CK8M_DIV_SEL_VLD_S 3 -#define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x78) +#define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0078) /* RTC_CNTL_SLOW_CLK_NEXT_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_SLOW_CLK_NEXT_EDGE (BIT(31)) +/*description: */ +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE (BIT(31)) #define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M (BIT(31)) #define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V 0x1 #define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S 31 /* RTC_CNTL_ANA_CLK_DIV : R/W ;bitpos:[30:23] ;default: 8'd0 ; */ -/*description: .*/ -#define RTC_CNTL_ANA_CLK_DIV 0x000000FF +/*description: */ +#define RTC_CNTL_ANA_CLK_DIV 0x000000FF #define RTC_CNTL_ANA_CLK_DIV_M ((RTC_CNTL_ANA_CLK_DIV_V)<<(RTC_CNTL_ANA_CLK_DIV_S)) #define RTC_CNTL_ANA_CLK_DIV_V 0xFF #define RTC_CNTL_ANA_CLK_DIV_S 23 /* RTC_CNTL_ANA_CLK_DIV_VLD : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div.*/ -#define RTC_CNTL_ANA_CLK_DIV_VLD (BIT(22)) +/*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/ +#define RTC_CNTL_ANA_CLK_DIV_VLD (BIT(22)) #define RTC_CNTL_ANA_CLK_DIV_VLD_M (BIT(22)) #define RTC_CNTL_ANA_CLK_DIV_VLD_V 0x1 #define RTC_CNTL_ANA_CLK_DIV_VLD_S 22 -#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x7C) +#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x007C) /* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: .*/ -#define RTC_CNTL_XPD_SDIO_REG (BIT(31)) +/*description: */ +#define RTC_CNTL_XPD_SDIO_REG (BIT(31)) #define RTC_CNTL_XPD_SDIO_REG_M (BIT(31)) #define RTC_CNTL_XPD_SDIO_REG_V 0x1 #define RTC_CNTL_XPD_SDIO_REG_S 31 /* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */ -/*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1.*/ -#define RTC_CNTL_DREFH_SDIO 0x00000003 +/*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFH_SDIO 0x00000003 #define RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S)) #define RTC_CNTL_DREFH_SDIO_V 0x3 #define RTC_CNTL_DREFH_SDIO_S 29 /* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b01 ; */ -/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1.*/ -#define RTC_CNTL_DREFM_SDIO 0x00000003 +/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFM_SDIO 0x00000003 #define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S)) #define RTC_CNTL_DREFM_SDIO_V 0x3 #define RTC_CNTL_DREFM_SDIO_S 27 /* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */ -/*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1.*/ -#define RTC_CNTL_DREFL_SDIO 0x00000003 +/*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFL_SDIO 0x00000003 #define RTC_CNTL_DREFL_SDIO_M ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S)) #define RTC_CNTL_DREFL_SDIO_V 0x3 #define RTC_CNTL_DREFL_SDIO_S 25 /* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */ -/*description: read only register for REG1P8_READY.*/ -#define RTC_CNTL_REG1P8_READY (BIT(24)) +/*description: read only register for REG1P8_READY*/ +#define RTC_CNTL_REG1P8_READY (BIT(24)) #define RTC_CNTL_REG1P8_READY_M (BIT(24)) #define RTC_CNTL_REG1P8_READY_V 0x1 #define RTC_CNTL_REG1P8_READY_S 24 /* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */ -/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1.*/ -#define RTC_CNTL_SDIO_TIEH (BIT(23)) +/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_SDIO_TIEH (BIT(23)) #define RTC_CNTL_SDIO_TIEH_M (BIT(23)) #define RTC_CNTL_SDIO_TIEH_V 0x1 #define RTC_CNTL_SDIO_TIEH_S 23 /* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: 1: use SW option to control SDIO_REG.*/ -#define RTC_CNTL_SDIO_FORCE (BIT(22)) +/*description: 1: use SW option to control SDIO_REG*/ +#define RTC_CNTL_SDIO_FORCE (BIT(22)) #define RTC_CNTL_SDIO_FORCE_M (BIT(22)) #define RTC_CNTL_SDIO_FORCE_V 0x1 #define RTC_CNTL_SDIO_FORCE_S 22 /* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ -/*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0.*/ -#define RTC_CNTL_SDIO_PD_EN (BIT(21)) +/*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ +#define RTC_CNTL_SDIO_PD_EN (BIT(21)) #define RTC_CNTL_SDIO_PD_EN_M (BIT(21)) #define RTC_CNTL_SDIO_PD_EN_V 0x1 #define RTC_CNTL_SDIO_PD_EN_S 21 /* RTC_CNTL_SDIO_ENCURLIM : R/W ;bitpos:[20] ;default: 1'd1 ; */ -/*description: enable current limit.*/ -#define RTC_CNTL_SDIO_ENCURLIM (BIT(20)) +/*description: enable current limit*/ +#define RTC_CNTL_SDIO_ENCURLIM (BIT(20)) #define RTC_CNTL_SDIO_ENCURLIM_M (BIT(20)) #define RTC_CNTL_SDIO_ENCURLIM_V 0x1 #define RTC_CNTL_SDIO_ENCURLIM_S 20 /* RTC_CNTL_SDIO_MODECURLIM : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: select current limit mode.*/ -#define RTC_CNTL_SDIO_MODECURLIM (BIT(19)) +/*description: select current limit mode*/ +#define RTC_CNTL_SDIO_MODECURLIM (BIT(19)) #define RTC_CNTL_SDIO_MODECURLIM_M (BIT(19)) #define RTC_CNTL_SDIO_MODECURLIM_V 0x1 #define RTC_CNTL_SDIO_MODECURLIM_S 19 /* RTC_CNTL_SDIO_DCURLIM : R/W ;bitpos:[18:16] ;default: 3'd0 ; */ -/*description: tune current limit threshold when tieh = 0. About 800mA/(8+d).*/ -#define RTC_CNTL_SDIO_DCURLIM 0x00000007 +/*description: tune current limit threshold when tieh = 0. About 800mA/(8+d)*/ +#define RTC_CNTL_SDIO_DCURLIM 0x00000007 #define RTC_CNTL_SDIO_DCURLIM_M ((RTC_CNTL_SDIO_DCURLIM_V)<<(RTC_CNTL_SDIO_DCURLIM_S)) #define RTC_CNTL_SDIO_DCURLIM_V 0x7 #define RTC_CNTL_SDIO_DCURLIM_S 16 /* RTC_CNTL_SDIO_EN_INITI : R/W ;bitpos:[15] ;default: 1'd1 ; */ -/*description: 0 to set init[1:0]=0.*/ -#define RTC_CNTL_SDIO_EN_INITI (BIT(15)) +/*description: 0 to set init[1:0]=0*/ +#define RTC_CNTL_SDIO_EN_INITI (BIT(15)) #define RTC_CNTL_SDIO_EN_INITI_M (BIT(15)) #define RTC_CNTL_SDIO_EN_INITI_V 0x1 #define RTC_CNTL_SDIO_EN_INITI_S 15 /* RTC_CNTL_SDIO_INITI : R/W ;bitpos:[14:13] ;default: 2'd1 ; */ -/*description: add resistor from ldo output to ground. 0: no res.*/ -#define RTC_CNTL_SDIO_INITI 0x00000003 +/*description: add resistor from ldo output to ground. 0: no res*/ +#define RTC_CNTL_SDIO_INITI 0x00000003 #define RTC_CNTL_SDIO_INITI_M ((RTC_CNTL_SDIO_INITI_V)<<(RTC_CNTL_SDIO_INITI_S)) #define RTC_CNTL_SDIO_INITI_V 0x3 #define RTC_CNTL_SDIO_INITI_S 13 /* RTC_CNTL_SDIO_DCAP : R/W ;bitpos:[12:11] ;default: 2'b11 ; */ -/*description: ability to prevent LDO from overshoot.*/ -#define RTC_CNTL_SDIO_DCAP 0x00000003 +/*description: ability to prevent LDO from overshoot*/ +#define RTC_CNTL_SDIO_DCAP 0x00000003 #define RTC_CNTL_SDIO_DCAP_M ((RTC_CNTL_SDIO_DCAP_V)<<(RTC_CNTL_SDIO_DCAP_S)) #define RTC_CNTL_SDIO_DCAP_V 0x3 #define RTC_CNTL_SDIO_DCAP_S 11 /* RTC_CNTL_SDIO_DTHDRV : R/W ;bitpos:[10:9] ;default: 2'b11 ; */ -/*description: Tieh = 1 mode drive ability. Initially set to 0 to limit charge current.*/ -#define RTC_CNTL_SDIO_DTHDRV 0x00000003 +/*description: Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/ +#define RTC_CNTL_SDIO_DTHDRV 0x00000003 #define RTC_CNTL_SDIO_DTHDRV_M ((RTC_CNTL_SDIO_DTHDRV_V)<<(RTC_CNTL_SDIO_DTHDRV_S)) #define RTC_CNTL_SDIO_DTHDRV_V 0x3 #define RTC_CNTL_SDIO_DTHDRV_S 9 /* RTC_CNTL_SDIO_TIMER_TARGET : R/W ;bitpos:[7:0] ;default: 8'd10 ; */ -/*description: timer count to apply reg_sdio_dcap after sdio power on.*/ -#define RTC_CNTL_SDIO_TIMER_TARGET 0x000000FF +/*description: timer count to apply reg_sdio_dcap after sdio power on*/ +#define RTC_CNTL_SDIO_TIMER_TARGET 0x000000FF #define RTC_CNTL_SDIO_TIMER_TARGET_M ((RTC_CNTL_SDIO_TIMER_TARGET_V)<<(RTC_CNTL_SDIO_TIMER_TARGET_S)) #define RTC_CNTL_SDIO_TIMER_TARGET_V 0xFF #define RTC_CNTL_SDIO_TIMER_TARGET_S 0 -#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x80) +#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0080) +/* RTC_CNTL_DBG_ATTEN_WAKEUP : R/W ;bitpos:[29:26] ;default: 4'd0 ; */ +/*description: */ +#define RTC_CNTL_DBG_ATTEN_WAKEUP 0x0000000F +#define RTC_CNTL_DBG_ATTEN_WAKEUP_M ((RTC_CNTL_DBG_ATTEN_WAKEUP_V)<<(RTC_CNTL_DBG_ATTEN_WAKEUP_S)) +#define RTC_CNTL_DBG_ATTEN_WAKEUP_V 0xF +#define RTC_CNTL_DBG_ATTEN_WAKEUP_S 26 /* RTC_CNTL_DBG_ATTEN_MONITOR : R/W ;bitpos:[25:22] ;default: 4'd0 ; */ -/*description: DBG_ATTEN when rtc in monitor state.*/ -#define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000F +/*description: DBG_ATTEN when rtc in monitor state*/ +#define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000F #define RTC_CNTL_DBG_ATTEN_MONITOR_M ((RTC_CNTL_DBG_ATTEN_MONITOR_V)<<(RTC_CNTL_DBG_ATTEN_MONITOR_S)) #define RTC_CNTL_DBG_ATTEN_MONITOR_V 0xF #define RTC_CNTL_DBG_ATTEN_MONITOR_S 22 /* RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W ;bitpos:[21:18] ;default: 4'd0 ; */ -/*description: DBG_ATTEN when rtc in sleep state.*/ -#define RTC_CNTL_DBG_ATTEN_DEEP_SLP 0x0000000F +/*description: DBG_ATTEN when rtc in sleep state*/ +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP 0x0000000F #define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V)<<(RTC_CNTL_DBG_ATTEN_DEEP_SLP_S)) #define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V 0xF #define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S 18 /* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: bias_sleep when rtc in monitor state.*/ -#define RTC_CNTL_BIAS_SLEEP_MONITOR (BIT(17)) +/*description: bias_sleep when rtc in monitor state*/ +#define RTC_CNTL_BIAS_SLEEP_MONITOR (BIT(17)) #define RTC_CNTL_BIAS_SLEEP_MONITOR_M (BIT(17)) #define RTC_CNTL_BIAS_SLEEP_MONITOR_V 0x1 #define RTC_CNTL_BIAS_SLEEP_MONITOR_S 17 /* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W ;bitpos:[16] ;default: 1'b1 ; */ -/*description: bias_sleep when rtc in sleep_state.*/ -#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP (BIT(16)) +/*description: bias_sleep when rtc in sleep_state*/ +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP (BIT(16)) #define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M (BIT(16)) #define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V 0x1 #define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S 16 /* RTC_CNTL_PD_CUR_MONITOR : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: xpd cur when rtc in monitor state.*/ -#define RTC_CNTL_PD_CUR_MONITOR (BIT(15)) +/*description: xpd cur when rtc in monitor state*/ +#define RTC_CNTL_PD_CUR_MONITOR (BIT(15)) #define RTC_CNTL_PD_CUR_MONITOR_M (BIT(15)) #define RTC_CNTL_PD_CUR_MONITOR_V 0x1 #define RTC_CNTL_PD_CUR_MONITOR_S 15 /* RTC_CNTL_PD_CUR_DEEP_SLP : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: xpd cur when rtc in sleep_state.*/ -#define RTC_CNTL_PD_CUR_DEEP_SLP (BIT(14)) +/*description: xpd cur when rtc in sleep_state*/ +#define RTC_CNTL_PD_CUR_DEEP_SLP (BIT(14)) #define RTC_CNTL_PD_CUR_DEEP_SLP_M (BIT(14)) #define RTC_CNTL_PD_CUR_DEEP_SLP_V 0x1 #define RTC_CNTL_PD_CUR_DEEP_SLP_S 14 /* RTC_CNTL_BIAS_BUF_MONITOR : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13)) +/*description: */ +#define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13)) #define RTC_CNTL_BIAS_BUF_MONITOR_M (BIT(13)) #define RTC_CNTL_BIAS_BUF_MONITOR_V 0x1 #define RTC_CNTL_BIAS_BUF_MONITOR_S 13 /* RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_BIAS_BUF_DEEP_SLP (BIT(12)) +/*description: */ +#define RTC_CNTL_BIAS_BUF_DEEP_SLP (BIT(12)) #define RTC_CNTL_BIAS_BUF_DEEP_SLP_M (BIT(12)) #define RTC_CNTL_BIAS_BUF_DEEP_SLP_V 0x1 #define RTC_CNTL_BIAS_BUF_DEEP_SLP_S 12 /* RTC_CNTL_BIAS_BUF_WAKE : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: .*/ -#define RTC_CNTL_BIAS_BUF_WAKE (BIT(11)) +/*description: */ +#define RTC_CNTL_BIAS_BUF_WAKE (BIT(11)) #define RTC_CNTL_BIAS_BUF_WAKE_M (BIT(11)) #define RTC_CNTL_BIAS_BUF_WAKE_V 0x1 #define RTC_CNTL_BIAS_BUF_WAKE_S 11 /* RTC_CNTL_BIAS_BUF_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_BIAS_BUF_IDLE (BIT(10)) +/*description: */ +#define RTC_CNTL_BIAS_BUF_IDLE (BIT(10)) #define RTC_CNTL_BIAS_BUF_IDLE_M (BIT(10)) #define RTC_CNTL_BIAS_BUF_IDLE_V 0x1 #define RTC_CNTL_BIAS_BUF_IDLE_S 10 -#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x84) +#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x0084) /* RTC_CNTL_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ -/*description: .*/ -#define RTC_CNTL_REGULATOR_FORCE_PU (BIT(31)) +/*description: */ +#define RTC_CNTL_REGULATOR_FORCE_PU (BIT(31)) #define RTC_CNTL_REGULATOR_FORCE_PU_M (BIT(31)) #define RTC_CNTL_REGULATOR_FORCE_PU_V 0x1 #define RTC_CNTL_REGULATOR_FORCE_PU_S 31 /* RTC_CNTL_REGULATOR_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0 -.8v or lower ).*/ -#define RTC_CNTL_REGULATOR_FORCE_PD (BIT(30)) +/*description: RTC_REG force power down (for RTC_REG power down means decrease + the voltage to 0.8v or lower )*/ +#define RTC_CNTL_REGULATOR_FORCE_PD (BIT(30)) #define RTC_CNTL_REGULATOR_FORCE_PD_M (BIT(30)) #define RTC_CNTL_REGULATOR_FORCE_PD_V 0x1 #define RTC_CNTL_REGULATOR_FORCE_PD_S 30 /* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */ -/*description: RTC_DBOOST force power up.*/ -#define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) +/*description: RTC_DBOOST force power up*/ +#define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) #define RTC_CNTL_DBOOST_FORCE_PU_M (BIT(29)) #define RTC_CNTL_DBOOST_FORCE_PU_V 0x1 #define RTC_CNTL_DBOOST_FORCE_PU_S 29 /* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: RTC_DBOOST force power down.*/ -#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) +/*description: RTC_DBOOST force power down*/ +#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) #define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28)) #define RTC_CNTL_DBOOST_FORCE_PD_V 0x1 #define RTC_CNTL_DBOOST_FORCE_PD_S 28 +/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, + * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. + * Valid if RTC_CNTL_DBG_ATTEN is 0. + */ +#define RTC_CNTL_DIG_DBIAS_0V85 0 +#define RTC_CNTL_DIG_DBIAS_0V90 1 +#define RTC_CNTL_DIG_DBIAS_0V95 2 +#define RTC_CNTL_DIG_DBIAS_1V00 3 +#define RTC_CNTL_DIG_DBIAS_1V05 4 +#define RTC_CNTL_DIG_DBIAS_1V10 5 +#define RTC_CNTL_DIG_DBIAS_1V15 6 +#define RTC_CNTL_DIG_DBIAS_1V20 7 + + /* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */ -/*description: SCK_DCAP.*/ -#define RTC_CNTL_SCK_DCAP 0x000000FF +/*description: SCK_DCAP*/ +#define RTC_CNTL_SCK_DCAP 0x000000FF #define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) #define RTC_CNTL_SCK_DCAP_V 0xFF #define RTC_CNTL_SCK_DCAP_S 14 /* RTC_CNTL_DIG_CAL_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_DIG_CAL_EN (BIT(7)) +/*description: */ +#define RTC_CNTL_DIG_CAL_EN (BIT(7)) #define RTC_CNTL_DIG_CAL_EN_M (BIT(7)) #define RTC_CNTL_DIG_CAL_EN_V 0x1 #define RTC_CNTL_DIG_CAL_EN_S 7 -#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x88) +#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x0088) /* RTC_CNTL_PAD_FORCE_HOLD : R/W ;bitpos:[21] ;default: 1'd0 ; */ -/*description: rtc pad force hold.*/ -#define RTC_CNTL_PAD_FORCE_HOLD (BIT(21)) +/*description: rtc pad force hold*/ +#define RTC_CNTL_PAD_FORCE_HOLD (BIT(21)) #define RTC_CNTL_PAD_FORCE_HOLD_M (BIT(21)) #define RTC_CNTL_PAD_FORCE_HOLD_V 0x1 #define RTC_CNTL_PAD_FORCE_HOLD_S 21 /* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: enable power down rtc_peri in sleep .*/ -#define RTC_CNTL_PD_EN (BIT(20)) +/*description: enable power down rtc_peri in sleep*/ +#define RTC_CNTL_PD_EN (BIT(20)) #define RTC_CNTL_PD_EN_M (BIT(20)) #define RTC_CNTL_PD_EN_V 0x1 #define RTC_CNTL_PD_EN_S 20 /* RTC_CNTL_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd0 ; */ -/*description: rtc_peri force power up.*/ -#define RTC_CNTL_FORCE_PU (BIT(19)) +/*description: rtc_peri force power up*/ +#define RTC_CNTL_FORCE_PU (BIT(19)) #define RTC_CNTL_FORCE_PU_M (BIT(19)) #define RTC_CNTL_FORCE_PU_V 0x1 #define RTC_CNTL_FORCE_PU_S 19 /* RTC_CNTL_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: rtc_peri force power down.*/ -#define RTC_CNTL_FORCE_PD (BIT(18)) +/*description: rtc_peri force power down*/ +#define RTC_CNTL_FORCE_PD (BIT(18)) #define RTC_CNTL_FORCE_PD_M (BIT(18)) #define RTC_CNTL_FORCE_PD_V 0x1 #define RTC_CNTL_FORCE_PD_S 18 -/* RTC_CNTL_SLOWMEM_PD_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: enable power down RTC memory in sleep.*/ -#define RTC_CNTL_SLOWMEM_PD_EN (BIT(17)) -#define RTC_CNTL_SLOWMEM_PD_EN_M (BIT(17)) -#define RTC_CNTL_SLOWMEM_PD_EN_V 0x1 -#define RTC_CNTL_SLOWMEM_PD_EN_S 17 -/* RTC_CNTL_SLOWMEM_FORCE_PU : R/W ;bitpos:[16] ;default: 1'b1 ; */ -/*description: RTC memory force power up.*/ -#define RTC_CNTL_SLOWMEM_FORCE_PU (BIT(16)) -#define RTC_CNTL_SLOWMEM_FORCE_PU_M (BIT(16)) -#define RTC_CNTL_SLOWMEM_FORCE_PU_V 0x1 -#define RTC_CNTL_SLOWMEM_FORCE_PU_S 16 -/* RTC_CNTL_SLOWMEM_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: RTC memory force power down.*/ -#define RTC_CNTL_SLOWMEM_FORCE_PD (BIT(15)) -#define RTC_CNTL_SLOWMEM_FORCE_PD_M (BIT(15)) -#define RTC_CNTL_SLOWMEM_FORCE_PD_V 0x1 -#define RTC_CNTL_SLOWMEM_FORCE_PD_S 15 -/* RTC_CNTL_FASTMEM_PD_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: enable power down fast RTC memory in sleep.*/ -#define RTC_CNTL_FASTMEM_PD_EN (BIT(14)) -#define RTC_CNTL_FASTMEM_PD_EN_M (BIT(14)) -#define RTC_CNTL_FASTMEM_PD_EN_V 0x1 -#define RTC_CNTL_FASTMEM_PD_EN_S 14 -/* RTC_CNTL_FASTMEM_FORCE_PU : R/W ;bitpos:[13] ;default: 1'b1 ; */ -/*description: Fast RTC memory force power up.*/ -#define RTC_CNTL_FASTMEM_FORCE_PU (BIT(13)) -#define RTC_CNTL_FASTMEM_FORCE_PU_M (BIT(13)) -#define RTC_CNTL_FASTMEM_FORCE_PU_V 0x1 -#define RTC_CNTL_FASTMEM_FORCE_PU_S 13 -/* RTC_CNTL_FASTMEM_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Fast RTC memory force power down.*/ -#define RTC_CNTL_FASTMEM_FORCE_PD (BIT(12)) -#define RTC_CNTL_FASTMEM_FORCE_PD_M (BIT(12)) -#define RTC_CNTL_FASTMEM_FORCE_PD_V 0x1 -#define RTC_CNTL_FASTMEM_FORCE_PD_S 12 /* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: RTC memory force no PD.*/ -#define RTC_CNTL_SLOWMEM_FORCE_LPU (BIT(11)) +/*description: RTC memory force no PD*/ +#define RTC_CNTL_SLOWMEM_FORCE_LPU (BIT(11)) #define RTC_CNTL_SLOWMEM_FORCE_LPU_M (BIT(11)) #define RTC_CNTL_SLOWMEM_FORCE_LPU_V 0x1 #define RTC_CNTL_SLOWMEM_FORCE_LPU_S 11 /* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: RTC memory force PD.*/ -#define RTC_CNTL_SLOWMEM_FORCE_LPD (BIT(10)) +/*description: RTC memory force PD*/ +#define RTC_CNTL_SLOWMEM_FORCE_LPD (BIT(10)) #define RTC_CNTL_SLOWMEM_FORCE_LPD_M (BIT(10)) #define RTC_CNTL_SLOWMEM_FORCE_LPD_V 0x1 #define RTC_CNTL_SLOWMEM_FORCE_LPD_S 10 /* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: 1: RTC memory PD following CPU.*/ -#define RTC_CNTL_SLOWMEM_FOLW_CPU (BIT(9)) +/*description: 1: RTC memory PD following CPU*/ +#define RTC_CNTL_SLOWMEM_FOLW_CPU (BIT(9)) #define RTC_CNTL_SLOWMEM_FOLW_CPU_M (BIT(9)) #define RTC_CNTL_SLOWMEM_FOLW_CPU_V 0x1 #define RTC_CNTL_SLOWMEM_FOLW_CPU_S 9 /* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: Fast RTC memory force no PD.*/ -#define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(8)) +/*description: Fast RTC memory force no PD*/ +#define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(8)) #define RTC_CNTL_FASTMEM_FORCE_LPU_M (BIT(8)) #define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x1 #define RTC_CNTL_FASTMEM_FORCE_LPU_S 8 /* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Fast RTC memory force PD.*/ -#define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(7)) +/*description: Fast RTC memory force PD*/ +#define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(7)) #define RTC_CNTL_FASTMEM_FORCE_LPD_M (BIT(7)) #define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x1 #define RTC_CNTL_FASTMEM_FORCE_LPD_S 7 /* RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: 1: Fast RTC memory PD following CPU.*/ -#define RTC_CNTL_FASTMEM_FOLW_CPU (BIT(6)) +/*description: 1: Fast RTC memory PD following CPU*/ +#define RTC_CNTL_FASTMEM_FOLW_CPU (BIT(6)) #define RTC_CNTL_FASTMEM_FOLW_CPU_M (BIT(6)) #define RTC_CNTL_FASTMEM_FOLW_CPU_V 0x1 #define RTC_CNTL_FASTMEM_FOLW_CPU_S 6 /* RTC_CNTL_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'd1 ; */ -/*description: rtc_peri force no ISO.*/ -#define RTC_CNTL_FORCE_NOISO (BIT(5)) +/*description: rtc_peri force no ISO*/ +#define RTC_CNTL_FORCE_NOISO (BIT(5)) #define RTC_CNTL_FORCE_NOISO_M (BIT(5)) #define RTC_CNTL_FORCE_NOISO_V 0x1 #define RTC_CNTL_FORCE_NOISO_S 5 /* RTC_CNTL_FORCE_ISO : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: rtc_peri force ISO.*/ -#define RTC_CNTL_FORCE_ISO (BIT(4)) +/*description: rtc_peri force ISO*/ +#define RTC_CNTL_FORCE_ISO (BIT(4)) #define RTC_CNTL_FORCE_ISO_M (BIT(4)) #define RTC_CNTL_FORCE_ISO_V 0x1 #define RTC_CNTL_FORCE_ISO_S 4 /* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: RTC memory force ISO.*/ -#define RTC_CNTL_SLOWMEM_FORCE_ISO (BIT(3)) +/*description: RTC memory force ISO*/ +#define RTC_CNTL_SLOWMEM_FORCE_ISO (BIT(3)) #define RTC_CNTL_SLOWMEM_FORCE_ISO_M (BIT(3)) #define RTC_CNTL_SLOWMEM_FORCE_ISO_V 0x1 #define RTC_CNTL_SLOWMEM_FORCE_ISO_S 3 /* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1 ; */ -/*description: RTC memory force no ISO.*/ -#define RTC_CNTL_SLOWMEM_FORCE_NOISO (BIT(2)) +/*description: RTC memory force no ISO*/ +#define RTC_CNTL_SLOWMEM_FORCE_NOISO (BIT(2)) #define RTC_CNTL_SLOWMEM_FORCE_NOISO_M (BIT(2)) #define RTC_CNTL_SLOWMEM_FORCE_NOISO_V 0x1 #define RTC_CNTL_SLOWMEM_FORCE_NOISO_S 2 /* RTC_CNTL_FASTMEM_FORCE_ISO : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Fast RTC memory force ISO.*/ -#define RTC_CNTL_FASTMEM_FORCE_ISO (BIT(1)) +/*description: Fast RTC memory force ISO*/ +#define RTC_CNTL_FASTMEM_FORCE_ISO (BIT(1)) #define RTC_CNTL_FASTMEM_FORCE_ISO_M (BIT(1)) #define RTC_CNTL_FASTMEM_FORCE_ISO_V 0x1 #define RTC_CNTL_FASTMEM_FORCE_ISO_S 1 /* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: Fast RTC memory force no ISO.*/ -#define RTC_CNTL_FASTMEM_FORCE_NOISO (BIT(0)) +/*description: Fast RTC memory force no ISO*/ +#define RTC_CNTL_FASTMEM_FORCE_NOISO (BIT(0)) #define RTC_CNTL_FASTMEM_FORCE_NOISO_M (BIT(0)) #define RTC_CNTL_FASTMEM_FORCE_NOISO_V 0x1 #define RTC_CNTL_FASTMEM_FORCE_NOISO_S 0 -#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x8C) +#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x008C) /* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0 ; */ -/*description: .*/ -#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) +/*description: */ +#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) #define RTC_CNTL_DG_WRAP_PD_EN_M (BIT(31)) #define RTC_CNTL_DG_WRAP_PD_EN_V 0x1 #define RTC_CNTL_DG_WRAP_PD_EN_S 31 /* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 0 ; */ -/*description: enable power down wifi in sleep.*/ -#define RTC_CNTL_WIFI_PD_EN (BIT(30)) +/*description: enable power down wifi in sleep*/ +#define RTC_CNTL_WIFI_PD_EN (BIT(30)) #define RTC_CNTL_WIFI_PD_EN_M (BIT(30)) #define RTC_CNTL_WIFI_PD_EN_V 0x1 #define RTC_CNTL_WIFI_PD_EN_S 30 -/* RTC_CNTL_INTER_RAM4_PD_EN : R/W ;bitpos:[29] ;default: 0 ; */ -/*description: enable power down internal SRAM 4 in sleep.*/ -#define RTC_CNTL_INTER_RAM4_PD_EN (BIT(29)) -#define RTC_CNTL_INTER_RAM4_PD_EN_M (BIT(29)) -#define RTC_CNTL_INTER_RAM4_PD_EN_V 0x1 -#define RTC_CNTL_INTER_RAM4_PD_EN_S 29 -/* RTC_CNTL_INTER_RAM3_PD_EN : R/W ;bitpos:[28] ;default: 0 ; */ -/*description: enable power down internal SRAM 3 in sleep.*/ -#define RTC_CNTL_INTER_RAM3_PD_EN (BIT(28)) -#define RTC_CNTL_INTER_RAM3_PD_EN_M (BIT(28)) -#define RTC_CNTL_INTER_RAM3_PD_EN_V 0x1 -#define RTC_CNTL_INTER_RAM3_PD_EN_S 28 -/* RTC_CNTL_INTER_RAM2_PD_EN : R/W ;bitpos:[27] ;default: 0 ; */ -/*description: enable power down internal SRAM 2 in sleep.*/ -#define RTC_CNTL_INTER_RAM2_PD_EN (BIT(27)) -#define RTC_CNTL_INTER_RAM2_PD_EN_M (BIT(27)) -#define RTC_CNTL_INTER_RAM2_PD_EN_V 0x1 -#define RTC_CNTL_INTER_RAM2_PD_EN_S 27 -/* RTC_CNTL_INTER_RAM1_PD_EN : R/W ;bitpos:[26] ;default: 0 ; */ -/*description: enable power down internal SRAM 1 in sleep.*/ -#define RTC_CNTL_INTER_RAM1_PD_EN (BIT(26)) -#define RTC_CNTL_INTER_RAM1_PD_EN_M (BIT(26)) -#define RTC_CNTL_INTER_RAM1_PD_EN_V 0x1 -#define RTC_CNTL_INTER_RAM1_PD_EN_S 26 -/* RTC_CNTL_INTER_RAM0_PD_EN : R/W ;bitpos:[25] ;default: 0 ; */ -/*description: enable power down internal SRAM 0 in sleep.*/ -#define RTC_CNTL_INTER_RAM0_PD_EN (BIT(25)) -#define RTC_CNTL_INTER_RAM0_PD_EN_M (BIT(25)) -#define RTC_CNTL_INTER_RAM0_PD_EN_V 0x1 -#define RTC_CNTL_INTER_RAM0_PD_EN_S 25 -/* RTC_CNTL_ROM0_PD_EN : R/W ;bitpos:[24] ;default: 0 ; */ -/*description: enable power down ROM in sleep.*/ -#define RTC_CNTL_ROM0_PD_EN (BIT(24)) -#define RTC_CNTL_ROM0_PD_EN_M (BIT(24)) -#define RTC_CNTL_ROM0_PD_EN_V 0x1 -#define RTC_CNTL_ROM0_PD_EN_S 24 -/* RTC_CNTL_DG_DCDC_PD_EN : R/W ;bitpos:[23] ;default: 0 ; */ -/*description: enable power down digital dcdc in sleep.*/ -#define RTC_CNTL_DG_DCDC_PD_EN (BIT(23)) -#define RTC_CNTL_DG_DCDC_PD_EN_M (BIT(23)) -#define RTC_CNTL_DG_DCDC_PD_EN_V 0x1 -#define RTC_CNTL_DG_DCDC_PD_EN_S 23 -/* RTC_CNTL_DG_DCDC_FORCE_PU : R/W ;bitpos:[22] ;default: 1'd1 ; */ -/*description: digital dcdc force power up.*/ -#define RTC_CNTL_DG_DCDC_FORCE_PU (BIT(22)) -#define RTC_CNTL_DG_DCDC_FORCE_PU_M (BIT(22)) -#define RTC_CNTL_DG_DCDC_FORCE_PU_V 0x1 -#define RTC_CNTL_DG_DCDC_FORCE_PU_S 22 -/* RTC_CNTL_DG_DCDC_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: digital dcdc force power down.*/ -#define RTC_CNTL_DG_DCDC_FORCE_PD (BIT(21)) -#define RTC_CNTL_DG_DCDC_FORCE_PD_M (BIT(21)) -#define RTC_CNTL_DG_DCDC_FORCE_PD_V 0x1 -#define RTC_CNTL_DG_DCDC_FORCE_PD_S 21 +/* RTC_CNTL_CPU_TOP_PD_EN : R/W ;bitpos:[29] ;default: 0 ; */ +/*description: enable power down internal SRAM 4 in sleep*/ +#define RTC_CNTL_CPU_TOP_PD_EN (BIT(29)) +#define RTC_CNTL_CPU_TOP_PD_EN_M (BIT(29)) +#define RTC_CNTL_CPU_TOP_PD_EN_V 0x1 +#define RTC_CNTL_CPU_TOP_PD_EN_S 29 +/* RTC_CNTL_DG_PERI_PD_EN : R/W ;bitpos:[28] ;default: 0 ; */ +/*description: enable power down internal SRAM 3 in sleep*/ +#define RTC_CNTL_DG_PERI_PD_EN (BIT(28)) +#define RTC_CNTL_DG_PERI_PD_EN_M (BIT(28)) +#define RTC_CNTL_DG_PERI_PD_EN_V 0x1 +#define RTC_CNTL_DG_PERI_PD_EN_S 28 +/* RTC_CNTL_BT_PD_EN : R/W ;bitpos:[27] ;default: 0 ; */ +/*description: enable power down internal SRAM 2 in sleep*/ +#define RTC_CNTL_BT_PD_EN (BIT(27)) +#define RTC_CNTL_BT_PD_EN_M (BIT(27)) +#define RTC_CNTL_BT_PD_EN_V 0x1 +#define RTC_CNTL_BT_PD_EN_S 27 +/* RTC_CNTL_CPU_TOP_FORCE_PU : R/W ;bitpos:[22] ;default: 1'd1 ; */ +/*description: digital dcdc force power up*/ +#define RTC_CNTL_CPU_TOP_FORCE_PU (BIT(22)) +#define RTC_CNTL_CPU_TOP_FORCE_PU_M (BIT(22)) +#define RTC_CNTL_CPU_TOP_FORCE_PU_V 0x1 +#define RTC_CNTL_CPU_TOP_FORCE_PU_S 22 +/* RTC_CNTL_CPU_TOP_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: digital dcdc force power down*/ +#define RTC_CNTL_CPU_TOP_FORCE_PD (BIT(21)) +#define RTC_CNTL_CPU_TOP_FORCE_PD_M (BIT(21)) +#define RTC_CNTL_CPU_TOP_FORCE_PD_V 0x1 +#define RTC_CNTL_CPU_TOP_FORCE_PD_S 21 /* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */ -/*description: digital core force power up.*/ -#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) +/*description: digital core force power up*/ +#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) #define RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(20)) #define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1 #define RTC_CNTL_DG_WRAP_FORCE_PU_S 20 /* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: digital core force power down.*/ -#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) +/*description: digital core force power down*/ +#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) #define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(19)) #define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1 #define RTC_CNTL_DG_WRAP_FORCE_PD_S 19 /* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */ -/*description: wifi force power up.*/ -#define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) +/*description: wifi force power up*/ +#define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) #define RTC_CNTL_WIFI_FORCE_PU_M (BIT(18)) #define RTC_CNTL_WIFI_FORCE_PU_V 0x1 #define RTC_CNTL_WIFI_FORCE_PU_S 18 /* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: wifi force power down.*/ -#define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) +/*description: wifi force power down*/ +#define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) #define RTC_CNTL_WIFI_FORCE_PD_M (BIT(17)) #define RTC_CNTL_WIFI_FORCE_PD_V 0x1 #define RTC_CNTL_WIFI_FORCE_PD_S 17 -/* RTC_CNTL_INTER_RAM4_FORCE_PU : R/W ;bitpos:[16] ;default: 1'd1 ; */ -/*description: internal SRAM 4 force power up.*/ -#define RTC_CNTL_INTER_RAM4_FORCE_PU (BIT(16)) -#define RTC_CNTL_INTER_RAM4_FORCE_PU_M (BIT(16)) -#define RTC_CNTL_INTER_RAM4_FORCE_PU_V 0x1 -#define RTC_CNTL_INTER_RAM4_FORCE_PU_S 16 -/* RTC_CNTL_INTER_RAM4_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: internal SRAM 4 force power down.*/ -#define RTC_CNTL_INTER_RAM4_FORCE_PD (BIT(15)) -#define RTC_CNTL_INTER_RAM4_FORCE_PD_M (BIT(15)) -#define RTC_CNTL_INTER_RAM4_FORCE_PD_V 0x1 -#define RTC_CNTL_INTER_RAM4_FORCE_PD_S 15 -/* RTC_CNTL_INTER_RAM3_FORCE_PU : R/W ;bitpos:[14] ;default: 1'd1 ; */ -/*description: internal SRAM 3 force power up.*/ -#define RTC_CNTL_INTER_RAM3_FORCE_PU (BIT(14)) -#define RTC_CNTL_INTER_RAM3_FORCE_PU_M (BIT(14)) -#define RTC_CNTL_INTER_RAM3_FORCE_PU_V 0x1 -#define RTC_CNTL_INTER_RAM3_FORCE_PU_S 14 -/* RTC_CNTL_INTER_RAM3_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: internal SRAM 3 force power down.*/ -#define RTC_CNTL_INTER_RAM3_FORCE_PD (BIT(13)) -#define RTC_CNTL_INTER_RAM3_FORCE_PD_M (BIT(13)) -#define RTC_CNTL_INTER_RAM3_FORCE_PD_V 0x1 -#define RTC_CNTL_INTER_RAM3_FORCE_PD_S 13 -/* RTC_CNTL_INTER_RAM2_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */ -/*description: internal SRAM 2 force power up.*/ -#define RTC_CNTL_INTER_RAM2_FORCE_PU (BIT(12)) -#define RTC_CNTL_INTER_RAM2_FORCE_PU_M (BIT(12)) -#define RTC_CNTL_INTER_RAM2_FORCE_PU_V 0x1 -#define RTC_CNTL_INTER_RAM2_FORCE_PU_S 12 -/* RTC_CNTL_INTER_RAM2_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: internal SRAM 2 force power down.*/ -#define RTC_CNTL_INTER_RAM2_FORCE_PD (BIT(11)) -#define RTC_CNTL_INTER_RAM2_FORCE_PD_M (BIT(11)) -#define RTC_CNTL_INTER_RAM2_FORCE_PD_V 0x1 -#define RTC_CNTL_INTER_RAM2_FORCE_PD_S 11 -/* RTC_CNTL_INTER_RAM1_FORCE_PU : R/W ;bitpos:[10] ;default: 1'd1 ; */ -/*description: internal SRAM 1 force power up.*/ -#define RTC_CNTL_INTER_RAM1_FORCE_PU (BIT(10)) -#define RTC_CNTL_INTER_RAM1_FORCE_PU_M (BIT(10)) -#define RTC_CNTL_INTER_RAM1_FORCE_PU_V 0x1 -#define RTC_CNTL_INTER_RAM1_FORCE_PU_S 10 -/* RTC_CNTL_INTER_RAM1_FORCE_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: internal SRAM 1 force power down.*/ -#define RTC_CNTL_INTER_RAM1_FORCE_PD (BIT(9)) -#define RTC_CNTL_INTER_RAM1_FORCE_PD_M (BIT(9)) -#define RTC_CNTL_INTER_RAM1_FORCE_PD_V 0x1 -#define RTC_CNTL_INTER_RAM1_FORCE_PD_S 9 -/* RTC_CNTL_INTER_RAM0_FORCE_PU : R/W ;bitpos:[8] ;default: 1'd1 ; */ -/*description: internal SRAM 0 force power up.*/ -#define RTC_CNTL_INTER_RAM0_FORCE_PU (BIT(8)) -#define RTC_CNTL_INTER_RAM0_FORCE_PU_M (BIT(8)) -#define RTC_CNTL_INTER_RAM0_FORCE_PU_V 0x1 -#define RTC_CNTL_INTER_RAM0_FORCE_PU_S 8 -/* RTC_CNTL_INTER_RAM0_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: internal SRAM 0 force power down.*/ -#define RTC_CNTL_INTER_RAM0_FORCE_PD (BIT(7)) -#define RTC_CNTL_INTER_RAM0_FORCE_PD_M (BIT(7)) -#define RTC_CNTL_INTER_RAM0_FORCE_PD_V 0x1 -#define RTC_CNTL_INTER_RAM0_FORCE_PD_S 7 -/* RTC_CNTL_ROM0_FORCE_PU : R/W ;bitpos:[6] ;default: 1'd1 ; */ -/*description: ROM force power up.*/ -#define RTC_CNTL_ROM0_FORCE_PU (BIT(6)) -#define RTC_CNTL_ROM0_FORCE_PU_M (BIT(6)) -#define RTC_CNTL_ROM0_FORCE_PU_V 0x1 -#define RTC_CNTL_ROM0_FORCE_PU_S 6 -/* RTC_CNTL_ROM0_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: ROM force power down.*/ -#define RTC_CNTL_ROM0_FORCE_PD (BIT(5)) -#define RTC_CNTL_ROM0_FORCE_PD_M (BIT(5)) -#define RTC_CNTL_ROM0_FORCE_PD_V 0x1 -#define RTC_CNTL_ROM0_FORCE_PD_S 5 +/* RTC_CNTL_DG_PERI_FORCE_PU : R/W ;bitpos:[14] ;default: 1'd1 ; */ +/*description: internal SRAM 3 force power up*/ +#define RTC_CNTL_DG_PERI_FORCE_PU (BIT(14)) +#define RTC_CNTL_DG_PERI_FORCE_PU_M (BIT(14)) +#define RTC_CNTL_DG_PERI_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_PERI_FORCE_PU_S 14 +/* RTC_CNTL_DG_PERI_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: internal SRAM 3 force power down*/ +#define RTC_CNTL_DG_PERI_FORCE_PD (BIT(13)) +#define RTC_CNTL_DG_PERI_FORCE_PD_M (BIT(13)) +#define RTC_CNTL_DG_PERI_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_PERI_FORCE_PD_S 13 +/* RTC_CNTL_BT_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: internal SRAM 2 force power up*/ +#define RTC_CNTL_BT_FORCE_PU (BIT(12)) +#define RTC_CNTL_BT_FORCE_PU_M (BIT(12)) +#define RTC_CNTL_BT_FORCE_PU_V 0x1 +#define RTC_CNTL_BT_FORCE_PU_S 12 +/* RTC_CNTL_BT_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: internal SRAM 2 force power down*/ +#define RTC_CNTL_BT_FORCE_PD (BIT(11)) +#define RTC_CNTL_BT_FORCE_PD_M (BIT(11)) +#define RTC_CNTL_BT_FORCE_PD_V 0x1 +#define RTC_CNTL_BT_FORCE_PD_S 11 /* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ -/*description: memories in digital core force no PD in sleep.*/ -#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) +/*description: memories in digital core force no PD in sleep*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) #define RTC_CNTL_LSLP_MEM_FORCE_PU_M (BIT(4)) #define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x1 #define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 /* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: memories in digital core force PD in sleep.*/ -#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) +/*description: memories in digital core force PD in sleep*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) #define RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(3)) #define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1 #define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 -#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x90) +#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x0090) /* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */ -/*description: .*/ -#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) +/*description: */ +#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) #define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (BIT(31)) #define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x1 #define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 /* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: digital core force ISO.*/ -#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) +/*description: digital core force ISO*/ +#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) #define RTC_CNTL_DG_WRAP_FORCE_ISO_M (BIT(30)) #define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x1 #define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 /* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */ -/*description: wifi force no ISO.*/ -#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) +/*description: wifi force no ISO*/ +#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) #define RTC_CNTL_WIFI_FORCE_NOISO_M (BIT(29)) #define RTC_CNTL_WIFI_FORCE_NOISO_V 0x1 #define RTC_CNTL_WIFI_FORCE_NOISO_S 29 /* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: wifi force ISO.*/ -#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) +/*description: wifi force ISO*/ +#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) #define RTC_CNTL_WIFI_FORCE_ISO_M (BIT(28)) #define RTC_CNTL_WIFI_FORCE_ISO_V 0x1 #define RTC_CNTL_WIFI_FORCE_ISO_S 28 -/* RTC_CNTL_INTER_RAM4_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ -/*description: internal SRAM 4 force no ISO.*/ -#define RTC_CNTL_INTER_RAM4_FORCE_NOISO (BIT(27)) -#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_M (BIT(27)) -#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_V 0x1 -#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_S 27 -/* RTC_CNTL_INTER_RAM4_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */ -/*description: internal SRAM 4 force ISO.*/ -#define RTC_CNTL_INTER_RAM4_FORCE_ISO (BIT(26)) -#define RTC_CNTL_INTER_RAM4_FORCE_ISO_M (BIT(26)) -#define RTC_CNTL_INTER_RAM4_FORCE_ISO_V 0x1 -#define RTC_CNTL_INTER_RAM4_FORCE_ISO_S 26 -/* RTC_CNTL_INTER_RAM3_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */ -/*description: internal SRAM 3 force no ISO.*/ -#define RTC_CNTL_INTER_RAM3_FORCE_NOISO (BIT(25)) -#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_M (BIT(25)) -#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_V 0x1 -#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_S 25 -/* RTC_CNTL_INTER_RAM3_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ -/*description: internal SRAM 3 force ISO.*/ -#define RTC_CNTL_INTER_RAM3_FORCE_ISO (BIT(24)) -#define RTC_CNTL_INTER_RAM3_FORCE_ISO_M (BIT(24)) -#define RTC_CNTL_INTER_RAM3_FORCE_ISO_V 0x1 -#define RTC_CNTL_INTER_RAM3_FORCE_ISO_S 24 -/* RTC_CNTL_INTER_RAM2_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */ -/*description: internal SRAM 2 force no ISO.*/ -#define RTC_CNTL_INTER_RAM2_FORCE_NOISO (BIT(23)) -#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_M (BIT(23)) -#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_V 0x1 -#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_S 23 -/* RTC_CNTL_INTER_RAM2_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */ -/*description: internal SRAM 2 force ISO.*/ -#define RTC_CNTL_INTER_RAM2_FORCE_ISO (BIT(22)) -#define RTC_CNTL_INTER_RAM2_FORCE_ISO_M (BIT(22)) -#define RTC_CNTL_INTER_RAM2_FORCE_ISO_V 0x1 -#define RTC_CNTL_INTER_RAM2_FORCE_ISO_S 22 -/* RTC_CNTL_INTER_RAM1_FORCE_NOISO : R/W ;bitpos:[21] ;default: 1'd1 ; */ -/*description: internal SRAM 1 force no ISO.*/ -#define RTC_CNTL_INTER_RAM1_FORCE_NOISO (BIT(21)) -#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_M (BIT(21)) -#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_V 0x1 -#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_S 21 -/* RTC_CNTL_INTER_RAM1_FORCE_ISO : R/W ;bitpos:[20] ;default: 1'd0 ; */ -/*description: internal SRAM 1 force ISO.*/ -#define RTC_CNTL_INTER_RAM1_FORCE_ISO (BIT(20)) -#define RTC_CNTL_INTER_RAM1_FORCE_ISO_M (BIT(20)) -#define RTC_CNTL_INTER_RAM1_FORCE_ISO_V 0x1 -#define RTC_CNTL_INTER_RAM1_FORCE_ISO_S 20 -/* RTC_CNTL_INTER_RAM0_FORCE_NOISO : R/W ;bitpos:[19] ;default: 1'd1 ; */ -/*description: internal SRAM 0 force no ISO.*/ -#define RTC_CNTL_INTER_RAM0_FORCE_NOISO (BIT(19)) -#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_M (BIT(19)) -#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_V 0x1 -#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_S 19 -/* RTC_CNTL_INTER_RAM0_FORCE_ISO : R/W ;bitpos:[18] ;default: 1'd0 ; */ -/*description: internal SRAM 0 force ISO.*/ -#define RTC_CNTL_INTER_RAM0_FORCE_ISO (BIT(18)) -#define RTC_CNTL_INTER_RAM0_FORCE_ISO_M (BIT(18)) -#define RTC_CNTL_INTER_RAM0_FORCE_ISO_V 0x1 -#define RTC_CNTL_INTER_RAM0_FORCE_ISO_S 18 -/* RTC_CNTL_ROM0_FORCE_NOISO : R/W ;bitpos:[17] ;default: 1'd1 ; */ -/*description: ROM force no ISO.*/ -#define RTC_CNTL_ROM0_FORCE_NOISO (BIT(17)) -#define RTC_CNTL_ROM0_FORCE_NOISO_M (BIT(17)) -#define RTC_CNTL_ROM0_FORCE_NOISO_V 0x1 -#define RTC_CNTL_ROM0_FORCE_NOISO_S 17 -/* RTC_CNTL_ROM0_FORCE_ISO : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: ROM force ISO.*/ -#define RTC_CNTL_ROM0_FORCE_ISO (BIT(16)) -#define RTC_CNTL_ROM0_FORCE_ISO_M (BIT(16)) -#define RTC_CNTL_ROM0_FORCE_ISO_V 0x1 -#define RTC_CNTL_ROM0_FORCE_ISO_S 16 +/* RTC_CNTL_CPU_TOP_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: internal SRAM 4 force no ISO*/ +#define RTC_CNTL_CPU_TOP_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_CPU_TOP_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_CPU_TOP_FORCE_NOISO_V 0x1 +#define RTC_CNTL_CPU_TOP_FORCE_NOISO_S 27 +/* RTC_CNTL_CPU_TOP_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: internal SRAM 4 force ISO*/ +#define RTC_CNTL_CPU_TOP_FORCE_ISO (BIT(26)) +#define RTC_CNTL_CPU_TOP_FORCE_ISO_M (BIT(26)) +#define RTC_CNTL_CPU_TOP_FORCE_ISO_V 0x1 +#define RTC_CNTL_CPU_TOP_FORCE_ISO_S 26 +/* RTC_CNTL_DG_PERI_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */ +/*description: internal SRAM 3 force no ISO*/ +#define RTC_CNTL_DG_PERI_FORCE_NOISO (BIT(25)) +#define RTC_CNTL_DG_PERI_FORCE_NOISO_M (BIT(25)) +#define RTC_CNTL_DG_PERI_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_PERI_FORCE_NOISO_S 25 +/* RTC_CNTL_DG_PERI_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: internal SRAM 3 force ISO*/ +#define RTC_CNTL_DG_PERI_FORCE_ISO (BIT(24)) +#define RTC_CNTL_DG_PERI_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_DG_PERI_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_PERI_FORCE_ISO_S 24 +/* RTC_CNTL_BT_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */ +/*description: internal SRAM 2 force no ISO*/ +#define RTC_CNTL_BT_FORCE_NOISO (BIT(23)) +#define RTC_CNTL_BT_FORCE_NOISO_M (BIT(23)) +#define RTC_CNTL_BT_FORCE_NOISO_V 0x1 +#define RTC_CNTL_BT_FORCE_NOISO_S 23 +/* RTC_CNTL_BT_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: internal SRAM 2 force ISO*/ +#define RTC_CNTL_BT_FORCE_ISO (BIT(22)) +#define RTC_CNTL_BT_FORCE_ISO_M (BIT(22)) +#define RTC_CNTL_BT_FORCE_ISO_V 0x1 +#define RTC_CNTL_BT_FORCE_ISO_S 22 /* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: digital pad force hold.*/ -#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) +/*description: digital pad force hold*/ +#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) #define RTC_CNTL_DG_PAD_FORCE_HOLD_M (BIT(15)) #define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x1 #define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 /* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */ -/*description: digital pad force un-hold.*/ -#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) +/*description: digital pad force un-hold*/ +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (BIT(14)) #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x1 #define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 /* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: digital pad force ISO.*/ -#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) +/*description: digital pad force ISO*/ +#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) #define RTC_CNTL_DG_PAD_FORCE_ISO_M (BIT(13)) #define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x1 #define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 /* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */ -/*description: digital pad force no ISO.*/ -#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) +/*description: digital pad force no ISO*/ +#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) #define RTC_CNTL_DG_PAD_FORCE_NOISO_M (BIT(12)) #define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x1 #define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 /* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: digital pad enable auto-hold.*/ -#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) +/*description: digital pad enable auto-hold*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (BIT(11)) #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x1 #define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 /* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */ -/*description: wtite only register to clear digital pad auto-hold.*/ -#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) +/*description: wtite only register to clear digital pad auto-hold*/ +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (BIT(10)) #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x1 #define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 /* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */ -/*description: read only register to indicate digital pad auto-hold status.*/ -#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) +/*description: read only register to indicate digital pad auto-hold status*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) #define RTC_CNTL_DG_PAD_AUTOHOLD_M (BIT(9)) #define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x1 #define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 /* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: .*/ -#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) +/*description: */ +#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) #define RTC_CNTL_DIG_ISO_FORCE_ON_M (BIT(8)) #define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x1 #define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 /* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd1 ; */ -/*description: .*/ -#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) +/*description: */ +#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) #define RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7)) #define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 #define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 -#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x94) +#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x0094) /* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: .*/ -#define RTC_CNTL_WDT_EN (BIT(31)) +/*description: */ +#define RTC_CNTL_WDT_EN (BIT(31)) #define RTC_CNTL_WDT_EN_M (BIT(31)) #define RTC_CNTL_WDT_EN_V 0x1 #define RTC_CNTL_WDT_EN_S 31 /* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ -/*description: 1: interrupt stage en.*/ -#define RTC_CNTL_WDT_STG0 0x00000007 +/*description: 1: interrupt stage en*/ +#define RTC_CNTL_WDT_STG0 0x00000007 #define RTC_CNTL_WDT_STG0_M ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S)) #define RTC_CNTL_WDT_STG0_V 0x7 #define RTC_CNTL_WDT_STG0_S 28 /* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ -/*description: 1: interrupt stage en.*/ -#define RTC_CNTL_WDT_STG1 0x00000007 +/*description: 1: interrupt stage en*/ +#define RTC_CNTL_WDT_STG1 0x00000007 #define RTC_CNTL_WDT_STG1_M ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S)) #define RTC_CNTL_WDT_STG1_V 0x7 #define RTC_CNTL_WDT_STG1_S 25 /* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */ -/*description: 1: interrupt stage en.*/ -#define RTC_CNTL_WDT_STG2 0x00000007 +/*description: 1: interrupt stage en*/ +#define RTC_CNTL_WDT_STG2 0x00000007 #define RTC_CNTL_WDT_STG2_M ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S)) #define RTC_CNTL_WDT_STG2_V 0x7 #define RTC_CNTL_WDT_STG2_S 22 /* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */ -/*description: 1: interrupt stage en.*/ -#define RTC_CNTL_WDT_STG3 0x00000007 +/*description: 1: interrupt stage en*/ +#define RTC_CNTL_WDT_STG3 0x00000007 #define RTC_CNTL_WDT_STG3_M ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S)) #define RTC_CNTL_WDT_STG3_V 0x7 #define RTC_CNTL_WDT_STG3_S 19 - +/* RTC_CNTL_WDT_STGX : */ /*description: stage action selection values */ #define RTC_WDT_STG_SEL_OFF 0 #define RTC_WDT_STG_SEL_INT 1 @@ -2124,1492 +1999,1509 @@ ork.*/ #define RTC_WDT_STG_SEL_RESET_RTC 4 /* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[18:16] ;default: 3'h1 ; */ -/*description: CPU reset counter length.*/ -#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 +/*description: CPU reset counter length*/ +#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 #define RTC_CNTL_WDT_CPU_RESET_LENGTH_M ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S)) #define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x7 #define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 16 /* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[15:13] ;default: 3'h1 ; */ -/*description: system reset counter length.*/ -#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 +/*description: system reset counter length*/ +#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_M ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S)) #define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x7 #define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 13 /* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ -/*description: enable WDT in flash boot.*/ -#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(12)) +/*description: enable WDT in flash boot*/ +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(12)) #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (BIT(12)) #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x1 #define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 12 /* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: enable WDT reset PRO CPU.*/ -#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(11)) +/*description: enable WDT reset PRO CPU*/ +#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(11)) #define RTC_CNTL_WDT_PROCPU_RESET_EN_M (BIT(11)) #define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x1 #define RTC_CNTL_WDT_PROCPU_RESET_EN_S 11 /* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: enable WDT reset APP CPU.*/ -#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(10)) +/*description: enable WDT reset APP CPU*/ +#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(10)) #define RTC_CNTL_WDT_APPCPU_RESET_EN_M (BIT(10)) #define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x1 #define RTC_CNTL_WDT_APPCPU_RESET_EN_S 10 /* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[9] ;default: 1'd1 ; */ -/*description: pause WDT in sleep.*/ -#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(9)) +/*description: pause WDT in sleep*/ +#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(9)) #define RTC_CNTL_WDT_PAUSE_IN_SLP_M (BIT(9)) #define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x1 #define RTC_CNTL_WDT_PAUSE_IN_SLP_S 9 /* RTC_CNTL_WDT_CHIP_RESET_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: wdt reset whole chip enable.*/ -#define RTC_CNTL_WDT_CHIP_RESET_EN (BIT(8)) +/*description: wdt reset whole chip enable*/ +#define RTC_CNTL_WDT_CHIP_RESET_EN (BIT(8)) #define RTC_CNTL_WDT_CHIP_RESET_EN_M (BIT(8)) #define RTC_CNTL_WDT_CHIP_RESET_EN_V 0x1 #define RTC_CNTL_WDT_CHIP_RESET_EN_S 8 /* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W ;bitpos:[7:0] ;default: 8'd20 ; */ -/*description: chip reset siginal pulse width.*/ -#define RTC_CNTL_WDT_CHIP_RESET_WIDTH 0x000000FF +/*description: chip reset siginal pulse width*/ +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH 0x000000FF #define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M ((RTC_CNTL_WDT_CHIP_RESET_WIDTH_V)<<(RTC_CNTL_WDT_CHIP_RESET_WIDTH_S)) #define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V 0xFF #define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S 0 -#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x98) +#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x0098) /* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd200000 ; */ -/*description: .*/ -#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF +/*description: */ +#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF #define RTC_CNTL_WDT_STG0_HOLD_M ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S)) #define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF #define RTC_CNTL_WDT_STG0_HOLD_S 0 -#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x9C) +#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x009C) /* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */ -/*description: .*/ -#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF +/*description: */ +#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF #define RTC_CNTL_WDT_STG1_HOLD_M ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S)) #define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF #define RTC_CNTL_WDT_STG1_HOLD_S 0 -#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0xA0) +#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x00A0) /* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ -/*description: .*/ -#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF +/*description: */ +#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF #define RTC_CNTL_WDT_STG2_HOLD_M ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S)) #define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF #define RTC_CNTL_WDT_STG2_HOLD_S 0 -#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0xA4) +#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x00A4) /* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ -/*description: .*/ -#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF +/*description: */ +#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF #define RTC_CNTL_WDT_STG3_HOLD_M ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S)) #define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF #define RTC_CNTL_WDT_STG3_HOLD_S 0 -#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0xA8) +#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0x00A8) /* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */ -/*description: .*/ -#define RTC_CNTL_WDT_FEED (BIT(31)) +/*description: */ +#define RTC_CNTL_WDT_FEED (BIT(31)) #define RTC_CNTL_WDT_FEED_M (BIT(31)) #define RTC_CNTL_WDT_FEED_V 0x1 #define RTC_CNTL_WDT_FEED_S 31 -#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xAC) +#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00AC) /* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ -/*description: .*/ -#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF +/*description: */ +#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF #define RTC_CNTL_WDT_WKEY_M ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S)) #define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF #define RTC_CNTL_WDT_WKEY_S 0 -#define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0xB0) +#define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00B0) /* RTC_CNTL_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: automatically feed swd when int comes.*/ -#define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31)) +/*description: automatically feed swd when int comes*/ +#define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31)) #define RTC_CNTL_SWD_AUTO_FEED_EN_M (BIT(31)) #define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x1 #define RTC_CNTL_SWD_AUTO_FEED_EN_S 31 /* RTC_CNTL_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: disabel SWD.*/ -#define RTC_CNTL_SWD_DISABLE (BIT(30)) +/*description: disabel SWD*/ +#define RTC_CNTL_SWD_DISABLE (BIT(30)) #define RTC_CNTL_SWD_DISABLE_M (BIT(30)) #define RTC_CNTL_SWD_DISABLE_V 0x1 #define RTC_CNTL_SWD_DISABLE_S 30 /* RTC_CNTL_SWD_FEED : WO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Sw feed swd.*/ -#define RTC_CNTL_SWD_FEED (BIT(29)) +/*description: Sw feed swd*/ +#define RTC_CNTL_SWD_FEED (BIT(29)) #define RTC_CNTL_SWD_FEED_M (BIT(29)) #define RTC_CNTL_SWD_FEED_V 0x1 #define RTC_CNTL_SWD_FEED_S 29 /* RTC_CNTL_SWD_RST_FLAG_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: reset swd reset flag.*/ -#define RTC_CNTL_SWD_RST_FLAG_CLR (BIT(28)) +/*description: reset swd reset flag*/ +#define RTC_CNTL_SWD_RST_FLAG_CLR (BIT(28)) #define RTC_CNTL_SWD_RST_FLAG_CLR_M (BIT(28)) #define RTC_CNTL_SWD_RST_FLAG_CLR_V 0x1 #define RTC_CNTL_SWD_RST_FLAG_CLR_S 28 /* RTC_CNTL_SWD_SIGNAL_WIDTH : R/W ;bitpos:[27:18] ;default: 10'd300 ; */ -/*description: adjust signal width send to swd.*/ -#define RTC_CNTL_SWD_SIGNAL_WIDTH 0x000003FF +/*description: adjust signal width send to swd*/ +#define RTC_CNTL_SWD_SIGNAL_WIDTH 0x000003FF #define RTC_CNTL_SWD_SIGNAL_WIDTH_M ((RTC_CNTL_SWD_SIGNAL_WIDTH_V)<<(RTC_CNTL_SWD_SIGNAL_WIDTH_S)) #define RTC_CNTL_SWD_SIGNAL_WIDTH_V 0x3FF #define RTC_CNTL_SWD_SIGNAL_WIDTH_S 18 /* RTC_CNTL_SWD_BYPASS_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_SWD_BYPASS_RST (BIT(17)) +/*description: */ +#define RTC_CNTL_SWD_BYPASS_RST (BIT(17)) #define RTC_CNTL_SWD_BYPASS_RST_M (BIT(17)) #define RTC_CNTL_SWD_BYPASS_RST_V 0x1 #define RTC_CNTL_SWD_BYPASS_RST_S 17 /* RTC_CNTL_SWD_FEED_INT : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: swd interrupt for feeding.*/ -#define RTC_CNTL_SWD_FEED_INT (BIT(1)) +/*description: swd interrupt for feeding*/ +#define RTC_CNTL_SWD_FEED_INT (BIT(1)) #define RTC_CNTL_SWD_FEED_INT_M (BIT(1)) #define RTC_CNTL_SWD_FEED_INT_V 0x1 #define RTC_CNTL_SWD_FEED_INT_S 1 /* RTC_CNTL_SWD_RESET_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: swd reset flag.*/ -#define RTC_CNTL_SWD_RESET_FLAG (BIT(0)) +/*description: swd reset flag*/ +#define RTC_CNTL_SWD_RESET_FLAG (BIT(0)) #define RTC_CNTL_SWD_RESET_FLAG_M (BIT(0)) #define RTC_CNTL_SWD_RESET_FLAG_V 0x1 #define RTC_CNTL_SWD_RESET_FLAG_S 0 -#define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xB4) +#define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00B4) /* RTC_CNTL_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h8f1d312a ; */ -/*description: .*/ -#define RTC_CNTL_SWD_WKEY 0xFFFFFFFF +/*description: */ +#define RTC_CNTL_SWD_WKEY 0xFFFFFFFF #define RTC_CNTL_SWD_WKEY_M ((RTC_CNTL_SWD_WKEY_V)<<(RTC_CNTL_SWD_WKEY_S)) #define RTC_CNTL_SWD_WKEY_V 0xFFFFFFFF #define RTC_CNTL_SWD_WKEY_S 0 -#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0xB8) +#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0x00B8) /* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */ -/*description: .*/ -#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F +/*description: */ +#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F #define RTC_CNTL_SW_STALL_PROCPU_C1_M ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S)) #define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x3F #define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 /* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */ -/*description: {reg_sw_stall_appcpu_c1[5:0].*/ -#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F +/*description: {reg_sw_stall_appcpu_c1[5:0]*/ +#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F #define RTC_CNTL_SW_STALL_APPCPU_C1_M ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S)) #define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F #define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 -#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xBC) +#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0x00BC) /* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: .*/ -#define RTC_CNTL_SCRATCH4 0xFFFFFFFF +/*description: */ +#define RTC_CNTL_SCRATCH4 0xFFFFFFFF #define RTC_CNTL_SCRATCH4_M ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S)) #define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF #define RTC_CNTL_SCRATCH4_S 0 -#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xC0) +#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0x00C0) /* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: .*/ -#define RTC_CNTL_SCRATCH5 0xFFFFFFFF +/*description: */ +#define RTC_CNTL_SCRATCH5 0xFFFFFFFF #define RTC_CNTL_SCRATCH5_M ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S)) #define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF #define RTC_CNTL_SCRATCH5_S 0 -#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0xC4) +#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0x00C4) /* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: .*/ -#define RTC_CNTL_SCRATCH6 0xFFFFFFFF +/*description: */ +#define RTC_CNTL_SCRATCH6 0xFFFFFFFF #define RTC_CNTL_SCRATCH6_M ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S)) #define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF #define RTC_CNTL_SCRATCH6_S 0 -#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0xC8) +#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0x00C8) /* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */ -/*description: .*/ -#define RTC_CNTL_SCRATCH7 0xFFFFFFFF +/*description: */ +#define RTC_CNTL_SCRATCH7 0xFFFFFFFF #define RTC_CNTL_SCRATCH7_M ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S)) #define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF #define RTC_CNTL_SCRATCH7_S 0 -#define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0xCC) +#define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0x00CC) /* RTC_CNTL_MAIN_STATE : RO ;bitpos:[31:28] ;default: 4'd0 ; */ -/*description: rtc main state machine status.*/ -#define RTC_CNTL_MAIN_STATE 0x0000000F +/*description: rtc main state machine status*/ +#define RTC_CNTL_MAIN_STATE 0x0000000F #define RTC_CNTL_MAIN_STATE_M ((RTC_CNTL_MAIN_STATE_V)<<(RTC_CNTL_MAIN_STATE_S)) #define RTC_CNTL_MAIN_STATE_V 0xF #define RTC_CNTL_MAIN_STATE_S 28 /* RTC_CNTL_MAIN_STATE_IN_IDLE : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: rtc main state machine is in idle state.*/ -#define RTC_CNTL_MAIN_STATE_IN_IDLE (BIT(27)) +/*description: rtc main state machine is in idle state*/ +#define RTC_CNTL_MAIN_STATE_IN_IDLE (BIT(27)) #define RTC_CNTL_MAIN_STATE_IN_IDLE_M (BIT(27)) #define RTC_CNTL_MAIN_STATE_IN_IDLE_V 0x1 #define RTC_CNTL_MAIN_STATE_IN_IDLE_S 27 /* RTC_CNTL_MAIN_STATE_IN_SLP : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: rtc main state machine is in sleep state.*/ -#define RTC_CNTL_MAIN_STATE_IN_SLP (BIT(26)) +/*description: rtc main state machine is in sleep state*/ +#define RTC_CNTL_MAIN_STATE_IN_SLP (BIT(26)) #define RTC_CNTL_MAIN_STATE_IN_SLP_M (BIT(26)) #define RTC_CNTL_MAIN_STATE_IN_SLP_V 0x1 #define RTC_CNTL_MAIN_STATE_IN_SLP_S 26 /* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: rtc main state machine is in wait xtal state.*/ -#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL (BIT(25)) +/*description: rtc main state machine is in wait xtal state*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL (BIT(25)) #define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M (BIT(25)) #define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V 0x1 #define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S 25 /* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: rtc main state machine is in wait pll state.*/ -#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL (BIT(24)) +/*description: rtc main state machine is in wait pll state*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL (BIT(24)) #define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M (BIT(24)) #define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V 0x1 #define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S 24 /* RTC_CNTL_MAIN_STATE_IN_WAIT_8M : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: rtc main state machine is in wait 8m state.*/ -#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M (BIT(23)) +/*description: rtc main state machine is in wait 8m state*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M (BIT(23)) #define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M (BIT(23)) #define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V 0x1 #define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S 23 /* RTC_CNTL_IN_LOW_POWER_STATE : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: rtc main state machine is in the states of low power.*/ -#define RTC_CNTL_IN_LOW_POWER_STATE (BIT(22)) +/*description: rtc main state machine is in the states of low power*/ +#define RTC_CNTL_IN_LOW_POWER_STATE (BIT(22)) #define RTC_CNTL_IN_LOW_POWER_STATE_M (BIT(22)) #define RTC_CNTL_IN_LOW_POWER_STATE_V 0x1 #define RTC_CNTL_IN_LOW_POWER_STATE_S 22 /* RTC_CNTL_IN_WAKEUP_STATE : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: rtc main state machine is in the states of wakeup process.*/ -#define RTC_CNTL_IN_WAKEUP_STATE (BIT(21)) +/*description: rtc main state machine is in the states of wakeup process*/ +#define RTC_CNTL_IN_WAKEUP_STATE (BIT(21)) #define RTC_CNTL_IN_WAKEUP_STATE_M (BIT(21)) #define RTC_CNTL_IN_WAKEUP_STATE_V 0x1 #define RTC_CNTL_IN_WAKEUP_STATE_S 21 /* RTC_CNTL_MAIN_STATE_WAIT_END : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: rtc main state machine has been waited for some cycles.*/ -#define RTC_CNTL_MAIN_STATE_WAIT_END (BIT(20)) +/*description: rtc main state machine has been waited for some cycles*/ +#define RTC_CNTL_MAIN_STATE_WAIT_END (BIT(20)) #define RTC_CNTL_MAIN_STATE_WAIT_END_M (BIT(20)) #define RTC_CNTL_MAIN_STATE_WAIT_END_V 0x1 #define RTC_CNTL_MAIN_STATE_WAIT_END_S 20 /* RTC_CNTL_RDY_FOR_WAKEUP : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: rtc is ready to receive wake up trigger from wake up source.*/ -#define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19)) +/*description: rtc is ready to receive wake up trigger from wake up source*/ +#define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19)) #define RTC_CNTL_RDY_FOR_WAKEUP_M (BIT(19)) #define RTC_CNTL_RDY_FOR_WAKEUP_V 0x1 #define RTC_CNTL_RDY_FOR_WAKEUP_S 19 /* RTC_CNTL_MAIN_STATE_PLL_ON : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: rtc main state machine is in states that pll should be running.*/ -#define RTC_CNTL_MAIN_STATE_PLL_ON (BIT(18)) +/*description: rtc main state machine is in states that pll should be running*/ +#define RTC_CNTL_MAIN_STATE_PLL_ON (BIT(18)) #define RTC_CNTL_MAIN_STATE_PLL_ON_M (BIT(18)) #define RTC_CNTL_MAIN_STATE_PLL_ON_V 0x1 #define RTC_CNTL_MAIN_STATE_PLL_ON_S 18 /* RTC_CNTL_MAIN_STATE_XTAL_ISO : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: no use any more.*/ -#define RTC_CNTL_MAIN_STATE_XTAL_ISO (BIT(17)) +/*description: no use any more*/ +#define RTC_CNTL_MAIN_STATE_XTAL_ISO (BIT(17)) #define RTC_CNTL_MAIN_STATE_XTAL_ISO_M (BIT(17)) #define RTC_CNTL_MAIN_STATE_XTAL_ISO_V 0x1 #define RTC_CNTL_MAIN_STATE_XTAL_ISO_S 17 /* RTC_CNTL_COCPU_STATE_DONE : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: ulp/cocpu is done.*/ -#define RTC_CNTL_COCPU_STATE_DONE (BIT(16)) +/*description: ulp/cocpu is done*/ +#define RTC_CNTL_COCPU_STATE_DONE (BIT(16)) #define RTC_CNTL_COCPU_STATE_DONE_M (BIT(16)) #define RTC_CNTL_COCPU_STATE_DONE_V 0x1 #define RTC_CNTL_COCPU_STATE_DONE_S 16 /* RTC_CNTL_COCPU_STATE_SLP : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: ulp/cocpu is in sleep state.*/ -#define RTC_CNTL_COCPU_STATE_SLP (BIT(15)) +/*description: ulp/cocpu is in sleep state*/ +#define RTC_CNTL_COCPU_STATE_SLP (BIT(15)) #define RTC_CNTL_COCPU_STATE_SLP_M (BIT(15)) #define RTC_CNTL_COCPU_STATE_SLP_V 0x1 #define RTC_CNTL_COCPU_STATE_SLP_S 15 /* RTC_CNTL_COCPU_STATE_SWITCH : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: ulp/cocpu is about to working. Switch rtc main state.*/ -#define RTC_CNTL_COCPU_STATE_SWITCH (BIT(14)) +/*description: ulp/cocpu is about to working. Switch rtc main state*/ +#define RTC_CNTL_COCPU_STATE_SWITCH (BIT(14)) #define RTC_CNTL_COCPU_STATE_SWITCH_M (BIT(14)) #define RTC_CNTL_COCPU_STATE_SWITCH_V 0x1 #define RTC_CNTL_COCPU_STATE_SWITCH_S 14 /* RTC_CNTL_COCPU_STATE_START : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: ulp/cocpu should start to work.*/ -#define RTC_CNTL_COCPU_STATE_START (BIT(13)) +/*description: ulp/cocpu should start to work*/ +#define RTC_CNTL_COCPU_STATE_START (BIT(13)) #define RTC_CNTL_COCPU_STATE_START_M (BIT(13)) #define RTC_CNTL_COCPU_STATE_START_V 0x1 #define RTC_CNTL_COCPU_STATE_START_S 13 /* RTC_CNTL_TOUCH_STATE_DONE : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: touch is done.*/ -#define RTC_CNTL_TOUCH_STATE_DONE (BIT(12)) +/*description: touch is done*/ +#define RTC_CNTL_TOUCH_STATE_DONE (BIT(12)) #define RTC_CNTL_TOUCH_STATE_DONE_M (BIT(12)) #define RTC_CNTL_TOUCH_STATE_DONE_V 0x1 #define RTC_CNTL_TOUCH_STATE_DONE_S 12 /* RTC_CNTL_TOUCH_STATE_SLP : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: touch is in sleep state.*/ -#define RTC_CNTL_TOUCH_STATE_SLP (BIT(11)) +/*description: touch is in sleep state*/ +#define RTC_CNTL_TOUCH_STATE_SLP (BIT(11)) #define RTC_CNTL_TOUCH_STATE_SLP_M (BIT(11)) #define RTC_CNTL_TOUCH_STATE_SLP_V 0x1 #define RTC_CNTL_TOUCH_STATE_SLP_S 11 /* RTC_CNTL_TOUCH_STATE_SWITCH : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: touch is about to working. Switch rtc main state.*/ -#define RTC_CNTL_TOUCH_STATE_SWITCH (BIT(10)) +/*description: touch is about to working. Switch rtc main state*/ +#define RTC_CNTL_TOUCH_STATE_SWITCH (BIT(10)) #define RTC_CNTL_TOUCH_STATE_SWITCH_M (BIT(10)) #define RTC_CNTL_TOUCH_STATE_SWITCH_V 0x1 #define RTC_CNTL_TOUCH_STATE_SWITCH_S 10 /* RTC_CNTL_TOUCH_STATE_START : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: touch should start to work.*/ -#define RTC_CNTL_TOUCH_STATE_START (BIT(9)) +/*description: touch should start to work*/ +#define RTC_CNTL_TOUCH_STATE_START (BIT(9)) #define RTC_CNTL_TOUCH_STATE_START_M (BIT(9)) #define RTC_CNTL_TOUCH_STATE_START_V 0x1 #define RTC_CNTL_TOUCH_STATE_START_S 9 /* RTC_CNTL_XPD_DIG : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: digital wrap power down.*/ -#define RTC_CNTL_XPD_DIG (BIT(8)) +/*description: digital wrap power down*/ +#define RTC_CNTL_XPD_DIG (BIT(8)) #define RTC_CNTL_XPD_DIG_M (BIT(8)) #define RTC_CNTL_XPD_DIG_V 0x1 #define RTC_CNTL_XPD_DIG_S 8 /* RTC_CNTL_DIG_ISO : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: digital wrap iso.*/ -#define RTC_CNTL_DIG_ISO (BIT(7)) +/*description: digital wrap iso*/ +#define RTC_CNTL_DIG_ISO (BIT(7)) #define RTC_CNTL_DIG_ISO_M (BIT(7)) #define RTC_CNTL_DIG_ISO_V 0x1 #define RTC_CNTL_DIG_ISO_S 7 /* RTC_CNTL_XPD_WIFI : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: wifi wrap power down.*/ -#define RTC_CNTL_XPD_WIFI (BIT(6)) +/*description: wifi wrap power down*/ +#define RTC_CNTL_XPD_WIFI (BIT(6)) #define RTC_CNTL_XPD_WIFI_M (BIT(6)) #define RTC_CNTL_XPD_WIFI_V 0x1 #define RTC_CNTL_XPD_WIFI_S 6 /* RTC_CNTL_WIFI_ISO : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: wifi iso.*/ -#define RTC_CNTL_WIFI_ISO (BIT(5)) +/*description: wifi iso*/ +#define RTC_CNTL_WIFI_ISO (BIT(5)) #define RTC_CNTL_WIFI_ISO_M (BIT(5)) #define RTC_CNTL_WIFI_ISO_V 0x1 #define RTC_CNTL_WIFI_ISO_S 5 /* RTC_CNTL_XPD_RTC_PERI : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: rtc peripheral power down .*/ -#define RTC_CNTL_XPD_RTC_PERI (BIT(4)) +/*description: rtc peripheral power down*/ +#define RTC_CNTL_XPD_RTC_PERI (BIT(4)) #define RTC_CNTL_XPD_RTC_PERI_M (BIT(4)) #define RTC_CNTL_XPD_RTC_PERI_V 0x1 #define RTC_CNTL_XPD_RTC_PERI_S 4 /* RTC_CNTL_PERI_ISO : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: rtc peripheral iso.*/ -#define RTC_CNTL_PERI_ISO (BIT(3)) +/*description: rtc peripheral iso*/ +#define RTC_CNTL_PERI_ISO (BIT(3)) #define RTC_CNTL_PERI_ISO_M (BIT(3)) #define RTC_CNTL_PERI_ISO_V 0x1 #define RTC_CNTL_PERI_ISO_S 3 /* RTC_CNTL_XPD_DIG_DCDC : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: External DCDC power down.*/ -#define RTC_CNTL_XPD_DIG_DCDC (BIT(2)) +/*description: External DCDC power down*/ +#define RTC_CNTL_XPD_DIG_DCDC (BIT(2)) #define RTC_CNTL_XPD_DIG_DCDC_M (BIT(2)) #define RTC_CNTL_XPD_DIG_DCDC_V 0x1 #define RTC_CNTL_XPD_DIG_DCDC_S 2 /* RTC_CNTL_XPD_ROM0 : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: rom0 power down.*/ -#define RTC_CNTL_XPD_ROM0 (BIT(0)) +/*description: rom0 power down*/ +#define RTC_CNTL_XPD_ROM0 (BIT(0)) #define RTC_CNTL_XPD_ROM0_M (BIT(0)) #define RTC_CNTL_XPD_ROM0_V 0x1 #define RTC_CNTL_XPD_ROM0_S 0 -#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0xD0) +#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0x00D0) /* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */ -/*description: .*/ -#define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF +/*description: */ +#define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF #define RTC_CNTL_LOW_POWER_DIAG1_M ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S)) #define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF #define RTC_CNTL_LOW_POWER_DIAG1_S 0 -#define RTC_CNTL_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0xD4) +#define RTC_CNTL_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D4) /* RTC_CNTL_PAD21_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_PAD21_HOLD (BIT(21)) +/*description: */ +#define RTC_CNTL_PAD21_HOLD (BIT(21)) #define RTC_CNTL_PAD21_HOLD_M (BIT(21)) #define RTC_CNTL_PAD21_HOLD_V 0x1 #define RTC_CNTL_PAD21_HOLD_S 21 /* RTC_CNTL_PAD20_HOLD : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_PAD20_HOLD (BIT(20)) +/*description: */ +#define RTC_CNTL_PAD20_HOLD (BIT(20)) #define RTC_CNTL_PAD20_HOLD_M (BIT(20)) #define RTC_CNTL_PAD20_HOLD_V 0x1 #define RTC_CNTL_PAD20_HOLD_S 20 /* RTC_CNTL_PAD19_HOLD : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_PAD19_HOLD (BIT(19)) +/*description: */ +#define RTC_CNTL_PAD19_HOLD (BIT(19)) #define RTC_CNTL_PAD19_HOLD_M (BIT(19)) #define RTC_CNTL_PAD19_HOLD_V 0x1 #define RTC_CNTL_PAD19_HOLD_S 19 /* RTC_CNTL_PDAC2_HOLD : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_PDAC2_HOLD (BIT(18)) +/*description: */ +#define RTC_CNTL_PDAC2_HOLD (BIT(18)) #define RTC_CNTL_PDAC2_HOLD_M (BIT(18)) #define RTC_CNTL_PDAC2_HOLD_V 0x1 #define RTC_CNTL_PDAC2_HOLD_S 18 /* RTC_CNTL_PDAC1_HOLD : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_PDAC1_HOLD (BIT(17)) +/*description: */ +#define RTC_CNTL_PDAC1_HOLD (BIT(17)) #define RTC_CNTL_PDAC1_HOLD_M (BIT(17)) #define RTC_CNTL_PDAC1_HOLD_V 0x1 #define RTC_CNTL_PDAC1_HOLD_S 17 /* RTC_CNTL_X32N_HOLD : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_X32N_HOLD (BIT(16)) +/*description: */ +#define RTC_CNTL_X32N_HOLD (BIT(16)) #define RTC_CNTL_X32N_HOLD_M (BIT(16)) #define RTC_CNTL_X32N_HOLD_V 0x1 #define RTC_CNTL_X32N_HOLD_S 16 /* RTC_CNTL_X32P_HOLD : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_X32P_HOLD (BIT(15)) +/*description: */ +#define RTC_CNTL_X32P_HOLD (BIT(15)) #define RTC_CNTL_X32P_HOLD_M (BIT(15)) #define RTC_CNTL_X32P_HOLD_V 0x1 #define RTC_CNTL_X32P_HOLD_S 15 /* RTC_CNTL_TOUCH_PAD14_HOLD : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_PAD14_HOLD (BIT(14)) +/*description: */ +#define RTC_CNTL_TOUCH_PAD14_HOLD (BIT(14)) #define RTC_CNTL_TOUCH_PAD14_HOLD_M (BIT(14)) #define RTC_CNTL_TOUCH_PAD14_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD14_HOLD_S 14 /* RTC_CNTL_TOUCH_PAD13_HOLD : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_PAD13_HOLD (BIT(13)) +/*description: */ +#define RTC_CNTL_TOUCH_PAD13_HOLD (BIT(13)) #define RTC_CNTL_TOUCH_PAD13_HOLD_M (BIT(13)) #define RTC_CNTL_TOUCH_PAD13_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD13_HOLD_S 13 /* RTC_CNTL_TOUCH_PAD12_HOLD : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_PAD12_HOLD (BIT(12)) +/*description: */ +#define RTC_CNTL_TOUCH_PAD12_HOLD (BIT(12)) #define RTC_CNTL_TOUCH_PAD12_HOLD_M (BIT(12)) #define RTC_CNTL_TOUCH_PAD12_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD12_HOLD_S 12 /* RTC_CNTL_TOUCH_PAD11_HOLD : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_PAD11_HOLD (BIT(11)) +/*description: */ +#define RTC_CNTL_TOUCH_PAD11_HOLD (BIT(11)) #define RTC_CNTL_TOUCH_PAD11_HOLD_M (BIT(11)) #define RTC_CNTL_TOUCH_PAD11_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD11_HOLD_S 11 /* RTC_CNTL_TOUCH_PAD10_HOLD : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_PAD10_HOLD (BIT(10)) +/*description: */ +#define RTC_CNTL_TOUCH_PAD10_HOLD (BIT(10)) #define RTC_CNTL_TOUCH_PAD10_HOLD_M (BIT(10)) #define RTC_CNTL_TOUCH_PAD10_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD10_HOLD_S 10 /* RTC_CNTL_TOUCH_PAD9_HOLD : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_PAD9_HOLD (BIT(9)) +/*description: */ +#define RTC_CNTL_TOUCH_PAD9_HOLD (BIT(9)) #define RTC_CNTL_TOUCH_PAD9_HOLD_M (BIT(9)) #define RTC_CNTL_TOUCH_PAD9_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD9_HOLD_S 9 /* RTC_CNTL_TOUCH_PAD8_HOLD : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_PAD8_HOLD (BIT(8)) +/*description: */ +#define RTC_CNTL_TOUCH_PAD8_HOLD (BIT(8)) #define RTC_CNTL_TOUCH_PAD8_HOLD_M (BIT(8)) #define RTC_CNTL_TOUCH_PAD8_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD8_HOLD_S 8 /* RTC_CNTL_TOUCH_PAD7_HOLD : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_PAD7_HOLD (BIT(7)) +/*description: */ +#define RTC_CNTL_TOUCH_PAD7_HOLD (BIT(7)) #define RTC_CNTL_TOUCH_PAD7_HOLD_M (BIT(7)) #define RTC_CNTL_TOUCH_PAD7_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD7_HOLD_S 7 /* RTC_CNTL_TOUCH_PAD6_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_PAD6_HOLD (BIT(6)) +/*description: */ +#define RTC_CNTL_TOUCH_PAD6_HOLD (BIT(6)) #define RTC_CNTL_TOUCH_PAD6_HOLD_M (BIT(6)) #define RTC_CNTL_TOUCH_PAD6_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD6_HOLD_S 6 /* RTC_CNTL_TOUCH_PAD5_HOLD : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_PAD5_HOLD (BIT(5)) +/*description: */ +#define RTC_CNTL_TOUCH_PAD5_HOLD (BIT(5)) #define RTC_CNTL_TOUCH_PAD5_HOLD_M (BIT(5)) #define RTC_CNTL_TOUCH_PAD5_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD5_HOLD_S 5 /* RTC_CNTL_TOUCH_PAD4_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_PAD4_HOLD (BIT(4)) +/*description: */ +#define RTC_CNTL_TOUCH_PAD4_HOLD (BIT(4)) #define RTC_CNTL_TOUCH_PAD4_HOLD_M (BIT(4)) #define RTC_CNTL_TOUCH_PAD4_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD4_HOLD_S 4 /* RTC_CNTL_TOUCH_PAD3_HOLD : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_PAD3_HOLD (BIT(3)) +/*description: */ +#define RTC_CNTL_TOUCH_PAD3_HOLD (BIT(3)) #define RTC_CNTL_TOUCH_PAD3_HOLD_M (BIT(3)) #define RTC_CNTL_TOUCH_PAD3_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD3_HOLD_S 3 /* RTC_CNTL_TOUCH_PAD2_HOLD : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_PAD2_HOLD (BIT(2)) +/*description: */ +#define RTC_CNTL_TOUCH_PAD2_HOLD (BIT(2)) #define RTC_CNTL_TOUCH_PAD2_HOLD_M (BIT(2)) #define RTC_CNTL_TOUCH_PAD2_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD2_HOLD_S 2 /* RTC_CNTL_TOUCH_PAD1_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_PAD1_HOLD (BIT(1)) +/*description: */ +#define RTC_CNTL_TOUCH_PAD1_HOLD (BIT(1)) #define RTC_CNTL_TOUCH_PAD1_HOLD_M (BIT(1)) #define RTC_CNTL_TOUCH_PAD1_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD1_HOLD_S 1 /* RTC_CNTL_TOUCH_PAD0_HOLD : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_PAD0_HOLD (BIT(0)) +/*description: */ +#define RTC_CNTL_TOUCH_PAD0_HOLD (BIT(0)) #define RTC_CNTL_TOUCH_PAD0_HOLD_M (BIT(0)) #define RTC_CNTL_TOUCH_PAD0_HOLD_V 0x1 #define RTC_CNTL_TOUCH_PAD0_HOLD_S 0 -#define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0xD8) +#define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D8) /* RTC_CNTL_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ -/*description: .*/ -#define RTC_CNTL_DIG_PAD_HOLD 0xFFFFFFFF +/*description: */ +#define RTC_CNTL_DIG_PAD_HOLD 0xFFFFFFFF #define RTC_CNTL_DIG_PAD_HOLD_M ((RTC_CNTL_DIG_PAD_HOLD_V)<<(RTC_CNTL_DIG_PAD_HOLD_S)) #define RTC_CNTL_DIG_PAD_HOLD_V 0xFFFFFFFF #define RTC_CNTL_DIG_PAD_HOLD_S 0 -#define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0xDC) +#define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0x00DC) /* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ -/*description: clear ext wakeup1 status.*/ -#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(22)) +/*description: clear ext wakeup1 status*/ +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(22)) #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M (BIT(22)) #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V 0x1 #define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 22 /* RTC_CNTL_EXT_WAKEUP1_SEL : R/W ;bitpos:[21:0] ;default: 22'd0 ; */ -/*description: Bitmap to select RTC pads for ext wakeup1.*/ -#define RTC_CNTL_EXT_WAKEUP1_SEL 0x003FFFFF +/*description: Bitmap to select RTC pads for ext wakeup1*/ +#define RTC_CNTL_EXT_WAKEUP1_SEL 0x003FFFFF #define RTC_CNTL_EXT_WAKEUP1_SEL_M ((RTC_CNTL_EXT_WAKEUP1_SEL_V)<<(RTC_CNTL_EXT_WAKEUP1_SEL_S)) #define RTC_CNTL_EXT_WAKEUP1_SEL_V 0x3FFFFF #define RTC_CNTL_EXT_WAKEUP1_SEL_S 0 -#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0xE0) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0x00E0) /* RTC_CNTL_EXT_WAKEUP1_STATUS : RO ;bitpos:[21:0] ;default: 22'd0 ; */ -/*description: ext wakeup1 status.*/ -#define RTC_CNTL_EXT_WAKEUP1_STATUS 0x003FFFFF +/*description: ext wakeup1 status*/ +#define RTC_CNTL_EXT_WAKEUP1_STATUS 0x003FFFFF #define RTC_CNTL_EXT_WAKEUP1_STATUS_M ((RTC_CNTL_EXT_WAKEUP1_STATUS_V)<<(RTC_CNTL_EXT_WAKEUP1_STATUS_S)) #define RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x3FFFFF #define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0 -#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0xE4) +#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0x00E4) /* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_BROWN_OUT_DET (BIT(31)) +/*description: */ +#define RTC_CNTL_BROWN_OUT_DET (BIT(31)) #define RTC_CNTL_BROWN_OUT_DET_M (BIT(31)) #define RTC_CNTL_BROWN_OUT_DET_V 0x1 #define RTC_CNTL_BROWN_OUT_DET_S 31 /* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b1 ; */ -/*description: enable brown out.*/ -#define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) +/*description: enable brown out*/ +#define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) #define RTC_CNTL_BROWN_OUT_ENA_M (BIT(30)) #define RTC_CNTL_BROWN_OUT_ENA_V 0x1 #define RTC_CNTL_BROWN_OUT_ENA_S 30 /* RTC_CNTL_BROWN_OUT_CNT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: clear brown out counter.*/ -#define RTC_CNTL_BROWN_OUT_CNT_CLR (BIT(29)) +/*description: clear brown out counter*/ +#define RTC_CNTL_BROWN_OUT_CNT_CLR (BIT(29)) #define RTC_CNTL_BROWN_OUT_CNT_CLR_M (BIT(29)) #define RTC_CNTL_BROWN_OUT_CNT_CLR_V 0x1 #define RTC_CNTL_BROWN_OUT_CNT_CLR_S 29 /* RTC_CNTL_BROWN_OUT_ANA_RST_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_BROWN_OUT_ANA_RST_EN (BIT(28)) +/*description: */ +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN (BIT(28)) #define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M (BIT(28)) #define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V 0x1 #define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S 28 /* RTC_CNTL_BROWN_OUT_RST_SEL : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: 1: 4-pos reset.*/ -#define RTC_CNTL_BROWN_OUT_RST_SEL (BIT(27)) +/*description: 1: 4-pos reset*/ +#define RTC_CNTL_BROWN_OUT_RST_SEL (BIT(27)) #define RTC_CNTL_BROWN_OUT_RST_SEL_M (BIT(27)) #define RTC_CNTL_BROWN_OUT_RST_SEL_V 0x1 #define RTC_CNTL_BROWN_OUT_RST_SEL_S 27 /* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: enable brown out reset.*/ -#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) +/*description: enable brown out reset*/ +#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) #define RTC_CNTL_BROWN_OUT_RST_ENA_M (BIT(26)) #define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x1 #define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 /* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */ -/*description: brown out reset wait cycles.*/ -#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF +/*description: brown out reset wait cycles*/ +#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF #define RTC_CNTL_BROWN_OUT_RST_WAIT_M ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S)) #define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x3FF #define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 /* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: enable power down RF when brown out happens.*/ -#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) +/*description: enable power down RF when brown out happens*/ +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15)) #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1 #define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 /* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: enable close flash when brown out happens.*/ -#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) +/*description: enable close flash when brown out happens*/ +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (BIT(14)) #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x1 #define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 /* RTC_CNTL_BROWN_OUT_INT_WAIT : R/W ;bitpos:[13:4] ;default: 10'h1 ; */ -/*description: brown out interrupt wait cycles.*/ -#define RTC_CNTL_BROWN_OUT_INT_WAIT 0x000003FF +/*description: brown out interrupt wait cycles*/ +#define RTC_CNTL_BROWN_OUT_INT_WAIT 0x000003FF #define RTC_CNTL_BROWN_OUT_INT_WAIT_M ((RTC_CNTL_BROWN_OUT_INT_WAIT_V)<<(RTC_CNTL_BROWN_OUT_INT_WAIT_S)) #define RTC_CNTL_BROWN_OUT_INT_WAIT_V 0x3FF #define RTC_CNTL_BROWN_OUT_INT_WAIT_S 4 -#define RTC_CNTL_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0xE8) +#define RTC_CNTL_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0x00E8) /* RTC_CNTL_TIMER_VALUE1_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: RTC timer low 32 bits.*/ -#define RTC_CNTL_TIMER_VALUE1_LOW 0xFFFFFFFF +/*description: RTC timer low 32 bits*/ +#define RTC_CNTL_TIMER_VALUE1_LOW 0xFFFFFFFF #define RTC_CNTL_TIMER_VALUE1_LOW_M ((RTC_CNTL_TIMER_VALUE1_LOW_V)<<(RTC_CNTL_TIMER_VALUE1_LOW_S)) #define RTC_CNTL_TIMER_VALUE1_LOW_V 0xFFFFFFFF #define RTC_CNTL_TIMER_VALUE1_LOW_S 0 -#define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0xEC) +#define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0x00EC) /* RTC_CNTL_TIMER_VALUE1_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: RTC timer high 16 bits.*/ -#define RTC_CNTL_TIMER_VALUE1_HIGH 0x0000FFFF +/*description: RTC timer high 16 bits*/ +#define RTC_CNTL_TIMER_VALUE1_HIGH 0x0000FFFF #define RTC_CNTL_TIMER_VALUE1_HIGH_M ((RTC_CNTL_TIMER_VALUE1_HIGH_V)<<(RTC_CNTL_TIMER_VALUE1_HIGH_S)) #define RTC_CNTL_TIMER_VALUE1_HIGH_V 0xFFFF #define RTC_CNTL_TIMER_VALUE1_HIGH_S 0 -#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0xF0) +#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0x00F0) /* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: xtal 32k watch dog backup clock factor.*/ -#define RTC_CNTL_XTAL32K_CLK_FACTOR 0xFFFFFFFF +/*description: xtal 32k watch dog backup clock factor*/ +#define RTC_CNTL_XTAL32K_CLK_FACTOR 0xFFFFFFFF #define RTC_CNTL_XTAL32K_CLK_FACTOR_M ((RTC_CNTL_XTAL32K_CLK_FACTOR_V)<<(RTC_CNTL_XTAL32K_CLK_FACTOR_S)) #define RTC_CNTL_XTAL32K_CLK_FACTOR_V 0xFFFFFFFF #define RTC_CNTL_XTAL32K_CLK_FACTOR_S 0 -#define RTC_CNTL_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0xF4) +#define RTC_CNTL_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00F4) /* RTC_CNTL_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: if restarted xtal32k period is smaller than this.*/ -#define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000F +/*description: if restarted xtal32k period is smaller than this*/ +#define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000F #define RTC_CNTL_XTAL32K_STABLE_THRES_M ((RTC_CNTL_XTAL32K_STABLE_THRES_V)<<(RTC_CNTL_XTAL32K_STABLE_THRES_S)) #define RTC_CNTL_XTAL32K_STABLE_THRES_V 0xF #define RTC_CNTL_XTAL32K_STABLE_THRES_S 28 /* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W ;bitpos:[27:20] ;default: 8'hff ; */ -/*description: If no clock detected for this amount of time.*/ -#define RTC_CNTL_XTAL32K_WDT_TIMEOUT 0x000000FF +/*description: If no clock detected for this amount of time*/ +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT 0x000000FF #define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M ((RTC_CNTL_XTAL32K_WDT_TIMEOUT_V)<<(RTC_CNTL_XTAL32K_WDT_TIMEOUT_S)) #define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V 0xFF #define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S 20 /* RTC_CNTL_XTAL32K_RESTART_WAIT : R/W ;bitpos:[19:4] ;default: 16'h0 ; */ -/*description: cycles to wait to repower on xtal 32k.*/ -#define RTC_CNTL_XTAL32K_RESTART_WAIT 0x0000FFFF +/*description: cycles to wait to repower on xtal 32k*/ +#define RTC_CNTL_XTAL32K_RESTART_WAIT 0x0000FFFF #define RTC_CNTL_XTAL32K_RESTART_WAIT_M ((RTC_CNTL_XTAL32K_RESTART_WAIT_V)<<(RTC_CNTL_XTAL32K_RESTART_WAIT_S)) #define RTC_CNTL_XTAL32K_RESTART_WAIT_V 0xFFFF #define RTC_CNTL_XTAL32K_RESTART_WAIT_S 4 /* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ -/*description: cycles to wait to return noral xtal 32k.*/ -#define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000F +/*description: cycles to wait to return noral xtal 32k*/ +#define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000F #define RTC_CNTL_XTAL32K_RETURN_WAIT_M ((RTC_CNTL_XTAL32K_RETURN_WAIT_V)<<(RTC_CNTL_XTAL32K_RETURN_WAIT_S)) #define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0xF #define RTC_CNTL_XTAL32K_RETURN_WAIT_S 0 -#define RTC_CNTL_ULP_CP_TIMER_REG (DR_REG_RTCCNTL_BASE + 0xF8) +#define RTC_CNTL_ULP_CP_TIMER_REG (DR_REG_RTCCNTL_BASE + 0x00F8) /* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: ULP-coprocessor timer enable bit.*/ -#define RTC_CNTL_ULP_CP_SLP_TIMER_EN (BIT(31)) +/*description: ULP-coprocessor timer enable bit*/ +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN (BIT(31)) #define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M (BIT(31)) #define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V 0x1 #define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S 31 /* RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR : WO ;bitpos:[30] ;default: 1'd0 ; */ -/*description: ULP-coprocessor wakeup by GPIO state clear.*/ -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR (BIT(30)) +/*description: ULP-coprocessor wakeup by GPIO state clear*/ +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR (BIT(30)) #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_M (BIT(30)) #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_V 0x1 #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_S 30 /* RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: ULP-coprocessor wakeup by GPIO enable.*/ -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA (BIT(29)) +/*description: ULP-coprocessor wakeup by GPIO enable*/ +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA (BIT(29)) #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_M (BIT(29)) #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_V 0x1 #define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_S 29 /* RTC_CNTL_ULP_CP_PC_INIT : R/W ;bitpos:[10:0] ;default: 11'b0 ; */ -/*description: ULP-coprocessor PC initial address.*/ -#define RTC_CNTL_ULP_CP_PC_INIT 0x000007FF +/*description: ULP-coprocessor PC initial address*/ +#define RTC_CNTL_ULP_CP_PC_INIT 0x000007FF #define RTC_CNTL_ULP_CP_PC_INIT_M ((RTC_CNTL_ULP_CP_PC_INIT_V)<<(RTC_CNTL_ULP_CP_PC_INIT_S)) #define RTC_CNTL_ULP_CP_PC_INIT_V 0x7FF #define RTC_CNTL_ULP_CP_PC_INIT_S 0 -#define RTC_CNTL_ULP_CP_CTRL_REG (DR_REG_RTCCNTL_BASE + 0xFC) +#define RTC_CNTL_ULP_CP_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x00FC) /* RTC_CNTL_ULP_CP_START_TOP : R/W ;bitpos:[31] ;default: 1'd0 ; */ -/*description: Write 1 to start ULP-coprocessor.*/ -#define RTC_CNTL_ULP_CP_START_TOP (BIT(31)) +/*description: Write 1 to start ULP-coprocessor*/ +#define RTC_CNTL_ULP_CP_START_TOP (BIT(31)) #define RTC_CNTL_ULP_CP_START_TOP_M (BIT(31)) #define RTC_CNTL_ULP_CP_START_TOP_V 0x1 #define RTC_CNTL_ULP_CP_START_TOP_S 31 /* RTC_CNTL_ULP_CP_FORCE_START_TOP : R/W ;bitpos:[30] ;default: 1'd0 ; */ -/*description: 1: ULP-coprocessor is started by SW.*/ -#define RTC_CNTL_ULP_CP_FORCE_START_TOP (BIT(30)) +/*description: 1: ULP-coprocessor is started by SW*/ +#define RTC_CNTL_ULP_CP_FORCE_START_TOP (BIT(30)) #define RTC_CNTL_ULP_CP_FORCE_START_TOP_M (BIT(30)) #define RTC_CNTL_ULP_CP_FORCE_START_TOP_V 0x1 #define RTC_CNTL_ULP_CP_FORCE_START_TOP_S 30 /* RTC_CNTL_ULP_CP_RESET : R/W ;bitpos:[29] ;default: 1'd0 ; */ -/*description: ulp coprocessor clk software reset.*/ -#define RTC_CNTL_ULP_CP_RESET (BIT(29)) +/*description: ulp coprocessor clk software reset*/ +#define RTC_CNTL_ULP_CP_RESET (BIT(29)) #define RTC_CNTL_ULP_CP_RESET_M (BIT(29)) #define RTC_CNTL_ULP_CP_RESET_V 0x1 #define RTC_CNTL_ULP_CP_RESET_S 29 /* RTC_CNTL_ULP_CP_CLK_FO : R/W ;bitpos:[28] ;default: 1'd0 ; */ -/*description: ulp coprocessor clk force on.*/ -#define RTC_CNTL_ULP_CP_CLK_FO (BIT(28)) +/*description: ulp coprocessor clk force on*/ +#define RTC_CNTL_ULP_CP_CLK_FO (BIT(28)) #define RTC_CNTL_ULP_CP_CLK_FO_M (BIT(28)) #define RTC_CNTL_ULP_CP_CLK_FO_V 0x1 #define RTC_CNTL_ULP_CP_CLK_FO_S 28 /* RTC_CNTL_ULP_CP_MEM_OFFST_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ -/*description: .*/ -#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR (BIT(22)) +/*description: */ +#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR (BIT(22)) #define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_M (BIT(22)) #define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_V 0x1 #define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_S 22 /* RTC_CNTL_ULP_CP_MEM_ADDR_SIZE : R/W ;bitpos:[21:11] ;default: 11'd512 ; */ -/*description: .*/ -#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE 0x000007FF +/*description: */ +#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE 0x000007FF #define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_M ((RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V)<<(RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S)) #define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V 0x7FF #define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S 11 /* RTC_CNTL_ULP_CP_MEM_ADDR_INIT : R/W ;bitpos:[10:0] ;default: 11'd512 ; */ -/*description: .*/ -#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT 0x000007FF +/*description: */ +#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT 0x000007FF #define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_M ((RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V)<<(RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S)) #define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V 0x7FF #define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S 0 -#define RTC_CNTL_COCPU_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x100) +#define RTC_CNTL_COCPU_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0100) /* RTC_CNTL_COCPU_CLKGATE_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_COCPU_CLKGATE_EN (BIT(27)) +/*description: */ +#define RTC_CNTL_COCPU_CLKGATE_EN (BIT(27)) #define RTC_CNTL_COCPU_CLKGATE_EN_M (BIT(27)) #define RTC_CNTL_COCPU_CLKGATE_EN_V 0x1 #define RTC_CNTL_COCPU_CLKGATE_EN_S 27 /* RTC_CNTL_COCPU_SW_INT_TRIGGER : WO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: trigger cocpu register interrupt.*/ -#define RTC_CNTL_COCPU_SW_INT_TRIGGER (BIT(26)) +/*description: trigger cocpu register interrupt*/ +#define RTC_CNTL_COCPU_SW_INT_TRIGGER (BIT(26)) #define RTC_CNTL_COCPU_SW_INT_TRIGGER_M (BIT(26)) #define RTC_CNTL_COCPU_SW_INT_TRIGGER_V 0x1 #define RTC_CNTL_COCPU_SW_INT_TRIGGER_S 26 /* RTC_CNTL_COCPU_DONE : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: done signal used by riscv to control timer. .*/ -#define RTC_CNTL_COCPU_DONE (BIT(25)) +/*description: done signal used by riscv to control timer.*/ +#define RTC_CNTL_COCPU_DONE (BIT(25)) #define RTC_CNTL_COCPU_DONE_M (BIT(25)) #define RTC_CNTL_COCPU_DONE_V 0x1 #define RTC_CNTL_COCPU_DONE_S 25 /* RTC_CNTL_COCPU_DONE_FORCE : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: 1: select riscv done 0: select ulp done.*/ -#define RTC_CNTL_COCPU_DONE_FORCE (BIT(24)) +/*description: 1: select riscv done 0: select ulp done*/ +#define RTC_CNTL_COCPU_DONE_FORCE (BIT(24)) #define RTC_CNTL_COCPU_DONE_FORCE_M (BIT(24)) #define RTC_CNTL_COCPU_DONE_FORCE_V 0x1 #define RTC_CNTL_COCPU_DONE_FORCE_S 24 /* RTC_CNTL_COCPU_SEL : R/W ;bitpos:[23] ;default: 1'b1 ; */ -/*description: 1: old ULP 0: new riscV.*/ -#define RTC_CNTL_COCPU_SEL (BIT(23)) +/*description: 1: old ULP 0: new riscV*/ +#define RTC_CNTL_COCPU_SEL (BIT(23)) #define RTC_CNTL_COCPU_SEL_M (BIT(23)) #define RTC_CNTL_COCPU_SEL_V 0x1 #define RTC_CNTL_COCPU_SEL_S 23 /* RTC_CNTL_COCPU_SHUT_RESET_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: to reset cocpu.*/ -#define RTC_CNTL_COCPU_SHUT_RESET_EN (BIT(22)) +/*description: to reset cocpu*/ +#define RTC_CNTL_COCPU_SHUT_RESET_EN (BIT(22)) #define RTC_CNTL_COCPU_SHUT_RESET_EN_M (BIT(22)) #define RTC_CNTL_COCPU_SHUT_RESET_EN_V 0x1 #define RTC_CNTL_COCPU_SHUT_RESET_EN_S 22 /* RTC_CNTL_COCPU_SHUT_2_CLK_DIS : R/W ;bitpos:[21:14] ;default: 8'd40 ; */ -/*description: time from shut cocpu to disable clk.*/ -#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS 0x000000FF +/*description: time from shut cocpu to disable clk*/ +#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS 0x000000FF #define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_M ((RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V)<<(RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S)) #define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V 0xFF #define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S 14 /* RTC_CNTL_COCPU_SHUT : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: to shut cocpu.*/ -#define RTC_CNTL_COCPU_SHUT (BIT(13)) +/*description: to shut cocpu*/ +#define RTC_CNTL_COCPU_SHUT (BIT(13)) #define RTC_CNTL_COCPU_SHUT_M (BIT(13)) #define RTC_CNTL_COCPU_SHUT_V 0x1 #define RTC_CNTL_COCPU_SHUT_S 13 /* RTC_CNTL_COCPU_START_2_INTR_EN : R/W ;bitpos:[12:7] ;default: 6'd16 ; */ -/*description: time from start cocpu to give start interrupt.*/ -#define RTC_CNTL_COCPU_START_2_INTR_EN 0x0000003F +/*description: time from start cocpu to give start interrupt*/ +#define RTC_CNTL_COCPU_START_2_INTR_EN 0x0000003F #define RTC_CNTL_COCPU_START_2_INTR_EN_M ((RTC_CNTL_COCPU_START_2_INTR_EN_V)<<(RTC_CNTL_COCPU_START_2_INTR_EN_S)) #define RTC_CNTL_COCPU_START_2_INTR_EN_V 0x3F #define RTC_CNTL_COCPU_START_2_INTR_EN_S 7 /* RTC_CNTL_COCPU_START_2_RESET_DIS : R/W ;bitpos:[6:1] ;default: 6'd8 ; */ -/*description: time from start cocpu to pull down reset.*/ -#define RTC_CNTL_COCPU_START_2_RESET_DIS 0x0000003F +/*description: time from start cocpu to pull down reset*/ +#define RTC_CNTL_COCPU_START_2_RESET_DIS 0x0000003F #define RTC_CNTL_COCPU_START_2_RESET_DIS_M ((RTC_CNTL_COCPU_START_2_RESET_DIS_V)<<(RTC_CNTL_COCPU_START_2_RESET_DIS_S)) #define RTC_CNTL_COCPU_START_2_RESET_DIS_V 0x3F #define RTC_CNTL_COCPU_START_2_RESET_DIS_S 1 /* RTC_CNTL_COCPU_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: cocpu clk force on.*/ -#define RTC_CNTL_COCPU_CLK_FO (BIT(0)) +/*description: cocpu clk force on*/ +#define RTC_CNTL_COCPU_CLK_FO (BIT(0)) #define RTC_CNTL_COCPU_CLK_FO_M (BIT(0)) #define RTC_CNTL_COCPU_CLK_FO_V 0x1 #define RTC_CNTL_COCPU_CLK_FO_S 0 -#define RTC_CNTL_TOUCH_CTRL1_REG (DR_REG_RTCCNTL_BASE + 0x104) +#define RTC_CNTL_TOUCH_CTRL1_REG (DR_REG_RTCCNTL_BASE + 0x0104) /* RTC_CNTL_TOUCH_MEAS_NUM : R/W ;bitpos:[31:16] ;default: 16'h1000 ; */ -/*description: the meas length (in 8MHz).*/ -#define RTC_CNTL_TOUCH_MEAS_NUM 0x0000FFFF +/*description: the meas length (in 8MHz)*/ +#define RTC_CNTL_TOUCH_MEAS_NUM 0x0000FFFF #define RTC_CNTL_TOUCH_MEAS_NUM_M ((RTC_CNTL_TOUCH_MEAS_NUM_V)<<(RTC_CNTL_TOUCH_MEAS_NUM_S)) #define RTC_CNTL_TOUCH_MEAS_NUM_V 0xFFFF #define RTC_CNTL_TOUCH_MEAS_NUM_S 16 /* RTC_CNTL_TOUCH_SLEEP_CYCLES : R/W ;bitpos:[15:0] ;default: 16'h100 ; */ -/*description: sleep cycles for timer.*/ -#define RTC_CNTL_TOUCH_SLEEP_CYCLES 0x0000FFFF +/*description: sleep cycles for timer*/ +#define RTC_CNTL_TOUCH_SLEEP_CYCLES 0x0000FFFF #define RTC_CNTL_TOUCH_SLEEP_CYCLES_M ((RTC_CNTL_TOUCH_SLEEP_CYCLES_V)<<(RTC_CNTL_TOUCH_SLEEP_CYCLES_S)) #define RTC_CNTL_TOUCH_SLEEP_CYCLES_V 0xFFFF #define RTC_CNTL_TOUCH_SLEEP_CYCLES_S 0 -#define RTC_CNTL_TOUCH_CTRL2_REG (DR_REG_RTCCNTL_BASE + 0x108) +#define RTC_CNTL_TOUCH_CTRL2_REG (DR_REG_RTCCNTL_BASE + 0x0108) /* RTC_CNTL_TOUCH_CLKGATE_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: touch clock enable.*/ -#define RTC_CNTL_TOUCH_CLKGATE_EN (BIT(31)) +/*description: touch clock enable*/ +#define RTC_CNTL_TOUCH_CLKGATE_EN (BIT(31)) #define RTC_CNTL_TOUCH_CLKGATE_EN_M (BIT(31)) #define RTC_CNTL_TOUCH_CLKGATE_EN_V 0x1 #define RTC_CNTL_TOUCH_CLKGATE_EN_S 31 /* RTC_CNTL_TOUCH_CLK_FO : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: touch clock force on.*/ -#define RTC_CNTL_TOUCH_CLK_FO (BIT(30)) +/*description: touch clock force on*/ +#define RTC_CNTL_TOUCH_CLK_FO (BIT(30)) #define RTC_CNTL_TOUCH_CLK_FO_M (BIT(30)) #define RTC_CNTL_TOUCH_CLK_FO_V 0x1 #define RTC_CNTL_TOUCH_CLK_FO_S 30 /* RTC_CNTL_TOUCH_RESET : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: reset upgrade touch.*/ -#define RTC_CNTL_TOUCH_RESET (BIT(29)) +/*description: reset upgrade touch*/ +#define RTC_CNTL_TOUCH_RESET (BIT(29)) #define RTC_CNTL_TOUCH_RESET_M (BIT(29)) #define RTC_CNTL_TOUCH_RESET_V 0x1 #define RTC_CNTL_TOUCH_RESET_S 29 /* RTC_CNTL_TOUCH_TIMER_FORCE_DONE : R/W ;bitpos:[28:27] ;default: 2'b0 ; */ -/*description: force touch timer done.*/ -#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE 0x00000003 +/*description: force touch timer done*/ +#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE 0x00000003 #define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_M ((RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V)<<(RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S)) #define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V 0x3 #define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S 27 /* RTC_CNTL_TOUCH_SLP_CYC_DIV : R/W ;bitpos:[26:25] ;default: 2'd0 ; */ -/*description: when a touch pad is active.*/ -#define RTC_CNTL_TOUCH_SLP_CYC_DIV 0x00000003 +/*description: when a touch pad is active*/ +#define RTC_CNTL_TOUCH_SLP_CYC_DIV 0x00000003 #define RTC_CNTL_TOUCH_SLP_CYC_DIV_M ((RTC_CNTL_TOUCH_SLP_CYC_DIV_V)<<(RTC_CNTL_TOUCH_SLP_CYC_DIV_S)) #define RTC_CNTL_TOUCH_SLP_CYC_DIV_V 0x3 #define RTC_CNTL_TOUCH_SLP_CYC_DIV_S 25 /* RTC_CNTL_TOUCH_XPD_WAIT : R/W ;bitpos:[24:17] ;default: 8'h4 ; */ -/*description: the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD.*/ -#define RTC_CNTL_TOUCH_XPD_WAIT 0x000000FF +/*description: the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/ +#define RTC_CNTL_TOUCH_XPD_WAIT 0x000000FF #define RTC_CNTL_TOUCH_XPD_WAIT_M ((RTC_CNTL_TOUCH_XPD_WAIT_V)<<(RTC_CNTL_TOUCH_XPD_WAIT_S)) #define RTC_CNTL_TOUCH_XPD_WAIT_V 0xFF #define RTC_CNTL_TOUCH_XPD_WAIT_S 17 /* RTC_CNTL_TOUCH_START_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: 1: to start touch fsm by SW.*/ -#define RTC_CNTL_TOUCH_START_FORCE (BIT(16)) +/*description: 1: to start touch fsm by SW*/ +#define RTC_CNTL_TOUCH_START_FORCE (BIT(16)) #define RTC_CNTL_TOUCH_START_FORCE_M (BIT(16)) #define RTC_CNTL_TOUCH_START_FORCE_V 0x1 #define RTC_CNTL_TOUCH_START_FORCE_S 16 /* RTC_CNTL_TOUCH_START_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: 1: start touch fsm.*/ -#define RTC_CNTL_TOUCH_START_EN (BIT(15)) +/*description: 1: start touch fsm*/ +#define RTC_CNTL_TOUCH_START_EN (BIT(15)) #define RTC_CNTL_TOUCH_START_EN_M (BIT(15)) #define RTC_CNTL_TOUCH_START_EN_V 0x1 #define RTC_CNTL_TOUCH_START_EN_S 15 /* RTC_CNTL_TOUCH_START_FSM_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ -/*description: 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm.*/ -#define RTC_CNTL_TOUCH_START_FSM_EN (BIT(14)) +/*description: 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm*/ +#define RTC_CNTL_TOUCH_START_FSM_EN (BIT(14)) #define RTC_CNTL_TOUCH_START_FSM_EN_M (BIT(14)) #define RTC_CNTL_TOUCH_START_FSM_EN_V 0x1 #define RTC_CNTL_TOUCH_START_FSM_EN_S 14 /* RTC_CNTL_TOUCH_SLP_TIMER_EN : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: touch timer enable bit.*/ -#define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(13)) +/*description: touch timer enable bit*/ +#define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(13)) #define RTC_CNTL_TOUCH_SLP_TIMER_EN_M (BIT(13)) #define RTC_CNTL_TOUCH_SLP_TIMER_EN_V 0x1 #define RTC_CNTL_TOUCH_SLP_TIMER_EN_S 13 /* RTC_CNTL_TOUCH_DBIAS : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: 1:use self bias 0:use bandgap bias.*/ -#define RTC_CNTL_TOUCH_DBIAS (BIT(12)) +/*description: 1:use self bias 0:use bandgap bias*/ +#define RTC_CNTL_TOUCH_DBIAS (BIT(12)) #define RTC_CNTL_TOUCH_DBIAS_M (BIT(12)) #define RTC_CNTL_TOUCH_DBIAS_V 0x1 #define RTC_CNTL_TOUCH_DBIAS_S 12 /* RTC_CNTL_TOUCH_REFC : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ -/*description: TOUCH pad0 reference cap.*/ -#define RTC_CNTL_TOUCH_REFC 0x00000007 +/*description: TOUCH pad0 reference cap*/ +#define RTC_CNTL_TOUCH_REFC 0x00000007 #define RTC_CNTL_TOUCH_REFC_M ((RTC_CNTL_TOUCH_REFC_V)<<(RTC_CNTL_TOUCH_REFC_S)) #define RTC_CNTL_TOUCH_REFC_V 0x7 #define RTC_CNTL_TOUCH_REFC_S 9 /* RTC_CNTL_TOUCH_XPD_BIAS : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: TOUCH_XPD_BIAS.*/ -#define RTC_CNTL_TOUCH_XPD_BIAS (BIT(8)) +/*description: TOUCH_XPD_BIAS*/ +#define RTC_CNTL_TOUCH_XPD_BIAS (BIT(8)) #define RTC_CNTL_TOUCH_XPD_BIAS_M (BIT(8)) #define RTC_CNTL_TOUCH_XPD_BIAS_V 0x1 #define RTC_CNTL_TOUCH_XPD_BIAS_S 8 /* RTC_CNTL_TOUCH_DREFH : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ -/*description: TOUCH_DREFH.*/ -#define RTC_CNTL_TOUCH_DREFH 0x00000003 +/*description: TOUCH_DREFH*/ +#define RTC_CNTL_TOUCH_DREFH 0x00000003 #define RTC_CNTL_TOUCH_DREFH_M ((RTC_CNTL_TOUCH_DREFH_V)<<(RTC_CNTL_TOUCH_DREFH_S)) #define RTC_CNTL_TOUCH_DREFH_V 0x3 #define RTC_CNTL_TOUCH_DREFH_S 6 /* RTC_CNTL_TOUCH_DREFL : R/W ;bitpos:[5:4] ;default: 2'b00 ; */ -/*description: TOUCH_DREFL.*/ -#define RTC_CNTL_TOUCH_DREFL 0x00000003 +/*description: TOUCH_DREFL*/ +#define RTC_CNTL_TOUCH_DREFL 0x00000003 #define RTC_CNTL_TOUCH_DREFL_M ((RTC_CNTL_TOUCH_DREFL_V)<<(RTC_CNTL_TOUCH_DREFL_S)) #define RTC_CNTL_TOUCH_DREFL_V 0x3 #define RTC_CNTL_TOUCH_DREFL_S 4 /* RTC_CNTL_TOUCH_DRANGE : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ -/*description: TOUCH_DRANGE.*/ -#define RTC_CNTL_TOUCH_DRANGE 0x00000003 +/*description: TOUCH_DRANGE*/ +#define RTC_CNTL_TOUCH_DRANGE 0x00000003 #define RTC_CNTL_TOUCH_DRANGE_M ((RTC_CNTL_TOUCH_DRANGE_V)<<(RTC_CNTL_TOUCH_DRANGE_S)) #define RTC_CNTL_TOUCH_DRANGE_V 0x3 #define RTC_CNTL_TOUCH_DRANGE_S 2 -#define RTC_CNTL_TOUCH_SCAN_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x10C) +#define RTC_CNTL_TOUCH_SCAN_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x010C) /* RTC_CNTL_TOUCH_OUT_RING : R/W ;bitpos:[31:28] ;default: 4'hf ; */ -/*description: select out ring pad.*/ -#define RTC_CNTL_TOUCH_OUT_RING 0x0000000F +/*description: select out ring pad*/ +#define RTC_CNTL_TOUCH_OUT_RING 0x0000000F #define RTC_CNTL_TOUCH_OUT_RING_M ((RTC_CNTL_TOUCH_OUT_RING_V)<<(RTC_CNTL_TOUCH_OUT_RING_S)) #define RTC_CNTL_TOUCH_OUT_RING_V 0xF #define RTC_CNTL_TOUCH_OUT_RING_S 28 /* RTC_CNTL_TOUCH_BUFDRV : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ -/*description: touch7 buffer driver strength.*/ -#define RTC_CNTL_TOUCH_BUFDRV 0x00000007 +/*description: touch7 buffer driver strength*/ +#define RTC_CNTL_TOUCH_BUFDRV 0x00000007 #define RTC_CNTL_TOUCH_BUFDRV_M ((RTC_CNTL_TOUCH_BUFDRV_V)<<(RTC_CNTL_TOUCH_BUFDRV_S)) #define RTC_CNTL_TOUCH_BUFDRV_V 0x7 #define RTC_CNTL_TOUCH_BUFDRV_S 25 /* RTC_CNTL_TOUCH_SCAN_PAD_MAP : R/W ;bitpos:[24:10] ;default: 15'h0 ; */ -/*description: touch scan mode pad enable map.*/ -#define RTC_CNTL_TOUCH_SCAN_PAD_MAP 0x00007FFF +/*description: touch scan mode pad enable map*/ +#define RTC_CNTL_TOUCH_SCAN_PAD_MAP 0x00007FFF #define RTC_CNTL_TOUCH_SCAN_PAD_MAP_M ((RTC_CNTL_TOUCH_SCAN_PAD_MAP_V)<<(RTC_CNTL_TOUCH_SCAN_PAD_MAP_S)) #define RTC_CNTL_TOUCH_SCAN_PAD_MAP_V 0x7FFF #define RTC_CNTL_TOUCH_SCAN_PAD_MAP_S 10 /* RTC_CNTL_TOUCH_SHIELD_PAD_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: touch pad14 will be used as shield.*/ -#define RTC_CNTL_TOUCH_SHIELD_PAD_EN (BIT(9)) +/*description: touch pad14 will be used as shield*/ +#define RTC_CNTL_TOUCH_SHIELD_PAD_EN (BIT(9)) #define RTC_CNTL_TOUCH_SHIELD_PAD_EN_M (BIT(9)) #define RTC_CNTL_TOUCH_SHIELD_PAD_EN_V 0x1 #define RTC_CNTL_TOUCH_SHIELD_PAD_EN_S 9 /* RTC_CNTL_TOUCH_INACTIVE_CONNECTION : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: inactive touch pads connect to 1: gnd 0: HighZ.*/ -#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION (BIT(8)) +/*description: inactive touch pads connect to 1: gnd 0: HighZ*/ +#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_M (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_V 0x1 #define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_S 8 /* RTC_CNTL_TOUCH_DENOISE_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: touch pad0 will be used to de-noise.*/ -#define RTC_CNTL_TOUCH_DENOISE_EN (BIT(2)) +/*description: touch pad0 will be used to de-noise*/ +#define RTC_CNTL_TOUCH_DENOISE_EN (BIT(2)) #define RTC_CNTL_TOUCH_DENOISE_EN_M (BIT(2)) #define RTC_CNTL_TOUCH_DENOISE_EN_V 0x1 #define RTC_CNTL_TOUCH_DENOISE_EN_S 2 /* RTC_CNTL_TOUCH_DENOISE_RES : R/W ;bitpos:[1:0] ;default: 2'd2 ; */ -/*description: De-noise resolution: 12/10/8/4 bit.*/ -#define RTC_CNTL_TOUCH_DENOISE_RES 0x00000003 +/*description: De-noise resolution: 12/10/8/4 bit*/ +#define RTC_CNTL_TOUCH_DENOISE_RES 0x00000003 #define RTC_CNTL_TOUCH_DENOISE_RES_M ((RTC_CNTL_TOUCH_DENOISE_RES_V)<<(RTC_CNTL_TOUCH_DENOISE_RES_S)) #define RTC_CNTL_TOUCH_DENOISE_RES_V 0x3 #define RTC_CNTL_TOUCH_DENOISE_RES_S 0 -#define RTC_CNTL_TOUCH_SLP_THRES_REG (DR_REG_RTCCNTL_BASE + 0x110) -/* RTC_CNTL_TOUCH_SLP_PAD : R/W ;bitpos:[31:27] ;default: 4'hf ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_SLP_PAD 0x0000001F +#define RTC_CNTL_TOUCH_SLP_THRES_REG (DR_REG_RTCCNTL_BASE + 0x0110) +/* RTC_CNTL_TOUCH_SLP_PAD : R/W ;bitpos:[31:27] ;default: 4'hF ; */ +/*description: */ +#define RTC_CNTL_TOUCH_SLP_PAD 0x0000001F #define RTC_CNTL_TOUCH_SLP_PAD_M ((RTC_CNTL_TOUCH_SLP_PAD_V)<<(RTC_CNTL_TOUCH_SLP_PAD_S)) #define RTC_CNTL_TOUCH_SLP_PAD_V 0x1F #define RTC_CNTL_TOUCH_SLP_PAD_S 27 /* RTC_CNTL_TOUCH_SLP_APPROACH_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: sleep pad approach function enable.*/ -#define RTC_CNTL_TOUCH_SLP_APPROACH_EN (BIT(26)) +/*description: sleep pad approach function enable*/ +#define RTC_CNTL_TOUCH_SLP_APPROACH_EN (BIT(26)) #define RTC_CNTL_TOUCH_SLP_APPROACH_EN_M (BIT(26)) #define RTC_CNTL_TOUCH_SLP_APPROACH_EN_V 0x1 #define RTC_CNTL_TOUCH_SLP_APPROACH_EN_S 26 /* RTC_CNTL_TOUCH_SLP_TH : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ -/*description: the threshold for sleep touch pad.*/ -#define RTC_CNTL_TOUCH_SLP_TH 0x003FFFFF +/*description: the threshold for sleep touch pad*/ +#define RTC_CNTL_TOUCH_SLP_TH 0x003FFFFF #define RTC_CNTL_TOUCH_SLP_TH_M ((RTC_CNTL_TOUCH_SLP_TH_V)<<(RTC_CNTL_TOUCH_SLP_TH_S)) #define RTC_CNTL_TOUCH_SLP_TH_V 0x3FFFFF #define RTC_CNTL_TOUCH_SLP_TH_S 0 -#define RTC_CNTL_TOUCH_APPROACH_REG (DR_REG_RTCCNTL_BASE + 0x114) +#define RTC_CNTL_TOUCH_APPROACH_REG (DR_REG_RTCCNTL_BASE + 0x0114) /* RTC_CNTL_TOUCH_APPROACH_MEAS_TIME : R/W ;bitpos:[31:24] ;default: 8'd80 ; */ -/*description: approach pads total meas times.*/ -#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME 0x000000FF +/*description: approach pads total meas times*/ +#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME 0x000000FF #define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_M ((RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V)<<(RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S)) #define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V 0xFF #define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S 24 /* RTC_CNTL_TOUCH_SLP_CHANNEL_CLR : WO ;bitpos:[23] ;default: 1'd0 ; */ -/*description: clear touch slp channel.*/ -#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR (BIT(23)) +/*description: clear touch slp channel*/ +#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR (BIT(23)) #define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_M (BIT(23)) #define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_V 0x1 #define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_S 23 -#define RTC_CNTL_TOUCH_FILTER_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x118) +#define RTC_CNTL_TOUCH_FILTER_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0118) /* RTC_CNTL_TOUCH_FILTER_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */ -/*description: touch filter enable.*/ -#define RTC_CNTL_TOUCH_FILTER_EN (BIT(31)) +/*description: touch filter enable*/ +#define RTC_CNTL_TOUCH_FILTER_EN (BIT(31)) #define RTC_CNTL_TOUCH_FILTER_EN_M (BIT(31)) #define RTC_CNTL_TOUCH_FILTER_EN_V 0x1 #define RTC_CNTL_TOUCH_FILTER_EN_S 31 /* RTC_CNTL_TOUCH_FILTER_MODE : R/W ;bitpos:[30:28] ;default: 3'd1 ; */ -/*description: 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter.*/ -#define RTC_CNTL_TOUCH_FILTER_MODE 0x00000007 +/*description: 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter*/ +#define RTC_CNTL_TOUCH_FILTER_MODE 0x00000007 #define RTC_CNTL_TOUCH_FILTER_MODE_M ((RTC_CNTL_TOUCH_FILTER_MODE_V)<<(RTC_CNTL_TOUCH_FILTER_MODE_S)) #define RTC_CNTL_TOUCH_FILTER_MODE_V 0x7 #define RTC_CNTL_TOUCH_FILTER_MODE_S 28 /* RTC_CNTL_TOUCH_DEBOUNCE : R/W ;bitpos:[27:25] ;default: 3'd3 ; */ -/*description: debounce counter.*/ -#define RTC_CNTL_TOUCH_DEBOUNCE 0x00000007 +/*description: debounce counter*/ +#define RTC_CNTL_TOUCH_DEBOUNCE 0x00000007 #define RTC_CNTL_TOUCH_DEBOUNCE_M ((RTC_CNTL_TOUCH_DEBOUNCE_V)<<(RTC_CNTL_TOUCH_DEBOUNCE_S)) #define RTC_CNTL_TOUCH_DEBOUNCE_V 0x7 #define RTC_CNTL_TOUCH_DEBOUNCE_S 25 /* RTC_CNTL_TOUCH_HYSTERESIS : R/W ;bitpos:[24:23] ;default: 2'd1 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_HYSTERESIS 0x00000003 +/*description: */ +#define RTC_CNTL_TOUCH_HYSTERESIS 0x00000003 #define RTC_CNTL_TOUCH_HYSTERESIS_M ((RTC_CNTL_TOUCH_HYSTERESIS_V)<<(RTC_CNTL_TOUCH_HYSTERESIS_S)) #define RTC_CNTL_TOUCH_HYSTERESIS_V 0x3 #define RTC_CNTL_TOUCH_HYSTERESIS_S 23 /* RTC_CNTL_TOUCH_NOISE_THRES : R/W ;bitpos:[22:21] ;default: 2'd1 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_NOISE_THRES 0x00000003 +/*description: */ +#define RTC_CNTL_TOUCH_NOISE_THRES 0x00000003 #define RTC_CNTL_TOUCH_NOISE_THRES_M ((RTC_CNTL_TOUCH_NOISE_THRES_V)<<(RTC_CNTL_TOUCH_NOISE_THRES_S)) #define RTC_CNTL_TOUCH_NOISE_THRES_V 0x3 #define RTC_CNTL_TOUCH_NOISE_THRES_S 21 /* RTC_CNTL_TOUCH_NEG_NOISE_THRES : R/W ;bitpos:[20:19] ;default: 2'd1 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_NEG_NOISE_THRES 0x00000003 +/*description: */ +#define RTC_CNTL_TOUCH_NEG_NOISE_THRES 0x00000003 #define RTC_CNTL_TOUCH_NEG_NOISE_THRES_M ((RTC_CNTL_TOUCH_NEG_NOISE_THRES_V)<<(RTC_CNTL_TOUCH_NEG_NOISE_THRES_S)) #define RTC_CNTL_TOUCH_NEG_NOISE_THRES_V 0x3 #define RTC_CNTL_TOUCH_NEG_NOISE_THRES_S 19 /* RTC_CNTL_TOUCH_NEG_NOISE_LIMIT : R/W ;bitpos:[18:15] ;default: 4'd5 ; */ -/*description: negative threshold counter limit.*/ -#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT 0x0000000F +/*description: negative threshold counter limit*/ +#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT 0x0000000F #define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_M ((RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_V)<<(RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_S)) #define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_V 0xF #define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_S 15 /* RTC_CNTL_TOUCH_JITTER_STEP : R/W ;bitpos:[14:11] ;default: 4'd1 ; */ -/*description: touch jitter step.*/ -#define RTC_CNTL_TOUCH_JITTER_STEP 0x0000000F +/*description: touch jitter step*/ +#define RTC_CNTL_TOUCH_JITTER_STEP 0x0000000F #define RTC_CNTL_TOUCH_JITTER_STEP_M ((RTC_CNTL_TOUCH_JITTER_STEP_V)<<(RTC_CNTL_TOUCH_JITTER_STEP_S)) #define RTC_CNTL_TOUCH_JITTER_STEP_V 0xF #define RTC_CNTL_TOUCH_JITTER_STEP_S 11 /* RTC_CNTL_TOUCH_SMOOTH_LVL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_SMOOTH_LVL 0x00000003 +/*description: */ +#define RTC_CNTL_TOUCH_SMOOTH_LVL 0x00000003 #define RTC_CNTL_TOUCH_SMOOTH_LVL_M ((RTC_CNTL_TOUCH_SMOOTH_LVL_V)<<(RTC_CNTL_TOUCH_SMOOTH_LVL_S)) #define RTC_CNTL_TOUCH_SMOOTH_LVL_V 0x3 #define RTC_CNTL_TOUCH_SMOOTH_LVL_S 9 /* RTC_CNTL_TOUCH_BYPASS_NOISE_THRES : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES (BIT(8)) +/*description: */ +#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES (BIT(8)) #define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_M (BIT(8)) #define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_V 0x1 #define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_S 8 /* RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES (BIT(7)) +/*description: */ +#define RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES (BIT(7)) #define RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES_M (BIT(7)) #define RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES_V 0x1 #define RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES_S 7 -#define RTC_CNTL_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x11C) +#define RTC_CNTL_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x011C) /* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W ;bitpos:[18] ;default: 1'd0 ; */ -/*description: .*/ -#define RTC_CNTL_IO_MUX_RESET_DISABLE (BIT(18)) +/*description: */ +#define RTC_CNTL_IO_MUX_RESET_DISABLE (BIT(18)) #define RTC_CNTL_IO_MUX_RESET_DISABLE_M (BIT(18)) #define RTC_CNTL_IO_MUX_RESET_DISABLE_V 0x1 #define RTC_CNTL_IO_MUX_RESET_DISABLE_S 18 /* RTC_CNTL_USB_RESET_DISABLE : R/W ;bitpos:[17] ;default: 1'd0 ; */ -/*description: .*/ -#define RTC_CNTL_USB_RESET_DISABLE (BIT(17)) +/*description: */ +#define RTC_CNTL_USB_RESET_DISABLE (BIT(17)) #define RTC_CNTL_USB_RESET_DISABLE_M (BIT(17)) #define RTC_CNTL_USB_RESET_DISABLE_V 0x1 #define RTC_CNTL_USB_RESET_DISABLE_S 17 /* RTC_CNTL_USB_TX_EN_OVERRIDE : R/W ;bitpos:[16] ;default: 1'd0 ; */ -/*description: .*/ -#define RTC_CNTL_USB_TX_EN_OVERRIDE (BIT(16)) +/*description: */ +#define RTC_CNTL_USB_TX_EN_OVERRIDE (BIT(16)) #define RTC_CNTL_USB_TX_EN_OVERRIDE_M (BIT(16)) #define RTC_CNTL_USB_TX_EN_OVERRIDE_V 0x1 #define RTC_CNTL_USB_TX_EN_OVERRIDE_S 16 /* RTC_CNTL_USB_TX_EN : R/W ;bitpos:[15] ;default: 1'd0 ; */ -/*description: .*/ -#define RTC_CNTL_USB_TX_EN (BIT(15)) +/*description: */ +#define RTC_CNTL_USB_TX_EN (BIT(15)) #define RTC_CNTL_USB_TX_EN_M (BIT(15)) #define RTC_CNTL_USB_TX_EN_V 0x1 #define RTC_CNTL_USB_TX_EN_S 15 /* RTC_CNTL_USB_TXP : R/W ;bitpos:[14] ;default: 1'd0 ; */ -/*description: .*/ -#define RTC_CNTL_USB_TXP (BIT(14)) +/*description: */ +#define RTC_CNTL_USB_TXP (BIT(14)) #define RTC_CNTL_USB_TXP_M (BIT(14)) #define RTC_CNTL_USB_TXP_V 0x1 #define RTC_CNTL_USB_TXP_S 14 /* RTC_CNTL_USB_TXM : R/W ;bitpos:[13] ;default: 1'd0 ; */ -/*description: .*/ -#define RTC_CNTL_USB_TXM (BIT(13)) +/*description: */ +#define RTC_CNTL_USB_TXM (BIT(13)) #define RTC_CNTL_USB_TXM_M (BIT(13)) #define RTC_CNTL_USB_TXM_V 0x1 #define RTC_CNTL_USB_TXM_S 13 /* RTC_CNTL_USB_PAD_ENABLE : R/W ;bitpos:[12] ;default: 1'd0 ; */ -/*description: .*/ -#define RTC_CNTL_USB_PAD_ENABLE (BIT(12)) +/*description: */ +#define RTC_CNTL_USB_PAD_ENABLE (BIT(12)) #define RTC_CNTL_USB_PAD_ENABLE_M (BIT(12)) #define RTC_CNTL_USB_PAD_ENABLE_V 0x1 #define RTC_CNTL_USB_PAD_ENABLE_S 12 /* RTC_CNTL_USB_PAD_ENABLE_OVERRIDE : R/W ;bitpos:[11] ;default: 1'd0 ; */ -/*description: .*/ -#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE (BIT(11)) +/*description: */ +#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE (BIT(11)) #define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_M (BIT(11)) #define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_V 0x1 #define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_S 11 /* RTC_CNTL_USB_PULLUP_VALUE : R/W ;bitpos:[10] ;default: 1'd0 ; */ -/*description: .*/ -#define RTC_CNTL_USB_PULLUP_VALUE (BIT(10)) +/*description: */ +#define RTC_CNTL_USB_PULLUP_VALUE (BIT(10)) #define RTC_CNTL_USB_PULLUP_VALUE_M (BIT(10)) #define RTC_CNTL_USB_PULLUP_VALUE_V 0x1 #define RTC_CNTL_USB_PULLUP_VALUE_S 10 /* RTC_CNTL_USB_DM_PULLDOWN : R/W ;bitpos:[9] ;default: 1'd0 ; */ -/*description: .*/ -#define RTC_CNTL_USB_DM_PULLDOWN (BIT(9)) +/*description: */ +#define RTC_CNTL_USB_DM_PULLDOWN (BIT(9)) #define RTC_CNTL_USB_DM_PULLDOWN_M (BIT(9)) #define RTC_CNTL_USB_DM_PULLDOWN_V 0x1 #define RTC_CNTL_USB_DM_PULLDOWN_S 9 /* RTC_CNTL_USB_DM_PULLUP : R/W ;bitpos:[8] ;default: 1'd0 ; */ -/*description: .*/ -#define RTC_CNTL_USB_DM_PULLUP (BIT(8)) +/*description: */ +#define RTC_CNTL_USB_DM_PULLUP (BIT(8)) #define RTC_CNTL_USB_DM_PULLUP_M (BIT(8)) #define RTC_CNTL_USB_DM_PULLUP_V 0x1 #define RTC_CNTL_USB_DM_PULLUP_S 8 /* RTC_CNTL_USB_DP_PULLDOWN : R/W ;bitpos:[7] ;default: 1'd0 ; */ -/*description: .*/ -#define RTC_CNTL_USB_DP_PULLDOWN (BIT(7)) +/*description: */ +#define RTC_CNTL_USB_DP_PULLDOWN (BIT(7)) #define RTC_CNTL_USB_DP_PULLDOWN_M (BIT(7)) #define RTC_CNTL_USB_DP_PULLDOWN_V 0x1 #define RTC_CNTL_USB_DP_PULLDOWN_S 7 /* RTC_CNTL_USB_DP_PULLUP : R/W ;bitpos:[6] ;default: 1'd0 ; */ -/*description: .*/ -#define RTC_CNTL_USB_DP_PULLUP (BIT(6)) +/*description: */ +#define RTC_CNTL_USB_DP_PULLUP (BIT(6)) #define RTC_CNTL_USB_DP_PULLUP_M (BIT(6)) #define RTC_CNTL_USB_DP_PULLUP_V 0x1 #define RTC_CNTL_USB_DP_PULLUP_S 6 /* RTC_CNTL_USB_PAD_PULL_OVERRIDE : R/W ;bitpos:[5] ;default: 1'd0 ; */ -/*description: .*/ -#define RTC_CNTL_USB_PAD_PULL_OVERRIDE (BIT(5)) +/*description: */ +#define RTC_CNTL_USB_PAD_PULL_OVERRIDE (BIT(5)) #define RTC_CNTL_USB_PAD_PULL_OVERRIDE_M (BIT(5)) #define RTC_CNTL_USB_PAD_PULL_OVERRIDE_V 0x1 #define RTC_CNTL_USB_PAD_PULL_OVERRIDE_S 5 /* RTC_CNTL_USB_VREF_OVERRIDE : R/W ;bitpos:[4] ;default: 1'd0 ; */ -/*description: .*/ -#define RTC_CNTL_USB_VREF_OVERRIDE (BIT(4)) +/*description: */ +#define RTC_CNTL_USB_VREF_OVERRIDE (BIT(4)) #define RTC_CNTL_USB_VREF_OVERRIDE_M (BIT(4)) #define RTC_CNTL_USB_VREF_OVERRIDE_V 0x1 #define RTC_CNTL_USB_VREF_OVERRIDE_S 4 /* RTC_CNTL_USB_VREFL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ -/*description: .*/ -#define RTC_CNTL_USB_VREFL 0x00000003 +/*description: */ +#define RTC_CNTL_USB_VREFL 0x00000003 #define RTC_CNTL_USB_VREFL_M ((RTC_CNTL_USB_VREFL_V)<<(RTC_CNTL_USB_VREFL_S)) #define RTC_CNTL_USB_VREFL_V 0x3 #define RTC_CNTL_USB_VREFL_S 2 /* RTC_CNTL_USB_VREFH : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ -/*description: .*/ -#define RTC_CNTL_USB_VREFH 0x00000003 +/*description: */ +#define RTC_CNTL_USB_VREFH 0x00000003 #define RTC_CNTL_USB_VREFH_M ((RTC_CNTL_USB_VREFH_V)<<(RTC_CNTL_USB_VREFH_S)) #define RTC_CNTL_USB_VREFH_V 0x3 #define RTC_CNTL_USB_VREFH_S 0 -#define RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x120) +#define RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0120) /* RTC_CNTL_TOUCH_TIMEOUT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_TIMEOUT_EN (BIT(22)) +/*description: */ +#define RTC_CNTL_TOUCH_TIMEOUT_EN (BIT(22)) #define RTC_CNTL_TOUCH_TIMEOUT_EN_M (BIT(22)) #define RTC_CNTL_TOUCH_TIMEOUT_EN_V 0x1 #define RTC_CNTL_TOUCH_TIMEOUT_EN_S 22 /* RTC_CNTL_TOUCH_TIMEOUT_NUM : R/W ;bitpos:[21:0] ;default: 22'h3fffff ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_TIMEOUT_NUM 0x003FFFFF +/*description: */ +#define RTC_CNTL_TOUCH_TIMEOUT_NUM 0x003FFFFF #define RTC_CNTL_TOUCH_TIMEOUT_NUM_M ((RTC_CNTL_TOUCH_TIMEOUT_NUM_V)<<(RTC_CNTL_TOUCH_TIMEOUT_NUM_S)) #define RTC_CNTL_TOUCH_TIMEOUT_NUM_V 0x3FFFFF #define RTC_CNTL_TOUCH_TIMEOUT_NUM_S 0 -#define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x124) +#define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x0124) /* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[17:0] ;default: 18'd0 ; */ -/*description: sleep reject cause.*/ -#define RTC_CNTL_REJECT_CAUSE 0x0003FFFF +/*description: sleep reject cause*/ +#define RTC_CNTL_REJECT_CAUSE 0x0003FFFF #define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S)) #define RTC_CNTL_REJECT_CAUSE_V 0x3FFFF #define RTC_CNTL_REJECT_CAUSE_S 0 -#define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x128) +#define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x0128) /* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: .*/ -#define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0)) +/*description: */ +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0)) #define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M (BIT(0)) #define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V 0x1 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S 0 -#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x12C) +#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x012C) /* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[16:0] ;default: 17'd0 ; */ -/*description: sleep wakeup cause.*/ -#define RTC_CNTL_WAKEUP_CAUSE 0x0001FFFF +/*description: sleep wakeup cause*/ +#define RTC_CNTL_WAKEUP_CAUSE 0x0001FFFF #define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) #define RTC_CNTL_WAKEUP_CAUSE_V 0x1FFFF #define RTC_CNTL_WAKEUP_CAUSE_S 0 -#define RTC_CNTL_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x130) +#define RTC_CNTL_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x0130) /* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W ;bitpos:[31:8] ;default: 24'd200 ; */ -/*description: sleep cycles for ULP-coprocessor timer.*/ -#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00FFFFFF +/*description: sleep cycles for ULP-coprocessor timer*/ +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00FFFFFF #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S)) #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V 0xFFFFFF #define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S 8 -#define RTC_CNTL_INT_ENA_RTC_W1TS_REG (DR_REG_RTCCNTL_BASE + 0x134) +#define RTC_CNTL_INT_ENA_W1TS_REG (DR_REG_RTCCNTL_BASE + 0x0134) /* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS (BIT(20)) +/*description: */ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS (BIT(20)) #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_M (BIT(20)) #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_S 20 /* RTC_CNTL_GLITCH_DET_INT_ENA_W1TS : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: enbale gitch det interrupt.*/ -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS (BIT(19)) +/*description: enbale gitch det interrupt*/ +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_M (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_S 19 /* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS : WO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: enable touch timeout interrupt.*/ -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS (BIT(18)) +/*description: enable touch timeout interrupt*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS (BIT(18)) #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_M (BIT(18)) #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_S 18 /* RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: enable cocpu trap interrupt.*/ -#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS (BIT(17)) +/*description: enable cocpu trap interrupt*/ +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS (BIT(17)) #define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_M (BIT(17)) #define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_S 17 /* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: enable xtal32k_dead interrupt.*/ -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS (BIT(16)) +/*description: enable xtal32k_dead interrupt*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS (BIT(16)) #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_M (BIT(16)) #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_S 16 /* RTC_CNTL_SWD_INT_ENA_W1TS : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: enable super watch dog interrupt.*/ -#define RTC_CNTL_SWD_INT_ENA_W1TS (BIT(15)) +/*description: enable super watch dog interrupt*/ +#define RTC_CNTL_SWD_INT_ENA_W1TS (BIT(15)) #define RTC_CNTL_SWD_INT_ENA_W1TS_M (BIT(15)) #define RTC_CNTL_SWD_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_SWD_INT_ENA_W1TS_S 15 /* RTC_CNTL_SARADC2_INT_ENA_W1TS : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: enable saradc2 interrupt.*/ -#define RTC_CNTL_SARADC2_INT_ENA_W1TS (BIT(14)) +/*description: enable saradc2 interrupt*/ +#define RTC_CNTL_SARADC2_INT_ENA_W1TS (BIT(14)) #define RTC_CNTL_SARADC2_INT_ENA_W1TS_M (BIT(14)) #define RTC_CNTL_SARADC2_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_SARADC2_INT_ENA_W1TS_S 14 /* RTC_CNTL_COCPU_INT_ENA_W1TS : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: enable riscV cocpu interrupt.*/ -#define RTC_CNTL_COCPU_INT_ENA_W1TS (BIT(13)) +/*description: enable riscV cocpu interrupt*/ +#define RTC_CNTL_COCPU_INT_ENA_W1TS (BIT(13)) #define RTC_CNTL_COCPU_INT_ENA_W1TS_M (BIT(13)) #define RTC_CNTL_COCPU_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_COCPU_INT_ENA_W1TS_S 13 /* RTC_CNTL_TSENS_INT_ENA_W1TS : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: enable tsens interrupt.*/ -#define RTC_CNTL_TSENS_INT_ENA_W1TS (BIT(12)) +/*description: enable tsens interrupt*/ +#define RTC_CNTL_TSENS_INT_ENA_W1TS (BIT(12)) #define RTC_CNTL_TSENS_INT_ENA_W1TS_M (BIT(12)) #define RTC_CNTL_TSENS_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_TSENS_INT_ENA_W1TS_S 12 /* RTC_CNTL_SARADC1_INT_ENA_W1TS : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: enable saradc1 interrupt.*/ -#define RTC_CNTL_SARADC1_INT_ENA_W1TS (BIT(11)) +/*description: enable saradc1 interrupt*/ +#define RTC_CNTL_SARADC1_INT_ENA_W1TS (BIT(11)) #define RTC_CNTL_SARADC1_INT_ENA_W1TS_M (BIT(11)) #define RTC_CNTL_SARADC1_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_SARADC1_INT_ENA_W1TS_S 11 /* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: enable RTC main timer interrupt.*/ -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS (BIT(10)) +/*description: enable RTC main timer interrupt*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS (BIT(10)) #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_M (BIT(10)) #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S 10 /* RTC_CNTL_BROWN_OUT_INT_ENA_W1TS : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: enable brown out interrupt.*/ -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS (BIT(9)) +/*description: enable brown out interrupt*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS (BIT(9)) #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_M (BIT(9)) #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S 9 /* RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: enable touch inactive interrupt.*/ -#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS (BIT(8)) +/*description: enable touch inactive interrupt*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_M (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_S 8 /* RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: enable touch active interrupt.*/ -#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS (BIT(7)) +/*description: enable touch active interrupt*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS (BIT(7)) #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_M (BIT(7)) #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_S 7 /* RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: enable touch done interrupt.*/ -#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS (BIT(6)) +/*description: enable touch done interrupt*/ +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS (BIT(6)) #define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_M (BIT(6)) #define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_S 6 /* RTC_CNTL_ULP_CP_INT_ENA_W1TS : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: enable ULP-coprocessor interrupt.*/ -#define RTC_CNTL_ULP_CP_INT_ENA_W1TS (BIT(5)) +/*description: enable ULP-coprocessor interrupt*/ +#define RTC_CNTL_ULP_CP_INT_ENA_W1TS (BIT(5)) #define RTC_CNTL_ULP_CP_INT_ENA_W1TS_M (BIT(5)) #define RTC_CNTL_ULP_CP_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_ULP_CP_INT_ENA_W1TS_S 5 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: enable touch scan done interrupt.*/ -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS (BIT(4)) +/*description: enable touch scan done interrupt*/ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS (BIT(4)) #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_M (BIT(4)) #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_S 4 /* RTC_CNTL_WDT_INT_ENA_W1TS : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: enable RTC WDT interrupt.*/ -#define RTC_CNTL_WDT_INT_ENA_W1TS (BIT(3)) +/*description: enable RTC WDT interrupt*/ +#define RTC_CNTL_WDT_INT_ENA_W1TS (BIT(3)) #define RTC_CNTL_WDT_INT_ENA_W1TS_M (BIT(3)) #define RTC_CNTL_WDT_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_WDT_INT_ENA_W1TS_S 3 /* RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: enable SDIO idle interrupt.*/ -#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS (BIT(2)) +/*description: enable SDIO idle interrupt*/ +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS (BIT(2)) #define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_M (BIT(2)) #define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_S 2 /* RTC_CNTL_SLP_REJECT_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: enable sleep reject interrupt.*/ -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS (BIT(1)) +/*description: enable sleep reject interrupt*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS (BIT(1)) #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_M (BIT(1)) #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S 1 /* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: enable sleep wakeup interrupt.*/ -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS (BIT(0)) +/*description: enable sleep wakeup interrupt*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS (BIT(0)) #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M (BIT(0)) #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V 0x1 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S 0 -#define RTC_CNTL_INT_ENA_RTC_W1TC_REG (DR_REG_RTCCNTL_BASE + 0x138) +#define RTC_CNTL_INT_ENA_W1TC_REG (DR_REG_RTCCNTL_BASE + 0x0138) /* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC : WO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC (BIT(20)) +/*description: */ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC (BIT(20)) #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_M (BIT(20)) #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_S 20 /* RTC_CNTL_GLITCH_DET_INT_ENA_W1TC : WO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: enbale gitch det interrupt.*/ -#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC (BIT(19)) +/*description: enbale gitch det interrupt*/ +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_M (BIT(19)) #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_S 19 /* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC : WO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: enable touch timeout interrupt.*/ -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC (BIT(18)) +/*description: enable touch timeout interrupt*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC (BIT(18)) #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_M (BIT(18)) #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_S 18 /* RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC : WO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: enable cocpu trap interrupt.*/ -#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC (BIT(17)) +/*description: enable cocpu trap interrupt*/ +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC (BIT(17)) #define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_M (BIT(17)) #define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_S 17 /* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC : WO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: enable xtal32k_dead interrupt.*/ -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC (BIT(16)) +/*description: enable xtal32k_dead interrupt*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC (BIT(16)) #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_M (BIT(16)) #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_S 16 /* RTC_CNTL_SWD_INT_ENA_W1TC : WO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: enable super watch dog interrupt.*/ -#define RTC_CNTL_SWD_INT_ENA_W1TC (BIT(15)) +/*description: enable super watch dog interrupt*/ +#define RTC_CNTL_SWD_INT_ENA_W1TC (BIT(15)) #define RTC_CNTL_SWD_INT_ENA_W1TC_M (BIT(15)) #define RTC_CNTL_SWD_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_SWD_INT_ENA_W1TC_S 15 /* RTC_CNTL_SARADC2_INT_ENA_W1TC : WO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: enable saradc2 interrupt.*/ -#define RTC_CNTL_SARADC2_INT_ENA_W1TC (BIT(14)) +/*description: enable saradc2 interrupt*/ +#define RTC_CNTL_SARADC2_INT_ENA_W1TC (BIT(14)) #define RTC_CNTL_SARADC2_INT_ENA_W1TC_M (BIT(14)) #define RTC_CNTL_SARADC2_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_SARADC2_INT_ENA_W1TC_S 14 /* RTC_CNTL_COCPU_INT_ENA_W1TC : WO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: enable riscV cocpu interrupt.*/ -#define RTC_CNTL_COCPU_INT_ENA_W1TC (BIT(13)) +/*description: enable riscV cocpu interrupt*/ +#define RTC_CNTL_COCPU_INT_ENA_W1TC (BIT(13)) #define RTC_CNTL_COCPU_INT_ENA_W1TC_M (BIT(13)) #define RTC_CNTL_COCPU_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_COCPU_INT_ENA_W1TC_S 13 /* RTC_CNTL_TSENS_INT_ENA_W1TC : WO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: enable tsens interrupt.*/ -#define RTC_CNTL_TSENS_INT_ENA_W1TC (BIT(12)) +/*description: enable tsens interrupt*/ +#define RTC_CNTL_TSENS_INT_ENA_W1TC (BIT(12)) #define RTC_CNTL_TSENS_INT_ENA_W1TC_M (BIT(12)) #define RTC_CNTL_TSENS_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_TSENS_INT_ENA_W1TC_S 12 /* RTC_CNTL_SARADC1_INT_ENA_W1TC : WO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: enable saradc1 interrupt.*/ -#define RTC_CNTL_SARADC1_INT_ENA_W1TC (BIT(11)) +/*description: enable saradc1 interrupt*/ +#define RTC_CNTL_SARADC1_INT_ENA_W1TC (BIT(11)) #define RTC_CNTL_SARADC1_INT_ENA_W1TC_M (BIT(11)) #define RTC_CNTL_SARADC1_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_SARADC1_INT_ENA_W1TC_S 11 /* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC : WO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: enable RTC main timer interrupt.*/ -#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC (BIT(10)) +/*description: enable RTC main timer interrupt*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC (BIT(10)) #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_M (BIT(10)) #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S 10 /* RTC_CNTL_BROWN_OUT_INT_ENA_W1TC : WO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: enable brown out interrupt.*/ -#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC (BIT(9)) +/*description: enable brown out interrupt*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC (BIT(9)) #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_M (BIT(9)) #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S 9 /* RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: enable touch inactive interrupt.*/ -#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC (BIT(8)) +/*description: enable touch inactive interrupt*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_M (BIT(8)) #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_S 8 /* RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: enable touch active interrupt.*/ -#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC (BIT(7)) +/*description: enable touch active interrupt*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC (BIT(7)) #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_M (BIT(7)) #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_S 7 /* RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: enable touch done interrupt.*/ -#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC (BIT(6)) +/*description: enable touch done interrupt*/ +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC (BIT(6)) #define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_M (BIT(6)) #define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_S 6 /* RTC_CNTL_ULP_CP_INT_ENA_W1TC : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: enable ULP-coprocessor interrupt.*/ -#define RTC_CNTL_ULP_CP_INT_ENA_W1TC (BIT(5)) +/*description: enable ULP-coprocessor interrupt*/ +#define RTC_CNTL_ULP_CP_INT_ENA_W1TC (BIT(5)) #define RTC_CNTL_ULP_CP_INT_ENA_W1TC_M (BIT(5)) #define RTC_CNTL_ULP_CP_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_ULP_CP_INT_ENA_W1TC_S 5 /* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: enable touch scan done interrupt.*/ -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC (BIT(4)) +/*description: enable touch scan done interrupt*/ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC (BIT(4)) #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_M (BIT(4)) #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_S 4 /* RTC_CNTL_WDT_INT_ENA_W1TC : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: enable RTC WDT interrupt.*/ -#define RTC_CNTL_WDT_INT_ENA_W1TC (BIT(3)) +/*description: enable RTC WDT interrupt*/ +#define RTC_CNTL_WDT_INT_ENA_W1TC (BIT(3)) #define RTC_CNTL_WDT_INT_ENA_W1TC_M (BIT(3)) #define RTC_CNTL_WDT_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_WDT_INT_ENA_W1TC_S 3 /* RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: enable SDIO idle interrupt.*/ -#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC (BIT(2)) +/*description: enable SDIO idle interrupt*/ +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC (BIT(2)) #define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_M (BIT(2)) #define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_S 2 /* RTC_CNTL_SLP_REJECT_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: enable sleep reject interrupt.*/ -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC (BIT(1)) +/*description: enable sleep reject interrupt*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC (BIT(1)) #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M (BIT(1)) #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S 1 /* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: enable sleep wakeup interrupt.*/ -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC (BIT(0)) +/*description: enable sleep wakeup interrupt*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC (BIT(0)) #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_M (BIT(0)) #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V 0x1 #define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S 0 -#define RTC_CNTL_RETENTION_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x13C) +#define RTC_CNTL_RETENTION_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x013c) /* RTC_CNTL_RETENTION_WAIT : R/W ;bitpos:[31:27] ;default: 5'd20 ; */ -/*description: wait cycles for rention operation.*/ -#define RTC_CNTL_RETENTION_WAIT 0x0000001F +/*description: wait cycles for rention operation*/ +#define RTC_CNTL_RETENTION_WAIT 0x0000001F #define RTC_CNTL_RETENTION_WAIT_M ((RTC_CNTL_RETENTION_WAIT_V)<<(RTC_CNTL_RETENTION_WAIT_S)) #define RTC_CNTL_RETENTION_WAIT_V 0x1F #define RTC_CNTL_RETENTION_WAIT_S 27 /* RTC_CNTL_RETENTION_EN : R/W ;bitpos:[26] ;default: 1'd0 ; */ -/*description: .*/ -#define RTC_CNTL_RETENTION_EN (BIT(26)) +/*description: */ +#define RTC_CNTL_RETENTION_EN (BIT(26)) #define RTC_CNTL_RETENTION_EN_M (BIT(26)) #define RTC_CNTL_RETENTION_EN_V 0x1 #define RTC_CNTL_RETENTION_EN_S 26 +/* RTC_CNTL_RETENTION_CLKOFF_WAIT : R/W ;bitpos:[25:22] ;default: 4'd3 ; */ +/*description: */ +#define RTC_CNTL_RETENTION_CLKOFF_WAIT 0x0000000F +#define RTC_CNTL_RETENTION_CLKOFF_WAIT_M ((RTC_CNTL_RETENTION_CLKOFF_WAIT_V)<<(RTC_CNTL_RETENTION_CLKOFF_WAIT_S)) +#define RTC_CNTL_RETENTION_CLKOFF_WAIT_V 0xF +#define RTC_CNTL_RETENTION_CLKOFF_WAIT_S 22 +/* RTC_CNTL_RETENTION_DONE_WAIT : R/W ;bitpos:[21:19] ;default: 3'd2 ; */ +/*description: */ +#define RTC_CNTL_RETENTION_DONE_WAIT 0x00000007 +#define RTC_CNTL_RETENTION_DONE_WAIT_M ((RTC_CNTL_RETENTION_DONE_WAIT_V)<<(RTC_CNTL_RETENTION_DONE_WAIT_S)) +#define RTC_CNTL_RETENTION_DONE_WAIT_V 0x7 +#define RTC_CNTL_RETENTION_DONE_WAIT_S 19 +/* RTC_CNTL_RETENTION_CLK_SEL : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_RETENTION_CLK_SEL (BIT(18)) +#define RTC_CNTL_RETENTION_CLK_SEL_M (BIT(18)) +#define RTC_CNTL_RETENTION_CLK_SEL_V 0x1 +#define RTC_CNTL_RETENTION_CLK_SEL_S 18 -#define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x140) +#define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x0140) /* RTC_CNTL_FIB_SEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ -/*description: select use analog fib signal.*/ -#define RTC_CNTL_FIB_SEL 0x00000007 +/*description: select use analog fib signal*/ +#define RTC_CNTL_FIB_SEL 0x00000007 #define RTC_CNTL_FIB_SEL_M ((RTC_CNTL_FIB_SEL_V)<<(RTC_CNTL_FIB_SEL_S)) #define RTC_CNTL_FIB_SEL_V 0x7 #define RTC_CNTL_FIB_SEL_S 0 -#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x144) -/* RTC_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003251 ; */ -/*description: .*/ -#define RTC_CNTL_DATE 0x0FFFFFFF -#define RTC_CNTL_DATE_M ((RTC_CNTL_DATE_V)<<(RTC_CNTL_DATE_S)) -#define RTC_CNTL_DATE_V 0xFFFFFFF -#define RTC_CNTL_DATE_S 0 - +#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x0144) +/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2010090 ; */ +/*description: */ +#define RTC_CNTL_CNTL_DATE 0x0FFFFFFF +#define RTC_CNTL_CNTL_DATE_M ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S)) +#define RTC_CNTL_CNTL_DATE_V 0xFFFFFFF +#define RTC_CNTL_CNTL_DATE_S 0 #ifdef __cplusplus } diff --git a/components/soc/esp32s3/include/soc/rtc_cntl_struct.h b/components/soc/esp32s3/include/soc/rtc_cntl_struct.h index a9408be766..e2fe8b0a18 100644 --- a/components/soc/esp32s3/include/soc/rtc_cntl_struct.h +++ b/components/soc/esp32s3/include/soc/rtc_cntl_struct.h @@ -13,949 +13,931 @@ // limitations under the License. #ifndef _SOC_RTC_CNTL_STRUCT_H_ #define _SOC_RTC_CNTL_STRUCT_H_ - - #ifdef __cplusplus extern "C" { #endif -#include "soc.h" typedef volatile struct { union { struct { - uint32_t sw_stall_appcpu_c0 : 2; /*{reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/ - uint32_t sw_stall_procpu_c0 : 2; /*{reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/ - uint32_t sw_appcpu_rst : 1; /*APP CPU SW reset*/ - uint32_t sw_procpu_rst : 1; /*PRO CPU SW reset*/ - uint32_t bb_i2c_force_pd : 1; /*BB_I2C force power down*/ - uint32_t bb_i2c_force_pu : 1; /*BB_I2C force power up*/ - uint32_t bbpll_i2c_force_pd : 1; /*BB_PLL _I2C force power down*/ - uint32_t bbpll_i2c_force_pu : 1; /*BB_PLL_I2C force power up*/ - uint32_t bbpll_force_pd : 1; /*BB_PLL force power down*/ - uint32_t bbpll_force_pu : 1; /*BB_PLL force power up*/ - uint32_t xtl_force_pd : 1; /*crystall force power down*/ - uint32_t xtl_force_pu : 1; /*crystall force power up*/ - uint32_t xtl_en_wait : 4; /*wait bias_sleep and current source wakeup*/ - uint32_t reserved18 : 5; - uint32_t xtl_force_iso : 1; - uint32_t pll_force_iso : 1; - uint32_t analog_force_iso : 1; - uint32_t xtl_force_noiso : 1; - uint32_t pll_force_noiso : 1; - uint32_t analog_force_noiso : 1; - uint32_t dg_wrap_force_rst : 1; /*digital wrap force reset in deep sleep*/ - uint32_t dg_wrap_force_norst : 1; /*digital core force no reset in deep sleep*/ - uint32_t sw_sys_rst : 1; /*SW system reset*/ + uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/ + uint32_t sw_stall_procpu_c0: 2; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/ + uint32_t sw_appcpu_rst: 1; /*APP CPU SW reset*/ + uint32_t sw_procpu_rst: 1; /*PRO CPU SW reset*/ + uint32_t bb_i2c_force_pd: 1; /*BB_I2C force power down*/ + uint32_t bb_i2c_force_pu: 1; /*BB_I2C force power up*/ + uint32_t bbpll_i2c_force_pd: 1; /*BB_PLL _I2C force power down*/ + uint32_t bbpll_i2c_force_pu: 1; /*BB_PLL_I2C force power up*/ + uint32_t bbpll_force_pd: 1; /*BB_PLL force power down*/ + uint32_t bbpll_force_pu: 1; /*BB_PLL force power up*/ + uint32_t xtl_force_pd: 1; /*crystall force power down*/ + uint32_t xtl_force_pu: 1; /*crystall force power up*/ + uint32_t xtl_en_wait: 4; /*wait bias_sleep and current source wakeup*/ + uint32_t reserved18: 5; + uint32_t xtl_force_iso: 1; + uint32_t pll_force_iso: 1; + uint32_t analog_force_iso: 1; + uint32_t xtl_force_noiso: 1; + uint32_t pll_force_noiso: 1; + uint32_t analog_force_noiso: 1; + uint32_t dg_wrap_force_rst: 1; /*digital wrap force reset in deep sleep*/ + uint32_t dg_wrap_force_norst: 1; /*digital core force no reset in deep sleep*/ + uint32_t sw_sys_rst: 1; /*SW system reset*/ }; uint32_t val; } options0; - uint32_t slp_timer0; + uint32_t slp_timer0; /**/ union { struct { - uint32_t slp_val_hi : 16; /*RTC sleep timer high 16 bits*/ - uint32_t main_timer_alarm_en : 1; /*timer alarm enable bit*/ - uint32_t reserved17 : 15; + uint32_t slp_val_hi: 16; /*RTC sleep timer high 16 bits*/ + uint32_t main_timer_alarm_en: 1; /*timer alarm enable bit*/ + uint32_t reserved17: 15; }; uint32_t val; } slp_timer1; union { struct { - uint32_t reserved0 : 27; - uint32_t timer_sys_stall : 1; /*Enable to record system stall time*/ - uint32_t timer_xtl_off : 1; /*Enable to record 40M XTAL OFF time*/ - uint32_t timer_sys_rst : 1; /*enable to record system reset time*/ - uint32_t reserved30 : 1; - uint32_t update : 1; /*Set 1: to update register with RTC timer*/ + uint32_t reserved0: 27; + uint32_t timer_sys_stall: 1; /*Enable to record system stall time*/ + uint32_t timer_xtl_off: 1; /*Enable to record 40M XTAL OFF time*/ + uint32_t timer_sys_rst: 1; /*enable to record system reset time*/ + uint32_t reserved30: 1; + uint32_t update: 1; /*Set 1: to update register with RTC timer*/ }; uint32_t val; } time_update; - uint32_t time_low0; + uint32_t time_low0; /*RTC timer low 32 bits*/ union { struct { - uint32_t rtc_timer_value0_high : 16; /*RTC timer high 16 bits*/ - uint32_t reserved16 : 16; + uint32_t rtc_timer_value0_high:16; /*RTC timer high 16 bits*/ + uint32_t reserved16: 16; }; uint32_t val; } time_high0; union { struct { - uint32_t rtc_sw_cpu_int : 1; /*rtc software interrupt to main cpu*/ - uint32_t rtc_slp_reject_cause_clr : 1; /*clear rtc sleep reject cause*/ - uint32_t reserved2 : 20; - uint32_t apb2rtc_bridge_sel : 1; /*1: APB to RTC using bridge*/ - uint32_t reserved23 : 5; - uint32_t sdio_active_ind : 1; /*SDIO active indication*/ - uint32_t slp_wakeup : 1; /*leep wakeup bit*/ - uint32_t slp_reject : 1; /*leep reject bit*/ - uint32_t sleep_en : 1; /*sleep enable bit*/ + uint32_t rtc_sw_cpu_int: 1; /*rtc software interrupt to main cpu*/ + uint32_t rtc_slp_reject_cause_clr: 1; /*clear rtc sleep reject cause*/ + uint32_t reserved2: 20; + uint32_t apb2rtc_bridge_sel: 1; /*1: APB to RTC using bridge*/ + uint32_t reserved23: 5; + uint32_t sdio_active_ind: 1; /*SDIO active indication*/ + uint32_t slp_wakeup: 1; /*leep wakeup bit*/ + uint32_t slp_reject: 1; /*leep reject bit*/ + uint32_t sleep_en: 1; /*sleep enable bit*/ }; uint32_t val; } state0; union { struct { - uint32_t cpu_stall_en : 1; /*CPU stall enable bit*/ - uint32_t cpu_stall_wait : 5; /*CPU stall wait cycles in fast_clk_rtc*/ - uint32_t ck8m_wait : 8; /*CK8M wait cycles in slow_clk_rtc*/ - uint32_t xtl_buf_wait : 10; /*XTAL wait cycles in slow_clk_rtc*/ - uint32_t pll_buf_wait : 8; /*PLL wait cycles in slow_clk_rtc*/ + uint32_t cpu_stall_en: 1; /*CPU stall enable bit*/ + uint32_t cpu_stall_wait: 5; /*CPU stall wait cycles in fast_clk_rtc*/ + uint32_t ck8m_wait: 8; /*CK8M wait cycles in slow_clk_rtc*/ + uint32_t xtl_buf_wait: 10; /*XTAL wait cycles in slow_clk_rtc*/ + uint32_t pll_buf_wait: 8; /*PLL wait cycles in slow_clk_rtc*/ }; uint32_t val; } timer1; union { struct { - uint32_t reserved0 : 15; - uint32_t ulpcp_touch_start_wait : 9; /*wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work*/ - uint32_t min_time_ck8m_off : 8; /*minimal cycles in slow_clk_rtc for CK8M in power down state*/ + uint32_t reserved0: 15; + uint32_t ulpcp_touch_start_wait: 9; /*wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work*/ + uint32_t min_time_ck8m_off: 8; /*minimal cycles in slow_clk_rtc for CK8M in power down state*/ }; uint32_t val; } timer2; union { struct { - uint32_t wifi_wait_timer : 9; - uint32_t wifi_powerup_timer : 7; - uint32_t rom_ram_wait_timer : 9; - uint32_t rom_ram_powerup_timer : 7; + uint32_t wifi_wait_timer: 9; + uint32_t wifi_powerup_timer: 7; + uint32_t bt_wait_timer: 9; + uint32_t bt_powerup_timer: 7; }; uint32_t val; } timer3; union { struct { - uint32_t rtc_wait_timer : 9; - uint32_t rtc_powerup_timer : 7; - uint32_t dg_wrap_wait_timer : 9; - uint32_t dg_wrap_powerup_timer : 7; + uint32_t rtc_wait_timer: 9; + uint32_t rtc_powerup_timer: 7; + uint32_t dg_wrap_wait_timer: 9; + uint32_t dg_wrap_powerup_timer: 7; }; uint32_t val; } timer4; union { struct { - uint32_t reserved0 : 8; - uint32_t min_slp_val : 8; /*minimal sleep cycles in slow_clk_rtc*/ - uint32_t rtcmem_wait_timer : 9; - uint32_t rtcmem_powerup_timer : 7; + uint32_t reserved0: 8; + uint32_t min_slp_val: 8; /*minimal sleep cycles in slow_clk_rtc*/ + uint32_t reserved16: 16; }; uint32_t val; } timer5; union { struct { - uint32_t reserved0 : 16; - uint32_t dg_dcdc_wait_timer : 9; - uint32_t dg_dcdc_powerup_timer : 7; + uint32_t cpu_top_wait_timer: 9; + uint32_t cpu_top_powerup_timer: 7; + uint32_t dg_peri_wait_timer: 9; + uint32_t dg_peri_powerup_timer: 7; }; uint32_t val; } timer6; union { struct { - uint32_t reserved0 : 18; - uint32_t i2c_reset_por_force_pd : 1; - uint32_t i2c_reset_por_force_pu : 1; - uint32_t glitch_rst_en : 1; - uint32_t reserved21 : 1; /*PLLA force power down*/ - uint32_t sar_i2c_pu : 1; /*PLLA force power up*/ - uint32_t plla_force_pd : 1; /*PLLA force power down*/ - uint32_t plla_force_pu : 1; /*PLLA force power up*/ - uint32_t bbpll_cal_slp_start : 1; /*start BBPLL calibration during sleep*/ - uint32_t pvtmon_pu : 1; /*1: PVTMON power up*/ - uint32_t txrf_i2c_pu : 1; /*1: TXRF_I2C power up*/ - uint32_t rfrx_pbus_pu : 1; /*1: RFRX_PBUS power up*/ - uint32_t reserved29 : 1; - uint32_t ckgen_i2c_pu : 1; /*1: CKGEN_I2C power up*/ - uint32_t pll_i2c_pu : 1; + uint32_t reserved0: 18; + uint32_t i2c_reset_por_force_pd: 1; + uint32_t i2c_reset_por_force_pu: 1; + uint32_t glitch_rst_en: 1; + uint32_t reserved21: 1; /*PLLA force power down*/ + uint32_t sar_i2c_pu: 1; /*PLLA force power up*/ + uint32_t plla_force_pd: 1; /*PLLA force power down*/ + uint32_t plla_force_pu: 1; /*PLLA force power up*/ + uint32_t bbpll_cal_slp_start: 1; /*start BBPLL calibration during sleep*/ + uint32_t pvtmon_pu: 1; /*1: PVTMON power up*/ + uint32_t txrf_i2c_pu: 1; /*1: TXRF_I2C power up*/ + uint32_t rfrx_pbus_pu: 1; /*1: RFRX_PBUS power up*/ + uint32_t reserved29: 1; + uint32_t ckgen_i2c_pu: 1; /*1: CKGEN_I2C power up*/ + uint32_t pll_i2c_pu: 1; }; uint32_t val; } ana_conf; union { struct { - uint32_t reset_cause_procpu : 6; /*reset cause of PRO CPU*/ - uint32_t reset_cause_appcpu : 6; /*reset cause of APP CPU*/ - uint32_t appcpu_stat_vector_sel : 1; /*APP CPU state vector sel*/ - uint32_t procpu_stat_vector_sel : 1; /*PRO CPU state vector sel*/ - uint32_t reset_flag_procpu : 1; /*PRO CPU reset_flag*/ - uint32_t reset_flag_appcpu : 1; /*APP CPU reset flag*/ - uint32_t reset_flag_procpu_clr : 1; /*clear PRO CPU reset_flag*/ - uint32_t reset_flag_appcpu_clr : 1; /*clear APP CPU reset flag*/ - uint32_t appcpu_ocd_halt_on_reset : 1; /*APPCPU OcdHaltOnReset*/ - uint32_t procpu_ocd_halt_on_reset : 1; /*PROCPU OcdHaltOnReset*/ - uint32_t reset_flag_jtag_procpu : 1; - uint32_t reset_flag_jtag_appcpu : 1; - uint32_t reset_flag_jtag_procpu_clr : 1; - uint32_t reset_flag_jtag_appcpu_clr : 1; - uint32_t rtc_app_dreset_mask : 1; - uint32_t rtc_pro_dreset_mask : 1; - uint32_t reserved26 : 6; + uint32_t reset_cause_procpu: 6; /*reset cause of PRO CPU*/ + uint32_t reset_cause_appcpu: 6; /*reset cause of APP CPU*/ + uint32_t appcpu_stat_vector_sel: 1; /*APP CPU state vector sel*/ + uint32_t procpu_stat_vector_sel: 1; /*PRO CPU state vector sel*/ + uint32_t reset_flag_procpu: 1; /*PRO CPU reset_flag*/ + uint32_t reset_flag_appcpu: 1; /*APP CPU reset flag*/ + uint32_t reset_flag_procpu_clr: 1; /*clear PRO CPU reset_flag*/ + uint32_t reset_flag_appcpu_clr: 1; /*clear APP CPU reset flag*/ + uint32_t appcpu_ocd_halt_on_reset: 1; /*APPCPU OcdHaltOnReset*/ + uint32_t procpu_ocd_halt_on_reset: 1; /*PROCPU OcdHaltOnReset*/ + uint32_t reset_flag_jtag_procpu: 1; + uint32_t reset_flag_jtag_appcpu: 1; + uint32_t reset_flag_jtag_procpu_clr: 1; + uint32_t reset_flag_jtag_appcpu_clr: 1; + uint32_t rtc_app_dreset_mask: 1; + uint32_t rtc_pro_dreset_mask: 1; + uint32_t reserved26: 6; }; uint32_t val; } reset_state; union { struct { - uint32_t reserved0 : 15; - uint32_t rtc_wakeup_ena : 17; /*wakeup enable bitmap*/ + uint32_t reserved0: 15; + uint32_t rtc_wakeup_ena:17; /*wakeup enable bitmap*/ }; uint32_t val; } wakeup_state; union { struct { - uint32_t slp_wakeup : 1; /*enable sleep wakeup interrupt*/ - uint32_t slp_reject : 1; /*enable sleep reject interrupt*/ - uint32_t sdio_idle : 1; /*enable SDIO idle interrupt*/ - uint32_t rtc_wdt : 1; /*enable RTC WDT interrupt*/ - uint32_t rtc_touch_scan_done : 1; /*enable touch scan done interrupt*/ - uint32_t rtc_ulp_cp : 1; /*enable ULP-coprocessor interrupt*/ - uint32_t rtc_touch_done : 1; /*enable touch done interrupt*/ - uint32_t rtc_touch_active : 1; /*enable touch active interrupt*/ - uint32_t rtc_touch_inactive : 1; /*enable touch inactive interrupt*/ - uint32_t rtc_brown_out : 1; /*enable brown out interrupt*/ - uint32_t rtc_main_timer : 1; /*enable RTC main timer interrupt*/ - uint32_t rtc_saradc1 : 1; /*enable saradc1 interrupt*/ - uint32_t rtc_tsens : 1; /*enable tsens interrupt*/ - uint32_t rtc_cocpu : 1; /*enable riscV cocpu interrupt*/ - uint32_t rtc_saradc2 : 1; /*enable saradc2 interrupt*/ - uint32_t rtc_swd : 1; /*enable super watch dog interrupt*/ - uint32_t rtc_xtal32k_dead : 1; /*enable xtal32k_dead interrupt*/ - uint32_t rtc_cocpu_trap : 1; /*enable cocpu trap interrupt*/ - uint32_t rtc_touch_timeout : 1; /*enable touch timeout interrupt*/ - uint32_t rtc_glitch_det : 1; /*enbale gitch det interrupt*/ - uint32_t rtc_touch_approach_loop_done : 1; - uint32_t reserved21 : 11; + uint32_t slp_wakeup: 1; /*enable sleep wakeup interrupt*/ + uint32_t slp_reject: 1; /*enable sleep reject interrupt*/ + uint32_t sdio_idle: 1; /*enable SDIO idle interrupt*/ + uint32_t rtc_wdt: 1; /*enable RTC WDT interrupt*/ + uint32_t rtc_touch_scan_done: 1; /*enable touch scan done interrupt*/ + uint32_t rtc_ulp_cp: 1; /*enable ULP-coprocessor interrupt*/ + uint32_t rtc_touch_done: 1; /*enable touch done interrupt*/ + uint32_t rtc_touch_active: 1; /*enable touch active interrupt*/ + uint32_t rtc_touch_inactive: 1; /*enable touch inactive interrupt*/ + uint32_t rtc_brown_out: 1; /*enable brown out interrupt*/ + uint32_t rtc_main_timer: 1; /*enable RTC main timer interrupt*/ + uint32_t rtc_saradc1: 1; /*enable saradc1 interrupt*/ + uint32_t rtc_tsens: 1; /*enable tsens interrupt*/ + uint32_t rtc_cocpu: 1; /*enable riscV cocpu interrupt*/ + uint32_t rtc_saradc2: 1; /*enable saradc2 interrupt*/ + uint32_t rtc_swd: 1; /*enable super watch dog interrupt*/ + uint32_t rtc_xtal32k_dead: 1; /*enable xtal32k_dead interrupt*/ + uint32_t rtc_cocpu_trap: 1; /*enable cocpu trap interrupt*/ + uint32_t rtc_touch_timeout: 1; /*enable touch timeout interrupt*/ + uint32_t rtc_glitch_det: 1; /*enbale gitch det interrupt*/ + uint32_t rtc_touch_approach_loop_done: 1; + uint32_t reserved21: 11; }; uint32_t val; } int_ena; union { struct { - uint32_t slp_wakeup : 1; /*sleep wakeup interrupt raw*/ - uint32_t slp_reject : 1; /*sleep reject interrupt raw*/ - uint32_t sdio_idle : 1; /*SDIO idle interrupt raw*/ - uint32_t rtc_wdt : 1; /*RTC WDT interrupt raw*/ - uint32_t rtc_touch_scan_done : 1; - uint32_t rtc_ulp_cp : 1; /*ULP-coprocessor interrupt raw*/ - uint32_t rtc_touch_done : 1; /*touch interrupt raw*/ - uint32_t rtc_touch_active : 1; /*touch active interrupt raw*/ - uint32_t rtc_touch_inactive : 1; /*touch inactive interrupt raw*/ - uint32_t rtc_brown_out : 1; /*brown out interrupt raw*/ - uint32_t rtc_main_timer : 1; /*RTC main timer interrupt raw*/ - uint32_t rtc_saradc1 : 1; /*saradc1 interrupt raw*/ - uint32_t rtc_tsens : 1; /*tsens interrupt raw*/ - uint32_t rtc_cocpu : 1; /*riscV cocpu interrupt raw*/ - uint32_t rtc_saradc2 : 1; /*saradc2 interrupt raw*/ - uint32_t rtc_swd : 1; /*super watch dog interrupt raw*/ - uint32_t rtc_xtal32k_dead : 1; /*xtal32k dead detection interrupt raw*/ - uint32_t rtc_cocpu_trap : 1; /*cocpu trap interrupt raw*/ - uint32_t rtc_touch_timeout : 1; /*touch timeout interrupt raw*/ - uint32_t rtc_glitch_det : 1; /*glitch_det_interrupt_raw*/ - uint32_t rtc_touch_approach_loop_done : 1; - uint32_t reserved21 : 11; + uint32_t slp_wakeup: 1; /*sleep wakeup interrupt raw*/ + uint32_t slp_reject: 1; /*sleep reject interrupt raw*/ + uint32_t sdio_idle: 1; /*SDIO idle interrupt raw*/ + uint32_t rtc_wdt: 1; /*RTC WDT interrupt raw*/ + uint32_t rtc_touch_scan_done: 1; + uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt raw*/ + uint32_t rtc_touch_done: 1; /*touch interrupt raw*/ + uint32_t rtc_touch_active: 1; /*touch active interrupt raw*/ + uint32_t rtc_touch_inactive: 1; /*touch inactive interrupt raw*/ + uint32_t rtc_brown_out: 1; /*brown out interrupt raw*/ + uint32_t rtc_main_timer: 1; /*RTC main timer interrupt raw*/ + uint32_t rtc_saradc1: 1; /*saradc1 interrupt raw*/ + uint32_t rtc_tsens: 1; /*tsens interrupt raw*/ + uint32_t rtc_cocpu: 1; /*riscV cocpu interrupt raw*/ + uint32_t rtc_saradc2: 1; /*saradc2 interrupt raw*/ + uint32_t rtc_swd: 1; /*super watch dog interrupt raw*/ + uint32_t rtc_xtal32k_dead: 1; /*xtal32k dead detection interrupt raw*/ + uint32_t rtc_cocpu_trap: 1; /*cocpu trap interrupt raw*/ + uint32_t rtc_touch_timeout: 1; /*touch timeout interrupt raw*/ + uint32_t rtc_glitch_det: 1; /*glitch_det_interrupt_raw*/ + uint32_t rtc_touch_approach_loop_done: 1; + uint32_t reserved21: 11; }; uint32_t val; } int_raw; union { struct { - uint32_t slp_wakeup : 1; /*sleep wakeup interrupt state*/ - uint32_t slp_reject : 1; /*sleep reject interrupt state*/ - uint32_t sdio_idle : 1; /*SDIO idle interrupt state*/ - uint32_t rtc_wdt : 1; /*RTC WDT interrupt state*/ - uint32_t rtc_touch_scan_done : 1; - uint32_t rtc_ulp_cp : 1; /*ULP-coprocessor interrupt state*/ - uint32_t rtc_touch_done : 1; /*touch done interrupt state*/ - uint32_t rtc_touch_active : 1; /*touch active interrupt state*/ - uint32_t rtc_touch_inactive : 1; /*touch inactive interrupt state*/ - uint32_t rtc_brown_out : 1; /*brown out interrupt state*/ - uint32_t rtc_main_timer : 1; /*RTC main timer interrupt state*/ - uint32_t rtc_saradc1 : 1; /*saradc1 interrupt state*/ - uint32_t rtc_tsens : 1; /*tsens interrupt state*/ - uint32_t rtc_cocpu : 1; /*riscV cocpu interrupt state*/ - uint32_t rtc_saradc2 : 1; /*saradc2 interrupt state*/ - uint32_t rtc_swd : 1; /*super watch dog interrupt state*/ - uint32_t rtc_xtal32k_dead : 1; /*xtal32k dead detection interrupt state*/ - uint32_t rtc_cocpu_trap : 1; /*cocpu trap interrupt state*/ - uint32_t rtc_touch_timeout : 1; /*Touch timeout interrupt state*/ - uint32_t rtc_glitch_det : 1; /*glitch_det_interrupt state*/ - uint32_t rtc_touch_approach_loop_done : 1; - uint32_t reserved21 : 11; + uint32_t slp_wakeup: 1; /*sleep wakeup interrupt state*/ + uint32_t slp_reject: 1; /*sleep reject interrupt state*/ + uint32_t sdio_idle: 1; /*SDIO idle interrupt state*/ + uint32_t rtc_wdt: 1; /*RTC WDT interrupt state*/ + uint32_t rtc_touch_scan_done: 1; + uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt state*/ + uint32_t rtc_touch_done: 1; /*touch done interrupt state*/ + uint32_t rtc_touch_active: 1; /*touch active interrupt state*/ + uint32_t rtc_touch_inactive: 1; /*touch inactive interrupt state*/ + uint32_t rtc_brown_out: 1; /*brown out interrupt state*/ + uint32_t rtc_main_timer: 1; /*RTC main timer interrupt state*/ + uint32_t rtc_saradc1: 1; /*saradc1 interrupt state*/ + uint32_t rtc_tsens: 1; /*tsens interrupt state*/ + uint32_t rtc_cocpu: 1; /*riscV cocpu interrupt state*/ + uint32_t rtc_saradc2: 1; /*saradc2 interrupt state*/ + uint32_t rtc_swd: 1; /*super watch dog interrupt state*/ + uint32_t rtc_xtal32k_dead: 1; /*xtal32k dead detection interrupt state*/ + uint32_t rtc_cocpu_trap: 1; /*cocpu trap interrupt state*/ + uint32_t rtc_touch_timeout: 1; /*Touch timeout interrupt state*/ + uint32_t rtc_glitch_det: 1; /*glitch_det_interrupt state*/ + uint32_t rtc_touch_approach_loop_done: 1; + uint32_t reserved21: 11; }; uint32_t val; } int_st; union { struct { - uint32_t slp_wakeup : 1; /*Clear sleep wakeup interrupt state*/ - uint32_t slp_reject : 1; /*Clear sleep reject interrupt state*/ - uint32_t sdio_idle : 1; /*Clear SDIO idle interrupt state*/ - uint32_t rtc_wdt : 1; /*Clear RTC WDT interrupt state*/ - uint32_t rtc_touch_scan_done : 1; - uint32_t rtc_ulp_cp : 1; /*Clear ULP-coprocessor interrupt state*/ - uint32_t rtc_touch_done : 1; /*Clear touch done interrupt state*/ - uint32_t rtc_touch_active : 1; /*Clear touch active interrupt state*/ - uint32_t rtc_touch_inactive : 1; /*Clear touch inactive interrupt state*/ - uint32_t rtc_brown_out : 1; /*Clear brown out interrupt state*/ - uint32_t rtc_main_timer : 1; /*Clear RTC main timer interrupt state*/ - uint32_t rtc_saradc1 : 1; /*Clear saradc1 interrupt state*/ - uint32_t rtc_tsens : 1; /*Clear tsens interrupt state*/ - uint32_t rtc_cocpu : 1; /*Clear riscV cocpu interrupt state*/ - uint32_t rtc_saradc2 : 1; /*Clear saradc2 interrupt state*/ - uint32_t rtc_swd : 1; /*Clear super watch dog interrupt state*/ - uint32_t rtc_xtal32k_dead : 1; /*Clear RTC WDT interrupt state*/ - uint32_t rtc_cocpu_trap : 1; /*Clear cocpu trap interrupt state*/ - uint32_t rtc_touch_timeout : 1; /*Clear touch timeout interrupt state*/ - uint32_t rtc_glitch_det : 1; /*Clear glitch det interrupt state*/ - uint32_t rtc_touch_approach_loop_done : 1; - uint32_t reserved21 : 11; + uint32_t slp_wakeup: 1; /*Clear sleep wakeup interrupt state*/ + uint32_t slp_reject: 1; /*Clear sleep reject interrupt state*/ + uint32_t sdio_idle: 1; /*Clear SDIO idle interrupt state*/ + uint32_t rtc_wdt: 1; /*Clear RTC WDT interrupt state*/ + uint32_t rtc_touch_scan_done: 1; + uint32_t rtc_ulp_cp: 1; /*Clear ULP-coprocessor interrupt state*/ + uint32_t rtc_touch_done: 1; /*Clear touch done interrupt state*/ + uint32_t rtc_touch_active: 1; /*Clear touch active interrupt state*/ + uint32_t rtc_touch_inactive: 1; /*Clear touch inactive interrupt state*/ + uint32_t rtc_brown_out: 1; /*Clear brown out interrupt state*/ + uint32_t rtc_main_timer: 1; /*Clear RTC main timer interrupt state*/ + uint32_t rtc_saradc1: 1; /*Clear saradc1 interrupt state*/ + uint32_t rtc_tsens: 1; /*Clear tsens interrupt state*/ + uint32_t rtc_cocpu: 1; /*Clear riscV cocpu interrupt state*/ + uint32_t rtc_saradc2: 1; /*Clear saradc2 interrupt state*/ + uint32_t rtc_swd: 1; /*Clear super watch dog interrupt state*/ + uint32_t rtc_xtal32k_dead: 1; /*Clear RTC WDT interrupt state*/ + uint32_t rtc_cocpu_trap: 1; /*Clear cocpu trap interrupt state*/ + uint32_t rtc_touch_timeout: 1; /*Clear touch timeout interrupt state*/ + uint32_t rtc_glitch_det: 1; /*Clear glitch det interrupt state*/ + uint32_t rtc_touch_approach_loop_done: 1; + uint32_t reserved21: 11; }; uint32_t val; } int_clr; - uint32_t store[4]; + uint32_t store[4]; /**/ union { struct { - uint32_t xtal32k_en : 1; /*xtal 32k watch dog enable*/ - uint32_t xtal32k_wdt_clk_fo : 1; /*xtal 32k watch dog clock force on*/ - uint32_t xtal32k_wdt_reset : 1; /*xtal 32k watch dog sw reset*/ - uint32_t xtal32k_ext_clk_fo : 1; /*xtal 32k external xtal clock force on*/ - uint32_t xtal32k_auto_backup : 1; /*xtal 32k switch to back up clock when xtal is dead*/ - uint32_t xtal32k_auto_restart : 1; /*xtal 32k restart xtal when xtal is dead*/ - uint32_t xtal32k_auto_return : 1; /*xtal 32k switch back xtal when xtal is restarted*/ - uint32_t xtal32k_xpd_force : 1; /*Xtal 32k xpd control by sw or fsm*/ - uint32_t enckinit_xtal_32k : 1; /*apply an internal clock to help xtal 32k to start*/ - uint32_t dbuf_xtal_32k : 1; /*0: single-end buffer 1: differential buffer*/ - uint32_t dgm_xtal_32k : 3; /*xtal_32k gm control*/ - uint32_t dres_xtal_32k : 3; /*DRES_XTAL_32K*/ - uint32_t xpd_xtal_32k : 1; /*XPD_XTAL_32K*/ - uint32_t dac_xtal_32k : 3; /*DAC_XTAL_32K*/ - uint32_t rtc_wdt_state : 3; /*state of 32k_wdt*/ - uint32_t rtc_xtal32k_gpio_sel : 1; /*XTAL_32K sel. 0: external XTAL_32K*/ - uint32_t reserved24 : 6; - uint32_t ctr_lv : 1; /*0: power down XTAL at high level*/ - uint32_t ctr_en : 1; + uint32_t xtal32k_wdt_en: 1; /*xtal 32k watch dog enable*/ + uint32_t xtal32k_wdt_clk_fo: 1; /*xtal 32k watch dog clock force on*/ + uint32_t xtal32k_wdt_reset: 1; /*xtal 32k watch dog sw reset*/ + uint32_t xtal32k_ext_clk_fo: 1; /*xtal 32k external xtal clock force on*/ + uint32_t xtal32k_auto_backup: 1; /*xtal 32k switch to back up clock when xtal is dead*/ + uint32_t xtal32k_auto_restart: 1; /*xtal 32k restart xtal when xtal is dead*/ + uint32_t xtal32k_auto_return: 1; /*xtal 32k switch back xtal when xtal is restarted*/ + uint32_t xtal32k_xpd_force: 1; /*Xtal 32k xpd control by sw or fsm*/ + uint32_t enckinit_xtal_32k: 1; /*apply an internal clock to help xtal 32k to start*/ + uint32_t dbuf_xtal_32k: 1; /*0: single-end buffer 1: differential buffer*/ + uint32_t dgm_xtal_32k: 3; /*xtal_32k gm control*/ + uint32_t dres_xtal_32k: 3; /*DRES_XTAL_32K*/ + uint32_t xpd_xtal_32k: 1; /*XPD_XTAL_32K*/ + uint32_t dac_xtal_32k: 3; /*DAC_XTAL_32K*/ + uint32_t rtc_wdt_state: 3; /*state of 32k_wdt*/ + uint32_t rtc_xtal32k_gpio_sel: 1; /*XTAL_32K sel. 0: external XTAL_32K*/ + uint32_t reserved24: 6; + uint32_t ctr_lv: 1; /*0: power down XTAL at high level*/ + uint32_t ctr_en: 1; }; uint32_t val; } ext_xtl_conf; union { struct { - uint32_t reserved0 : 29; - uint32_t gpio_wakeup_filter : 1; /*enable filter for gpio wakeup event*/ - uint32_t ext_wakeup0_lv : 1; /*0: external wakeup at low level*/ - uint32_t ext_wakeup1_lv : 1; + uint32_t reserved0: 29; + uint32_t gpio_wakeup_filter: 1; /*enable filter for gpio wakeup event*/ + uint32_t wakeup0_lv: 1; /*0: external wakeup at low level*/ + uint32_t wakeup1_lv: 1; }; uint32_t val; } ext_wakeup_conf; union { struct { - uint32_t reserved0 : 12; - uint32_t rtc_sleep_reject_ena : 18; /*sleep reject enable*/ - uint32_t light_slp_reject_en : 1; /*enable reject for light sleep*/ - uint32_t deep_slp_reject_en : 1; /*enable reject for deep sleep*/ + uint32_t reserved0: 12; + uint32_t rtc_sleep_reject_ena:18; /*sleep reject enable*/ + uint32_t light_slp_reject_en: 1; /*enable reject for light sleep*/ + uint32_t deep_slp_reject_en: 1; /*enable reject for deep sleep*/ }; uint32_t val; } slp_reject_conf; union { struct { - uint32_t reserved0 : 29; - uint32_t cpusel_conf : 1; /*CPU sel option*/ - uint32_t cpuperiod_sel : 2; + uint32_t reserved0: 29; + uint32_t cpusel_conf: 1; /*CPU sel option*/ + uint32_t cpuperiod_sel: 2; }; uint32_t val; } cpu_period_conf; union { struct { - uint32_t reserved0 : 22; - uint32_t sdio_act_dnum : 10; + uint32_t reserved0: 22; + uint32_t sdio_act_dnum:10; }; uint32_t val; } sdio_act_conf; union { struct { - uint32_t reserved0 : 3; - uint32_t ck8m_div_sel_vld : 1; /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/ - uint32_t ck8m_div : 2; /*CK8M_D256_OUT divider. 00: div128*/ - uint32_t enb_ck8m : 1; /*disable CK8M and CK8M_D256_OUT*/ - uint32_t enb_ck8m_div : 1; /*1: CK8M_D256_OUT is actually CK8M*/ - uint32_t dig_xtal32k_en : 1; /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ - uint32_t dig_clk8m_d256_en : 1; /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ - uint32_t dig_clk8m_en : 1; /*enable CK8M for digital core (no relationship with RTC core)*/ - uint32_t reserved11 : 1; - uint32_t ck8m_div_sel : 3; /*divider = reg_ck8m_div_sel + 1*/ - uint32_t xtal_force_nogating : 1; /*XTAL force no gating during sleep*/ - uint32_t ck8m_force_nogating : 1; /*CK8M force no gating during sleep*/ - uint32_t ck8m_dfreq : 8; /*CK8M_DFREQ*/ - uint32_t ck8m_force_pd : 1; /*CK8M force power down*/ - uint32_t ck8m_force_pu : 1; /*CK8M force power up*/ - uint32_t reserved27 : 2; - uint32_t fast_clk_rtc_sel : 1; /*fast_clk_rtc sel. 0: XTAL div 4*/ - uint32_t ana_clk_rtc_sel : 2; + uint32_t reserved0: 3; + uint32_t ck8m_div_sel_vld: 1; /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/ + uint32_t ck8m_div: 2; /*CK8M_D256_OUT divider. 00: div128*/ + uint32_t enb_ck8m: 1; /*disable CK8M and CK8M_D256_OUT*/ + uint32_t enb_ck8m_div: 1; /*1: CK8M_D256_OUT is actually CK8M*/ + uint32_t dig_xtal32k_en: 1; /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ + uint32_t dig_clk8m_d256_en: 1; /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ + uint32_t dig_clk8m_en: 1; /*enable CK8M for digital core (no relationship with RTC core)*/ + uint32_t reserved11: 1; + uint32_t ck8m_div_sel: 3; /*divider = reg_ck8m_div_sel + 1*/ + uint32_t xtal_force_nogating: 1; /*XTAL force no gating during sleep*/ + uint32_t ck8m_force_nogating: 1; /*CK8M force no gating during sleep*/ + uint32_t ck8m_dfreq: 8; /*CK8M_DFREQ*/ + uint32_t ck8m_force_pd: 1; /*CK8M force power down*/ + uint32_t ck8m_force_pu: 1; /*CK8M force power up*/ + uint32_t reserved27: 2; + uint32_t fast_clk_rtc_sel: 1; /*fast_clk_rtc sel. 0: XTAL div 4*/ + uint32_t ana_clk_rtc_sel: 2; }; uint32_t val; } clk_conf; union { struct { - uint32_t reserved0 : 22; - uint32_t rtc_ana_clk_div_vld : 1; /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/ - uint32_t rtc_ana_clk_div : 8; - uint32_t slow_clk_next_edge : 1; + uint32_t reserved0: 22; + uint32_t rtc_ana_clk_div_vld: 1; /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/ + uint32_t rtc_ana_clk_div: 8; + uint32_t slow_clk_next_edge: 1; }; uint32_t val; } slow_clk_conf; union { struct { - uint32_t sdio_timer_target : 8; /*timer count to apply reg_sdio_dcap after sdio power on*/ - uint32_t reserved8 : 1; - uint32_t sdio_dthdrv : 2; /*Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/ - uint32_t sdio_dcap : 2; /*ability to prevent LDO from overshoot*/ - uint32_t sdio_initi : 2; /*add resistor from ldo output to ground. 0: no res*/ - uint32_t sdio_en_initi : 1; /*0 to set init[1:0]=0*/ - uint32_t sdio_dcurlim : 3; /*tune current limit threshold when tieh = 0. About 800mA/(8+d)*/ - uint32_t sdio_modecurlim : 1; /*select current limit mode*/ - uint32_t sdio_encurlim : 1; /*enable current limit*/ - uint32_t sdio_pd_en : 1; /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ - uint32_t sdio_force : 1; /*1: use SW option to control SDIO_REG*/ - uint32_t sdio_tieh : 1; /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ - uint32_t reg1p8_ready : 1; /*read only register for REG1P8_READY*/ - uint32_t drefl_sdio : 2; /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ - uint32_t drefm_sdio : 2; /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ - uint32_t drefh_sdio : 2; /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ - uint32_t xpd_sdio : 1; + uint32_t sdio_timer_target: 8; /*timer count to apply reg_sdio_dcap after sdio power on*/ + uint32_t reserved8: 1; + uint32_t sdio_dthdrv: 2; /*Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/ + uint32_t sdio_dcap: 2; /*ability to prevent LDO from overshoot*/ + uint32_t sdio_initi: 2; /*add resistor from ldo output to ground. 0: no res*/ + uint32_t sdio_en_initi: 1; /*0 to set init[1:0]=0*/ + uint32_t sdio_dcurlim: 3; /*tune current limit threshold when tieh = 0. About 800mA/(8+d)*/ + uint32_t sdio_modecurlim: 1; /*select current limit mode*/ + uint32_t sdio_encurlim: 1; /*enable current limit*/ + uint32_t sdio_pd_en: 1; /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ + uint32_t sdio_force: 1; /*1: use SW option to control SDIO_REG*/ + uint32_t sdio_tieh: 1; /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ + uint32_t reg1p8_ready: 1; /*read only register for REG1P8_READY*/ + uint32_t drefl_sdio: 2; /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t drefm_sdio: 2; /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t drefh_sdio: 2; /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t xpd_sdio: 1; }; uint32_t val; } sdio_conf; union { struct { - uint32_t reserved0 : 10; - uint32_t bias_buf_idle : 1; - uint32_t bias_buf_wake : 1; - uint32_t bias_buf_deep_slp : 1; - uint32_t bias_buf_monitor : 1; - uint32_t pd_cur_deep_slp : 1; /*xpd cur when rtc in sleep_state*/ - uint32_t pd_cur_monitor : 1; /*xpd cur when rtc in monitor state*/ - uint32_t bias_sleep_deep_slp : 1; /*bias_sleep when rtc in sleep_state*/ - uint32_t bias_sleep_monitor : 1; /*bias_sleep when rtc in monitor state*/ - uint32_t dbg_atten_deep_slp : 4; /*DBG_ATTEN when rtc in sleep state*/ - uint32_t dbg_atten_monitor : 4; /*DBG_ATTEN when rtc in monitor state*/ - uint32_t reserved26 : 6; + uint32_t reserved0: 10; + uint32_t bias_buf_idle: 1; + uint32_t bias_buf_wake: 1; + uint32_t bias_buf_deep_slp: 1; + uint32_t bias_buf_monitor: 1; + uint32_t pd_cur_deep_slp: 1; /*xpd cur when rtc in sleep_state*/ + uint32_t pd_cur_monitor: 1; /*xpd cur when rtc in monitor state*/ + uint32_t bias_sleep_deep_slp: 1; /*bias_sleep when rtc in sleep_state*/ + uint32_t bias_sleep_monitor: 1; /*bias_sleep when rtc in monitor state*/ + uint32_t dbg_atten_deep_slp: 4; /*DBG_ATTEN when rtc in sleep state*/ + uint32_t dbg_atten_monitor: 4; /*DBG_ATTEN when rtc in monitor state*/ + uint32_t dbg_atten_wakeup: 4; + uint32_t reserved30: 2; }; uint32_t val; } bias_conf; union { struct { - uint32_t reserved0 : 7; - uint32_t dig_cal_en : 1; - uint32_t reserved8 : 6; - uint32_t sck_dcap : 8; /*SCK_DCAP*/ - uint32_t reserved22 : 6; - uint32_t rtc_dboost_force_pd : 1; /*RTC_DBOOST force power down*/ - uint32_t rtc_dboost_force_pu : 1; /*RTC_DBOOST force power up*/ - uint32_t rtculator_force_pd : 1; /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/ - uint32_t rtculator_force_pu : 1; + uint32_t reserved0: 7; + uint32_t dig_cal_en: 1; + uint32_t reserved8: 6; + uint32_t sck_dcap: 8; /*SCK_DCAP*/ + uint32_t reserved22: 6; + uint32_t rtc_dboost_force_pd: 1; /*RTC_DBOOST force power down*/ + uint32_t rtc_dboost_force_pu: 1; /*RTC_DBOOST force power up*/ + uint32_t rtculator_force_pd: 1; /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/ + uint32_t rtculator_force_pu: 1; }; uint32_t val; } rtc; union { struct { - uint32_t rtc_fastmem_force_noiso : 1; /*Fast RTC memory force no ISO*/ - uint32_t rtc_fastmem_force_iso : 1; /*Fast RTC memory force ISO*/ - uint32_t rtc_slowmem_force_noiso : 1; /*RTC memory force no ISO*/ - uint32_t rtc_slowmem_force_iso : 1; /*RTC memory force ISO*/ - uint32_t rtc_force_iso : 1; /*rtc_peri force ISO*/ - uint32_t rtc_force_noiso : 1; /*rtc_peri force no ISO*/ - uint32_t rtc_fastmem_folw_cpu : 1; /*1: Fast RTC memory PD following CPU*/ - uint32_t fastmem_force_lpd : 1; /*Fast RTC memory force PD*/ - uint32_t fastmem_force_lpu : 1; /*Fast RTC memory force no PD*/ - uint32_t rtc_slowmem_folw_cpu : 1; /*1: RTC memory PD following CPU*/ - uint32_t rtc_slowmem_force_lpd : 1; /*RTC memory force PD*/ - uint32_t rtc_slowmem_force_lpu : 1; /*RTC memory force no PD*/ - uint32_t rtc_fastmem_force_pd : 1; /*Fast RTC memory force power down*/ - uint32_t rtc_fastmem_force_pu : 1; /*Fast RTC memory force power up*/ - uint32_t rtc_fastmem_pd_en : 1; /*enable power down fast RTC memory in sleep*/ - uint32_t rtc_slowmem_force_pd : 1; /*RTC memory force power down*/ - uint32_t rtc_slowmem_force_pu : 1; /*RTC memory force power up*/ - uint32_t rtc_slowmem_pd_en : 1; /*enable power down RTC memory in sleep*/ - uint32_t rtc_force_pd : 1; /*rtc_peri force power down*/ - uint32_t rtc_force_pu : 1; /*rtc_peri force power up*/ - uint32_t rtc_pd_en : 1; /*enable power down rtc_peri in sleep */ - uint32_t rtc_pad_force_hold : 1; /*rtc pad force hold*/ - uint32_t reserved22 : 10; + uint32_t fastmem_force_noiso: 1; /*Fast RTC memory force no ISO*/ + uint32_t fastmem_force_iso: 1; /*Fast RTC memory force ISO*/ + uint32_t slowmem_force_noiso: 1; /*RTC memory force no ISO*/ + uint32_t slowmem_force_iso: 1; /*RTC memory force ISO*/ + uint32_t rtc_force_iso: 1; /*rtc_peri force ISO*/ + uint32_t rtc_force_noiso: 1; /*rtc_peri force no ISO*/ + uint32_t fastmem_folw_cpu: 1; /*1: Fast RTC memory PD following CPU*/ + uint32_t fastmem_force_lpd: 1; /*Fast RTC memory force PD*/ + uint32_t fastmem_force_lpu: 1; /*Fast RTC memory force no PD*/ + uint32_t slowmem_folw_cpu: 1; /*1: RTC memory PD following CPU*/ + uint32_t slowmem_force_lpd: 1; /*RTC memory force PD*/ + uint32_t slowmem_force_lpu: 1; /*RTC memory force no PD*/ + uint32_t reserved12: 6; /*enable power down RTC memory in sleep*/ + uint32_t rtc_force_pd: 1; /*rtc_peri force power down*/ + uint32_t rtc_force_pu: 1; /*rtc_peri force power up*/ + uint32_t rtc_pd_en: 1; /*enable power down rtc_peri in sleep*/ + uint32_t rtc_pad_force_hold: 1; /*rtc pad force hold*/ + uint32_t reserved22: 10; }; uint32_t val; - } pwc; + } rtc_pwc; union { struct { - uint32_t reserved0 : 3; - uint32_t lslp_mem_force_pd : 1; /*memories in digital core force PD in sleep*/ - uint32_t lslp_mem_force_pu : 1; /*memories in digital core force no PD in sleep*/ - uint32_t rom0_force_pd : 1; /*ROM force power down*/ - uint32_t rom0_force_pu : 1; /*ROM force power up*/ - uint32_t inter_ram0_force_pd : 1; /*internal SRAM 0 force power down*/ - uint32_t inter_ram0_force_pu : 1; /*internal SRAM 0 force power up*/ - uint32_t inter_ram1_force_pd : 1; /*internal SRAM 1 force power down*/ - uint32_t inter_ram1_force_pu : 1; /*internal SRAM 1 force power up*/ - uint32_t inter_ram2_force_pd : 1; /*internal SRAM 2 force power down*/ - uint32_t inter_ram2_force_pu : 1; /*internal SRAM 2 force power up*/ - uint32_t inter_ram3_force_pd : 1; /*internal SRAM 3 force power down*/ - uint32_t inter_ram3_force_pu : 1; /*internal SRAM 3 force power up*/ - uint32_t inter_ram4_force_pd : 1; /*internal SRAM 4 force power down*/ - uint32_t inter_ram4_force_pu : 1; /*internal SRAM 4 force power up*/ - uint32_t wifi_force_pd : 1; /*wifi force power down*/ - uint32_t wifi_force_pu : 1; /*wifi force power up*/ - uint32_t dg_wrap_force_pd : 1; /*digital core force power down*/ - uint32_t dg_wrap_force_pu : 1; /*digital core force power up*/ - uint32_t dg_dcdc_force_pd : 1; /*digital dcdc force power down*/ - uint32_t dg_dcdc_force_pu : 1; /*digital dcdc force power up*/ - uint32_t dg_dcdc_pd_en : 1; /*enable power down digital dcdc in sleep*/ - uint32_t rom0_pd_en : 1; /*enable power down ROM in sleep*/ - uint32_t inter_ram0_pd_en : 1; /*enable power down internal SRAM 0 in sleep*/ - uint32_t inter_ram1_pd_en : 1; /*enable power down internal SRAM 1 in sleep*/ - uint32_t inter_ram2_pd_en : 1; /*enable power down internal SRAM 2 in sleep*/ - uint32_t inter_ram3_pd_en : 1; /*enable power down internal SRAM 3 in sleep*/ - uint32_t inter_ram4_pd_en : 1; /*enable power down internal SRAM 4 in sleep*/ - uint32_t wifi_pd_en : 1; /*enable power down wifi in sleep*/ - uint32_t dg_wrap_pd_en : 1; + uint32_t reserved0: 3; + uint32_t lslp_mem_force_pd: 1; /*memories in digital core force PD in sleep*/ + uint32_t lslp_mem_force_pu: 1; /*memories in digital core force no PD in sleep*/ + uint32_t reserved5: 6; /*internal SRAM 1 force power up*/ + uint32_t bt_force_pd: 1; /*internal SRAM 2 force power down*/ + uint32_t bt_force_pu: 1; /*internal SRAM 2 force power up*/ + uint32_t dg_peri_force_pd: 1; /*internal SRAM 3 force power down*/ + uint32_t dg_peri_force_pu: 1; /*internal SRAM 3 force power up*/ + uint32_t reserved15: 2; /*internal SRAM 4 force power up*/ + uint32_t wifi_force_pd: 1; /*wifi force power down*/ + uint32_t wifi_force_pu: 1; /*wifi force power up*/ + uint32_t dg_wrap_force_pd: 1; /*digital core force power down*/ + uint32_t dg_wrap_force_pu: 1; /*digital core force power up*/ + uint32_t cpu_top_force_pd: 1; /*digital dcdc force power down*/ + uint32_t cpu_top_force_pu: 1; /*digital dcdc force power up*/ + uint32_t reserved23: 4; /*enable power down internal SRAM 1 in sleep*/ + uint32_t bt_pd_en: 1; /*enable power down internal SRAM 2 in sleep*/ + uint32_t dg_peri_pd_en: 1; /*enable power down internal SRAM 3 in sleep*/ + uint32_t cpu_top_pd_en: 1; /*enable power down internal SRAM 4 in sleep*/ + uint32_t wifi_pd_en: 1; /*enable power down wifi in sleep*/ + uint32_t dg_wrap_pd_en: 1; }; uint32_t val; } dig_pwc; union { struct { - uint32_t reserved0 : 7; - uint32_t dig_iso_force_off : 1; - uint32_t dig_iso_force_on : 1; - uint32_t dg_pad_autohold : 1; /*read only register to indicate digital pad auto-hold status*/ - uint32_t clr_dg_pad_autohold : 1; /*wtite only register to clear digital pad auto-hold*/ - uint32_t dg_pad_autohold_en : 1; /*digital pad enable auto-hold*/ - uint32_t dg_pad_force_noiso : 1; /*digital pad force no ISO*/ - uint32_t dg_pad_force_iso : 1; /*digital pad force ISO*/ - uint32_t dg_pad_force_unhold : 1; /*digital pad force un-hold*/ - uint32_t dg_pad_force_hold : 1; /*digital pad force hold*/ - uint32_t rom0_force_iso : 1; /*ROM force ISO*/ - uint32_t rom0_force_noiso : 1; /*ROM force no ISO*/ - uint32_t inter_ram0_force_iso : 1; /*internal SRAM 0 force ISO*/ - uint32_t inter_ram0_force_noiso : 1; /*internal SRAM 0 force no ISO*/ - uint32_t inter_ram1_force_iso : 1; /*internal SRAM 1 force ISO*/ - uint32_t inter_ram1_force_noiso : 1; /*internal SRAM 1 force no ISO*/ - uint32_t inter_ram2_force_iso : 1; /*internal SRAM 2 force ISO*/ - uint32_t inter_ram2_force_noiso : 1; /*internal SRAM 2 force no ISO*/ - uint32_t inter_ram3_force_iso : 1; /*internal SRAM 3 force ISO*/ - uint32_t inter_ram3_force_noiso : 1; /*internal SRAM 3 force no ISO*/ - uint32_t inter_ram4_force_iso : 1; /*internal SRAM 4 force ISO*/ - uint32_t inter_ram4_force_noiso : 1; /*internal SRAM 4 force no ISO*/ - uint32_t wifi_force_iso : 1; /*wifi force ISO*/ - uint32_t wifi_force_noiso : 1; /*wifi force no ISO*/ - uint32_t dg_wrap_force_iso : 1; /*digital core force ISO*/ - uint32_t dg_wrap_force_noiso : 1; + uint32_t reserved0: 7; + uint32_t dig_iso_force_off: 1; + uint32_t dig_iso_force_on: 1; + uint32_t dg_pad_autohold: 1; /*read only register to indicate digital pad auto-hold status*/ + uint32_t clr_dg_pad_autohold: 1; /*wtite only register to clear digital pad auto-hold*/ + uint32_t dg_pad_autohold_en: 1; /*digital pad enable auto-hold*/ + uint32_t dg_pad_force_noiso: 1; /*digital pad force no ISO*/ + uint32_t dg_pad_force_iso: 1; /*digital pad force ISO*/ + uint32_t dg_pad_force_unhold: 1; /*digital pad force un-hold*/ + uint32_t dg_pad_force_hold: 1; /*digital pad force hold*/ + uint32_t reserved16: 6; /*internal SRAM 1 force no ISO*/ + uint32_t bt_force_iso: 1; /*internal SRAM 2 force ISO*/ + uint32_t bt_force_noiso: 1; /*internal SRAM 2 force no ISO*/ + uint32_t dg_peri_force_iso: 1; /*internal SRAM 3 force ISO*/ + uint32_t dg_peri_force_noiso: 1; /*internal SRAM 3 force no ISO*/ + uint32_t cpu_top_force_iso: 1; /*internal SRAM 4 force ISO*/ + uint32_t cpu_top_force_noiso: 1; /*internal SRAM 4 force no ISO*/ + uint32_t wifi_force_iso: 1; /*wifi force ISO*/ + uint32_t wifi_force_noiso: 1; /*wifi force no ISO*/ + uint32_t dg_wrap_force_iso: 1; /*digital core force ISO*/ + uint32_t dg_wrap_force_noiso: 1; }; uint32_t val; } dig_iso; union { struct { - uint32_t chip_reset_width : 8; /*chip reset siginal pulse width*/ - uint32_t chip_reset_en : 1; /*wdt reset whole chip enable*/ - uint32_t pause_in_slp : 1; /*pause WDT in sleep*/ - uint32_t appcpu_reset_en : 1; /*enable WDT reset APP CPU*/ - uint32_t procpu_reset_en : 1; /*enable WDT reset PRO CPU*/ - uint32_t flashboot_mod_en : 1; /*enable WDT in flash boot*/ - uint32_t sys_reset_length : 3; /*system reset counter length*/ - uint32_t cpu_reset_length : 3; /*CPU reset counter length*/ - uint32_t stg3 : 3; /*1: interrupt stage en*/ - uint32_t stg2 : 3; /*1: interrupt stage en*/ - uint32_t stg1 : 3; /*1: interrupt stage en*/ - uint32_t stg0 : 3; /*1: interrupt stage en*/ - uint32_t en : 1; + uint32_t chip_reset_width: 8; /*chip reset siginal pulse width*/ + uint32_t chip_reset_en: 1; /*wdt reset whole chip enable*/ + uint32_t pause_in_slp: 1; /*pause WDT in sleep*/ + uint32_t appcpu_reset_en: 1; /*enable WDT reset APP CPU*/ + uint32_t procpu_reset_en: 1; /*enable WDT reset PRO CPU*/ + uint32_t flashboot_mod_en: 1; /*enable WDT in flash boot*/ + uint32_t sys_reset_length: 3; /*system reset counter length*/ + uint32_t cpu_reset_length: 3; /*CPU reset counter length*/ + uint32_t stg3: 3; /*1: interrupt stage en*/ + uint32_t stg2: 3; /*1: interrupt stage en*/ + uint32_t stg1: 3; /*1: interrupt stage en*/ + uint32_t stg0: 3; /*1: interrupt stage en*/ + uint32_t en: 1; }; uint32_t val; } wdt_config0; - uint32_t wdt_config1; - uint32_t wdt_config2; - uint32_t wdt_config3; - uint32_t wdt_config4; + uint32_t wdt_config1; /**/ + uint32_t wdt_config2; /**/ + uint32_t wdt_config3; /**/ + uint32_t wdt_config4; /**/ union { struct { - uint32_t reserved0 : 31; - uint32_t feed : 1; + uint32_t reserved0: 31; + uint32_t feed: 1; }; uint32_t val; } wdt_feed; - uint32_t wdt_wprotect; + uint32_t wdt_wprotect; /**/ union { struct { - uint32_t swd_reset_flag : 1; /*swd reset flag*/ - uint32_t swd_feed_int : 1; /*swd interrupt for feeding*/ - uint32_t reserved2 : 15; - uint32_t swd_bypass_rst : 1; - uint32_t swd_signal_width : 10; /*adjust signal width send to swd*/ - uint32_t swd_rst_flag_clr : 1; /*reset swd reset flag*/ - uint32_t swd_feed : 1; /*Sw feed swd*/ - uint32_t swd_disable : 1; /*disabel SWD*/ - uint32_t swd_auto_feed_en : 1; /*automatically feed swd when int comes*/ + uint32_t swd_reset_flag: 1; /*swd reset flag*/ + uint32_t swd_feed_int: 1; /*swd interrupt for feeding*/ + uint32_t reserved2: 15; + uint32_t swd_bypass_rst: 1; + uint32_t swd_signal_width:10; /*adjust signal width send to swd*/ + uint32_t swd_rst_flag_clr: 1; /*reset swd reset flag*/ + uint32_t swd_feed: 1; /*Sw feed swd*/ + uint32_t swd_disable: 1; /*disabel SWD*/ + uint32_t swd_auto_feed_en: 1; /*automatically feed swd when int comes*/ }; uint32_t val; } swd_conf; - uint32_t swd_wprotect; + uint32_t swd_wprotect; /**/ union { struct { - uint32_t reserved0 : 20; - uint32_t appcpu_c1 : 6; /*{reg_sw_stall_appcpu_c1[5:0]*/ - uint32_t procpu_c1 : 6; + uint32_t reserved0: 20; + uint32_t appcpu_c1: 6; /*{reg_sw_stall_appcpu_c1[5:0]*/ + uint32_t procpu_c1: 6; }; uint32_t val; } sw_cpu_stall; - uint32_t store4; - uint32_t store5; - uint32_t store6; - uint32_t store7; + uint32_t store4; /**/ + uint32_t store5; /**/ + uint32_t store6; /**/ + uint32_t store7; /**/ union { struct { - uint32_t xpd_rom0 : 1; /*rom0 power down*/ - uint32_t reserved1 : 1; - uint32_t xpd_dig_dcdc : 1; /*External DCDC power down*/ - uint32_t rtc_peri_iso : 1; /*rtc peripheral iso*/ - uint32_t xpd_rtc_peri : 1; /*rtc peripheral power down */ - uint32_t wifi_iso : 1; /*wifi iso*/ - uint32_t xpd_wifi : 1; /*wifi wrap power down*/ - uint32_t dig_iso : 1; /*digital wrap iso*/ - uint32_t xpd_dig : 1; /*digital wrap power down*/ - uint32_t rtc_touch_state_start : 1; /*touch should start to work*/ - uint32_t rtc_touch_state_switch : 1; /*touch is about to working. Switch rtc main state*/ - uint32_t rtc_touch_state_slp : 1; /*touch is in sleep state*/ - uint32_t rtc_touch_state_done : 1; /*touch is done*/ - uint32_t rtc_cocpu_state_start : 1; /*ulp/cocpu should start to work*/ - uint32_t rtc_cocpu_state_switch : 1; /*ulp/cocpu is about to working. Switch rtc main state*/ - uint32_t rtc_cocpu_state_slp : 1; /*ulp/cocpu is in sleep state*/ - uint32_t rtc_cocpu_state_done : 1; /*ulp/cocpu is done*/ - uint32_t rtc_main_state_xtal_iso : 1; /*no use any more*/ - uint32_t rtc_main_state_pll_on : 1; /*rtc main state machine is in states that pll should be running*/ - uint32_t rtc_rdy_for_wakeup : 1; /*rtc is ready to receive wake up trigger from wake up source*/ - uint32_t rtc_main_state_wait_end : 1; /*rtc main state machine has been waited for some cycles*/ - uint32_t rtc_in_wakeup_state : 1; /*rtc main state machine is in the states of wakeup process*/ - uint32_t rtc_in_low_power_state : 1; /*rtc main state machine is in the states of low power*/ - uint32_t rtc_main_state_in_wait_8m : 1; /*rtc main state machine is in wait 8m state*/ - uint32_t rtc_main_state_in_wait_pll : 1; /*rtc main state machine is in wait pll state*/ - uint32_t rtc_main_state_in_wait_xtl : 1; /*rtc main state machine is in wait xtal state*/ - uint32_t rtc_main_state_in_slp : 1; /*rtc main state machine is in sleep state*/ - uint32_t rtc_main_state_in_idle : 1; /*rtc main state machine is in idle state*/ - uint32_t rtc_main_state : 4; /*rtc main state machine status*/ + uint32_t xpd_rom0: 1; /*rom0 power down*/ + uint32_t reserved1: 1; + uint32_t xpd_dig_dcdc: 1; /*External DCDC power down*/ + uint32_t rtc_peri_iso: 1; /*rtc peripheral iso*/ + uint32_t xpd_rtc_peri: 1; /*rtc peripheral power down*/ + uint32_t wifi_iso: 1; /*wifi iso*/ + uint32_t xpd_wifi: 1; /*wifi wrap power down*/ + uint32_t dig_iso: 1; /*digital wrap iso*/ + uint32_t xpd_dig: 1; /*digital wrap power down*/ + uint32_t rtc_touch_state_start: 1; /*touch should start to work*/ + uint32_t rtc_touch_state_switch: 1; /*touch is about to working. Switch rtc main state*/ + uint32_t rtc_touch_state_slp: 1; /*touch is in sleep state*/ + uint32_t rtc_touch_state_done: 1; /*touch is done*/ + uint32_t rtc_cocpu_state_start: 1; /*ulp/cocpu should start to work*/ + uint32_t rtc_cocpu_state_switch: 1; /*ulp/cocpu is about to working. Switch rtc main state*/ + uint32_t rtc_cocpu_state_slp: 1; /*ulp/cocpu is in sleep state*/ + uint32_t rtc_cocpu_state_done: 1; /*ulp/cocpu is done*/ + uint32_t rtc_main_state_xtal_iso: 1; /*no use any more*/ + uint32_t rtc_main_state_pll_on: 1; /*rtc main state machine is in states that pll should be running*/ + uint32_t rtc_rdy_for_wakeup: 1; /*rtc is ready to receive wake up trigger from wake up source*/ + uint32_t rtc_main_state_wait_end: 1; /*rtc main state machine has been waited for some cycles*/ + uint32_t rtc_in_wakeup_state: 1; /*rtc main state machine is in the states of wakeup process*/ + uint32_t rtc_in_low_power_state: 1; /*rtc main state machine is in the states of low power*/ + uint32_t rtc_main_state_in_wait_8m: 1; /*rtc main state machine is in wait 8m state*/ + uint32_t rtc_main_state_in_wait_pll: 1; /*rtc main state machine is in wait pll state*/ + uint32_t rtc_main_state_in_wait_xtl: 1; /*rtc main state machine is in wait xtal state*/ + uint32_t rtc_main_state_in_slp: 1; /*rtc main state machine is in sleep state*/ + uint32_t rtc_main_state_in_idle: 1; /*rtc main state machine is in idle state*/ + uint32_t rtc_main_state: 4; /*rtc main state machine status*/ }; uint32_t val; } low_power_st; - uint32_t diag0; + uint32_t diag0; /**/ union { struct { - uint32_t touch_pad0_hold : 1; - uint32_t touch_pad1_hold : 1; - uint32_t touch_pad2_hold : 1; - uint32_t touch_pad3_hold : 1; - uint32_t touch_pad4_hold : 1; - uint32_t touch_pad5_hold : 1; - uint32_t touch_pad6_hold : 1; - uint32_t touch_pad7_hold : 1; - uint32_t touch_pad8_hold : 1; - uint32_t touch_pad9_hold : 1; - uint32_t touch_pad10_hold : 1; - uint32_t touch_pad11_hold : 1; - uint32_t touch_pad12_hold : 1; - uint32_t touch_pad13_hold : 1; - uint32_t touch_pad14_hold : 1; - uint32_t x32p_hold : 1; - uint32_t x32n_hold : 1; - uint32_t pdac1_hold : 1; - uint32_t pdac2_hold : 1; - uint32_t rtc_pad19_hold : 1; - uint32_t rtc_pad20_hold : 1; - uint32_t rtc_pad21_hold : 1; - uint32_t reserved22 : 10; + uint32_t touch_pad0_hold: 1; + uint32_t touch_pad1_hold: 1; + uint32_t touch_pad2_hold: 1; + uint32_t touch_pad3_hold: 1; + uint32_t touch_pad4_hold: 1; + uint32_t touch_pad5_hold: 1; + uint32_t touch_pad6_hold: 1; + uint32_t touch_pad7_hold: 1; + uint32_t touch_pad8_hold: 1; + uint32_t touch_pad9_hold: 1; + uint32_t touch_pad10_hold: 1; + uint32_t touch_pad11_hold: 1; + uint32_t touch_pad12_hold: 1; + uint32_t touch_pad13_hold: 1; + uint32_t touch_pad14_hold: 1; + uint32_t x32p_hold: 1; + uint32_t x32n_hold: 1; + uint32_t pdac1_hold: 1; + uint32_t pdac2_hold: 1; + uint32_t rtc_pad19_hold: 1; + uint32_t rtc_pad20_hold: 1; + uint32_t rtc_pad21_hold: 1; + uint32_t reserved22: 10; }; uint32_t val; } pad_hold; - uint32_t dig_pad_hold; + uint32_t dig_pad_hold; /**/ union { struct { - uint32_t ext_wakeup1_sel : 22; /*Bitmap to select RTC pads for ext wakeup1*/ - uint32_t ext_wakeup1_status_clr : 1; /*clear ext wakeup1 status*/ - uint32_t reserved23 : 9; + uint32_t sel: 22; /*Bitmap to select RTC pads for ext wakeup1*/ + uint32_t status_clr: 1; /*clear ext wakeup1 status*/ + uint32_t reserved23: 9; }; uint32_t val; } ext_wakeup1; union { struct { - uint32_t ext_wakeup1_status : 22; /*ext wakeup1 status*/ - uint32_t reserved22 : 10; + uint32_t status: 22; /*ext wakeup1 status*/ + uint32_t reserved22: 10; }; uint32_t val; } ext_wakeup1_status; union { struct { - uint32_t reserved0 : 4; - uint32_t int_wait : 10; /*brown out interrupt wait cycles*/ - uint32_t close_flash_ena : 1; /*enable close flash when brown out happens*/ - uint32_t pd_rf_ena : 1; /*enable power down RF when brown out happens*/ - uint32_t rst_wait : 10; /*brown out reset wait cycles*/ - uint32_t rst_ena : 1; /*enable brown out reset*/ - uint32_t rst_sel : 1; /*1: 4-pos reset*/ - uint32_t ana_rst_en : 1; - uint32_t cnt_clr : 1; /*clear brown out counter*/ - uint32_t ena : 1; /*enable brown out*/ - uint32_t det : 1; + uint32_t reserved0: 4; + uint32_t int_wait: 10; /*brown out interrupt wait cycles*/ + uint32_t close_flash_ena: 1; /*enable close flash when brown out happens*/ + uint32_t pd_rf_ena: 1; /*enable power down RF when brown out happens*/ + uint32_t rst_wait: 10; /*brown out reset wait cycles*/ + uint32_t rst_ena: 1; /*enable brown out reset*/ + uint32_t rst_sel: 1; /*1: 4-pos reset*/ + uint32_t ana_rst_en: 1; + uint32_t cnt_clr: 1; /*clear brown out counter*/ + uint32_t ena: 1; /*enable brown out*/ + uint32_t det: 1; }; uint32_t val; } brown_out; - uint32_t time_low1; + uint32_t time_low1; /*RTC timer low 32 bits*/ union { struct { - uint32_t rtc_timer_value1_high : 16; /*RTC timer high 16 bits*/ - uint32_t reserved16 : 16; + uint32_t rtc_timer_value1_high:16; /*RTC timer high 16 bits*/ + uint32_t reserved16: 16; }; uint32_t val; } time_high1; - uint32_t xtal32k_clk_factor; + uint32_t xtal32k_clk_factor; /*xtal 32k watch dog backup clock factor*/ union { struct { - uint32_t xtal32k_return_wait : 4; /*cycles to wait to return noral xtal 32k*/ - uint32_t xtal32k_restart_wait : 16; /*cycles to wait to repower on xtal 32k*/ - uint32_t xtal32k_wdt_timeout : 8; /*If no clock detected for this amount of time*/ - uint32_t xtal32k_stable_thres : 4; /*if restarted xtal32k period is smaller than this*/ + uint32_t xtal32k_return_wait: 4; /*cycles to wait to return noral xtal 32k*/ + uint32_t xtal32k_restart_wait:16; /*cycles to wait to repower on xtal 32k*/ + uint32_t xtal32k_wdt_timeout: 8; /*If no clock detected for this amount of time*/ + uint32_t xtal32k_stable_thres: 4; /*if restarted xtal32k period is smaller than this*/ }; uint32_t val; } xtal32k_conf; union { struct { - uint32_t ulp_cp_pc_init : 11; /*ULP-coprocessor PC initial address*/ - uint32_t reserved11 : 18; - uint32_t ulp_cp_gpio_wakeup_ena : 1; /*ULP-coprocessor wakeup by GPIO enable*/ - uint32_t ulp_cp_gpio_wakeup_clr : 1; /*ULP-coprocessor wakeup by GPIO state clear*/ - uint32_t ulp_cp_slp_timer_en : 1; /*ULP-coprocessor timer enable bit*/ + uint32_t ulp_cp_pc_init: 11; /*ULP-coprocessor PC initial address*/ + uint32_t reserved11: 18; + uint32_t ulp_cp_gpio_wakeup_ena: 1; /*ULP-coprocessor wakeup by GPIO enable*/ + uint32_t ulp_cp_gpio_wakeup_clr: 1; /*ULP-coprocessor wakeup by GPIO state clear*/ + uint32_t ulp_cp_slp_timer_en: 1; /*ULP-coprocessor timer enable bit*/ }; uint32_t val; } ulp_cp_timer; union { struct { - uint32_t ulp_cp_mem_addr_init : 11; - uint32_t ulp_cp_mem_addr_size : 11; - uint32_t ulp_cp_mem_offst_clr : 1; - uint32_t reserved23 : 5; - uint32_t ulp_cp_clk_fo : 1; /*ulp coprocessor clk force on*/ - uint32_t ulp_cp_reset : 1; /*ulp coprocessor clk software reset*/ - uint32_t ulp_cp_force_start_top : 1; /*1: ULP-coprocessor is started by SW*/ - uint32_t ulp_cp_start_top : 1; /*Write 1 to start ULP-coprocessor*/ + uint32_t ulp_cp_mem_addr_init: 11; + uint32_t ulp_cp_mem_addr_size: 11; + uint32_t ulp_cp_mem_offst_clr: 1; + uint32_t reserved23: 5; + uint32_t ulp_cp_clk_fo: 1; /*ulp coprocessor clk force on*/ + uint32_t ulp_cp_reset: 1; /*ulp coprocessor clk software reset*/ + uint32_t ulp_cp_force_start_top: 1; /*1: ULP-coprocessor is started by SW*/ + uint32_t ulp_cp_start_top: 1; /*Write 1 to start ULP-coprocessor*/ }; uint32_t val; } ulp_cp_ctrl; union { struct { - uint32_t cocpu_clk_fo : 1; /*cocpu clk force on*/ - uint32_t cocpu_start_2_reset_dis : 6; /*time from start cocpu to pull down reset*/ - uint32_t cocpu_start_2_intr_en : 6; /*time from start cocpu to give start interrupt*/ - uint32_t cocpu_shut : 1; /*to shut cocpu*/ - uint32_t cocpu_shut_2_clk_dis : 8; /*time from shut cocpu to disable clk*/ - uint32_t cocpu_shut_reset_en : 1; /*to reset cocpu*/ - uint32_t cocpu_sel : 1; /*1: old ULP 0: new riscV*/ - uint32_t cocpu_done_force : 1; /*1: select riscv done 0: select ulp done*/ - uint32_t cocpu_done : 1; /*done signal used by riscv to control timer. */ - uint32_t cocpu_sw_int_trigger : 1; /*trigger cocpu register interrupt*/ - uint32_t cocpu_clkgate_en : 1; - uint32_t reserved28 : 4; + uint32_t cocpu_clk_fo: 1; /*cocpu clk force on*/ + uint32_t cocpu_start_2_reset_dis: 6; /*time from start cocpu to pull down reset*/ + uint32_t cocpu_start_2_intr_en: 6; /*time from start cocpu to give start interrupt*/ + uint32_t cocpu_shut: 1; /*to shut cocpu*/ + uint32_t cocpu_shut_2_clk_dis: 8; /*time from shut cocpu to disable clk*/ + uint32_t cocpu_shut_reset_en: 1; /*to reset cocpu*/ + uint32_t cocpu_sel: 1; /*1: old ULP 0: new riscV*/ + uint32_t cocpu_done_force: 1; /*1: select riscv done 0: select ulp done*/ + uint32_t cocpu_done: 1; /*done signal used by riscv to control timer.*/ + uint32_t cocpu_sw_int_trigger: 1; /*trigger cocpu register interrupt*/ + uint32_t cocpu_clkgate_en: 1; + uint32_t reserved28: 4; }; uint32_t val; } cocpu_ctrl; union { struct { - uint32_t touch_sleep_cycles : 16; /*sleep cycles for timer*/ - uint32_t touch_meas_num : 16; /*the meas length (in 8MHz)*/ + uint32_t touch_sleep_cycles:16; /*sleep cycles for timer*/ + uint32_t touch_meas_num: 16; /*the meas length (in 8MHz)*/ }; uint32_t val; } touch_ctrl1; union { struct { - uint32_t reserved0 : 2; - uint32_t touch_drange : 2; /*TOUCH_DRANGE*/ - uint32_t touch_drefl : 2; /*TOUCH_DREFL*/ - uint32_t touch_drefh : 2; /*TOUCH_DREFH*/ - uint32_t touch_xpd_bias : 1; /*TOUCH_XPD_BIAS*/ - uint32_t touch_refc : 3; /*TOUCH pad0 reference cap*/ - uint32_t touch_dbias : 1; /*1:use self bias 0:use bandgap bias*/ - uint32_t touch_slp_timer_en : 1; /*touch timer enable bit*/ - uint32_t touch_start_fsm_en : 1; /*1: TOUCH_START & TOUCH_XPD is controlled by touch fsm*/ - uint32_t touch_start_en : 1; /*1: start touch fsm*/ - uint32_t touch_start_force : 1; /*1: to start touch fsm by SW*/ - uint32_t touch_xpd_wait : 8; /*the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/ - uint32_t touch_slp_cyc_div : 2; /*when a touch pad is active*/ - uint32_t touch_timer_force_done : 2; /*force touch timer done*/ - uint32_t touch_reset : 1; /*reset upgrade touch*/ - uint32_t touch_clk_fo : 1; /*touch clock force on*/ - uint32_t touch_clkgate_en : 1; /*touch clock enable*/ + uint32_t reserved0: 2; + uint32_t touch_drange: 2; /*TOUCH_DRANGE*/ + uint32_t touch_drefl: 2; /*TOUCH_DREFL*/ + uint32_t touch_drefh: 2; /*TOUCH_DREFH*/ + uint32_t touch_xpd_bias: 1; /*TOUCH_XPD_BIAS*/ + uint32_t touch_refc: 3; /*TOUCH pad0 reference cap*/ + uint32_t touch_dbias: 1; /*1:use self bias 0:use bandgap bias*/ + uint32_t touch_slp_timer_en: 1; /*touch timer enable bit*/ + uint32_t touch_start_fsm_en: 1; /*1: TOUCH_START & TOUCH_XPD is controlled by touch fsm*/ + uint32_t touch_start_en: 1; /*1: start touch fsm*/ + uint32_t touch_start_force: 1; /*1: to start touch fsm by SW*/ + uint32_t touch_xpd_wait: 8; /*the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/ + uint32_t touch_slp_cyc_div: 2; /*when a touch pad is active*/ + uint32_t touch_timer_force_done: 2; /*force touch timer done*/ + uint32_t touch_reset: 1; /*reset upgrade touch*/ + uint32_t touch_clk_fo: 1; /*touch clock force on*/ + uint32_t touch_clkgate_en: 1; /*touch clock enable*/ }; uint32_t val; } touch_ctrl2; union { struct { - uint32_t touch_denoise_res : 2; /*De-noise resolution: 12/10/8/4 bit*/ - uint32_t touch_denoise_en : 1; /*touch pad0 will be used to de-noise*/ - uint32_t reserved3 : 5; - uint32_t touch_inactive_connection : 1; /*inactive touch pads connect to 1: gnd 0: HighZ*/ - uint32_t touch_shield_pad_en : 1; /*touch pad14 will be used as shield*/ - uint32_t touch_scan_pad_map : 15; /*touch scan mode pad enable map*/ - uint32_t touch_bufdrv : 3; /*touch7 buffer driver strength*/ - uint32_t touch_out_ring : 4; /*select out ring pad*/ + uint32_t touch_denoise_res: 2; /*De-noise resolution: 12/10/8/4 bit*/ + uint32_t touch_denoise_en: 1; /*touch pad0 will be used to de-noise*/ + uint32_t reserved3: 5; + uint32_t touch_inactive_connection: 1; /*inactive touch pads connect to 1: gnd 0: HighZ*/ + uint32_t touch_shield_pad_en: 1; /*touch pad14 will be used as shield*/ + uint32_t touch_scan_pad_map: 15; /*touch scan mode pad enable map*/ + uint32_t touch_bufdrv: 3; /*touch7 buffer driver strength*/ + uint32_t touch_out_ring: 4; /*select out ring pad*/ }; uint32_t val; } touch_scan_ctrl; union { struct { - uint32_t touch_slp_th : 22; /*the threshold for sleep touch pad*/ - uint32_t reserved22 : 4; - uint32_t touch_slp_approach_en : 1; /*sleep pad approach function enable*/ - uint32_t touch_slp_pad : 5; /* */ + uint32_t touch_slp_th: 22; /*the threshold for sleep touch pad*/ + uint32_t reserved22: 4; + uint32_t touch_slp_approach_en: 1; /*sleep pad approach function enable*/ + uint32_t touch_slp_pad: 5; }; uint32_t val; } touch_slp_thres; union { struct { - uint32_t reserved0 : 23; - uint32_t touch_slp_channel_clr : 1; /*clear touch slp channel*/ - uint32_t touch_approach_meas_time : 8; /*approach pads total meas times*/ + uint32_t reserved0: 23; + uint32_t touch_slp_channel_clr: 1; /*clear touch slp channel*/ + uint32_t touch_approach_meas_time: 8; /*approach pads total meas times*/ }; uint32_t val; } touch_approach; union { struct { - uint32_t reserved0 : 7; - uint32_t touch_bypass_neg_noise_thres : 1; - uint32_t touch_bypass_noise_thres : 1; - uint32_t touch_smooth_lvl : 2; - uint32_t touch_jitter_step : 4; /*touch jitter step*/ - uint32_t touch_neg_noise_limit : 4; /*negative threshold counter limit*/ - uint32_t touch_neg_noise_thres : 2; - uint32_t touch_noise_thres : 2; - uint32_t touch_hysteresis : 2; - uint32_t touch_debounce : 3; /*debounce counter*/ - uint32_t touch_filter_mode : 3; /*0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter*/ - uint32_t touch_filter_en : 1; /*touch filter enable*/ + uint32_t reserved0: 7; + uint32_t touch_bypass_neg_noise_thres: 1; + uint32_t touch_bypass_noise_thres: 1; + uint32_t touch_smooth_lvl: 2; + uint32_t touch_jitter_step: 4; /*touch jitter step*/ + uint32_t touch_neg_noise_limit: 4; /*negative threshold counter limit*/ + uint32_t touch_neg_noise_thres: 2; + uint32_t touch_noise_thres: 2; + uint32_t touch_hysteresis: 2; + uint32_t touch_debounce: 3; /*debounce counter*/ + uint32_t touch_filter_mode: 3; /*0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter*/ + uint32_t touch_filter_en: 1; /*touch filter enable*/ }; uint32_t val; } touch_filter_ctrl; union { struct { - uint32_t usb_vrefh : 2; - uint32_t usb_vrefl : 2; - uint32_t usb_vref_override : 1; - uint32_t usb_pad_pull_override : 1; - uint32_t usb_dp_pullup : 1; - uint32_t usb_dp_pulldown : 1; - uint32_t usb_dm_pullup : 1; - uint32_t usb_dm_pulldown : 1; - uint32_t usb_pullup_value : 1; - uint32_t usb_pad_enable_override : 1; - uint32_t usb_pad_enable : 1; - uint32_t usb_txm : 1; - uint32_t usb_txp : 1; - uint32_t usb_tx_en : 1; - uint32_t usb_tx_en_override : 1; - uint32_t usb_reset_disable : 1; - uint32_t io_mux_reset_disable : 1; - uint32_t reserved19 : 13; + uint32_t usb_vrefh: 2; + uint32_t usb_vrefl: 2; + uint32_t usb_vref_override: 1; + uint32_t usb_pad_pull_override: 1; + uint32_t usb_dp_pullup: 1; + uint32_t usb_dp_pulldown: 1; + uint32_t usb_dm_pullup: 1; + uint32_t usb_dm_pulldown: 1; + uint32_t usb_pullup_value: 1; + uint32_t usb_pad_enable_override: 1; + uint32_t usb_pad_enable: 1; + uint32_t usb_txm: 1; + uint32_t usb_txp: 1; + uint32_t usb_tx_en: 1; + uint32_t usb_tx_en_override: 1; + uint32_t usb_reset_disable: 1; + uint32_t io_mux_reset_disable: 1; + uint32_t reserved19: 13; }; uint32_t val; } usb_conf; union { struct { - uint32_t touch_timeout_num : 22; - uint32_t touch_timeout_en : 1; - uint32_t reserved23 : 9; + uint32_t touch_timeout_num:22; + uint32_t touch_timeout_en: 1; + uint32_t reserved23: 9; }; uint32_t val; } touch_timeout_ctrl; union { struct { - uint32_t reject_cause : 18; /*sleep reject cause*/ - uint32_t reserved18 : 14; + uint32_t reject_cause:18; /*sleep reject cause*/ + uint32_t reserved18: 14; }; uint32_t val; } slp_reject_cause; union { struct { - uint32_t force_download_boot : 1; - uint32_t reserved1 : 31; + uint32_t force_download_boot: 1; + uint32_t reserved1: 31; }; uint32_t val; } option1; union { struct { - uint32_t wakeup_cause : 17; /*sleep wakeup cause*/ - uint32_t reserved17 : 15; + uint32_t wakeup_cause:17; /*sleep wakeup cause*/ + uint32_t reserved17: 15; }; uint32_t val; } slp_wakeup_cause; union { struct { - uint32_t reserved0 : 8; - uint32_t ulp_cp_timer_slp_cycle : 24; /*sleep cycles for ULP-coprocessor timer*/ + uint32_t reserved0: 8; + uint32_t ulp_cp_timer_slp_cycle:24; /*sleep cycles for ULP-coprocessor timer*/ }; uint32_t val; } ulp_cp_timer_1; union { struct { - uint32_t slp_wakeup_w1ts : 1; /*enable sleep wakeup interrupt*/ - uint32_t slp_reject_w1ts : 1; /*enable sleep reject interrupt*/ - uint32_t sdio_idle_w1ts : 1; /*enable SDIO idle interrupt*/ - uint32_t rtc_wdt_w1ts : 1; /*enable RTC WDT interrupt*/ - uint32_t rtc_touch_scan_done_w1ts : 1; /*enable touch scan done interrupt*/ - uint32_t rtc_ulp_cp_w1ts : 1; /*enable ULP-coprocessor interrupt*/ - uint32_t rtc_touch_done_w1ts : 1; /*enable touch done interrupt*/ - uint32_t rtc_touch_active_w1ts : 1; /*enable touch active interrupt*/ - uint32_t rtc_touch_inactive_w1ts : 1; /*enable touch inactive interrupt*/ - uint32_t w1ts : 1; /*enable brown out interrupt*/ - uint32_t rtc_main_timer_w1ts : 1; /*enable RTC main timer interrupt*/ - uint32_t rtc_saradc1_w1ts : 1; /*enable saradc1 interrupt*/ - uint32_t rtc_tsens_w1ts : 1; /*enable tsens interrupt*/ - uint32_t rtc_cocpu_w1ts : 1; /*enable riscV cocpu interrupt*/ - uint32_t rtc_saradc2_w1ts : 1; /*enable saradc2 interrupt*/ - uint32_t rtc_swd_w1ts : 1; /*enable super watch dog interrupt*/ - uint32_t rtc_xtal32k_dead_w1ts : 1; /*enable xtal32k_dead interrupt*/ - uint32_t rtc_cocpu_trap_w1ts : 1; /*enable cocpu trap interrupt*/ - uint32_t rtc_touch_timeout_w1ts : 1; /*enable touch timeout interrupt*/ - uint32_t rtc_glitch_det_w1ts : 1; /*enbale gitch det interrupt*/ - uint32_t rtc_touch_approach_loop_done_w1ts: 1; - uint32_t reserved21 : 11; + uint32_t slp_wakeup_w1ts: 1; /*enable sleep wakeup interrupt*/ + uint32_t slp_reject_w1ts: 1; /*enable sleep reject interrupt*/ + uint32_t sdio_idle_w1ts: 1; /*enable SDIO idle interrupt*/ + uint32_t rtc_wdt_w1ts: 1; /*enable RTC WDT interrupt*/ + uint32_t rtc_touch_scan_done_w1ts: 1; /*enable touch scan done interrupt*/ + uint32_t rtc_ulp_cp_w1ts: 1; /*enable ULP-coprocessor interrupt*/ + uint32_t rtc_touch_done_w1ts: 1; /*enable touch done interrupt*/ + uint32_t rtc_touch_active_w1ts: 1; /*enable touch active interrupt*/ + uint32_t rtc_touch_inactive_w1ts: 1; /*enable touch inactive interrupt*/ + uint32_t w1ts: 1; /*enable brown out interrupt*/ + uint32_t rtc_main_timer_w1ts: 1; /*enable RTC main timer interrupt*/ + uint32_t rtc_saradc1_w1ts: 1; /*enable saradc1 interrupt*/ + uint32_t rtc_tsens_w1ts: 1; /*enable tsens interrupt*/ + uint32_t rtc_cocpu_w1ts: 1; /*enable riscV cocpu interrupt*/ + uint32_t rtc_saradc2_w1ts: 1; /*enable saradc2 interrupt*/ + uint32_t rtc_swd_w1ts: 1; /*enable super watch dog interrupt*/ + uint32_t rtc_xtal32k_dead_w1ts: 1; /*enable xtal32k_dead interrupt*/ + uint32_t rtc_cocpu_trap_w1ts: 1; /*enable cocpu trap interrupt*/ + uint32_t rtc_touch_timeout_w1ts: 1; /*enable touch timeout interrupt*/ + uint32_t rtc_glitch_det_w1ts: 1; /*enbale gitch det interrupt*/ + uint32_t rtc_touch_approach_loop_done_w1ts: 1; + uint32_t reserved21: 11; }; uint32_t val; } int_ena_w1ts; union { struct { - uint32_t slp_wakeup_w1tc : 1; /*enable sleep wakeup interrupt*/ - uint32_t slp_reject_w1tc : 1; /*enable sleep reject interrupt*/ - uint32_t sdio_idle_w1tc : 1; /*enable SDIO idle interrupt*/ - uint32_t rtc_wdt_w1tc : 1; /*enable RTC WDT interrupt*/ - uint32_t rtc_touch_scan_done_w1tc : 1; /*enable touch scan done interrupt*/ - uint32_t rtc_ulp_cp_w1tc : 1; /*enable ULP-coprocessor interrupt*/ - uint32_t rtc_touch_done_w1tc : 1; /*enable touch done interrupt*/ - uint32_t rtc_touch_active_w1tc : 1; /*enable touch active interrupt*/ - uint32_t rtc_touch_inactive_w1tc : 1; /*enable touch inactive interrupt*/ - uint32_t w1tc : 1; /*enable brown out interrupt*/ - uint32_t rtc_main_timer_w1tc : 1; /*enable RTC main timer interrupt*/ - uint32_t rtc_saradc1_w1tc : 1; /*enable saradc1 interrupt*/ - uint32_t rtc_tsens_w1tc : 1; /*enable tsens interrupt*/ - uint32_t rtc_cocpu_w1tc : 1; /*enable riscV cocpu interrupt*/ - uint32_t rtc_saradc2_w1tc : 1; /*enable saradc2 interrupt*/ - uint32_t rtc_swd_w1tc : 1; /*enable super watch dog interrupt*/ - uint32_t rtc_xtal32k_dead_w1tc : 1; /*enable xtal32k_dead interrupt*/ - uint32_t rtc_cocpu_trap_w1tc : 1; /*enable cocpu trap interrupt*/ - uint32_t rtc_touch_timeout_w1tc : 1; /*enable touch timeout interrupt*/ - uint32_t rtc_glitch_det_w1tc : 1; /*enbale gitch det interrupt*/ - uint32_t rtc_touch_approach_loop_done_w1tc: 1; - uint32_t reserved21 : 11; + uint32_t slp_wakeup_w1tc: 1; /*enable sleep wakeup interrupt*/ + uint32_t slp_reject_w1tc: 1; /*enable sleep reject interrupt*/ + uint32_t sdio_idle_w1tc: 1; /*enable SDIO idle interrupt*/ + uint32_t rtc_wdt_w1tc: 1; /*enable RTC WDT interrupt*/ + uint32_t rtc_touch_scan_done_w1tc: 1; /*enable touch scan done interrupt*/ + uint32_t rtc_ulp_cp_w1tc: 1; /*enable ULP-coprocessor interrupt*/ + uint32_t rtc_touch_done_w1tc: 1; /*enable touch done interrupt*/ + uint32_t rtc_touch_active_w1tc: 1; /*enable touch active interrupt*/ + uint32_t rtc_touch_inactive_w1tc: 1; /*enable touch inactive interrupt*/ + uint32_t w1tc: 1; /*enable brown out interrupt*/ + uint32_t rtc_main_timer_w1tc: 1; /*enable RTC main timer interrupt*/ + uint32_t rtc_saradc1_w1tc: 1; /*enable saradc1 interrupt*/ + uint32_t rtc_tsens_w1tc: 1; /*enable tsens interrupt*/ + uint32_t rtc_cocpu_w1tc: 1; /*enable riscV cocpu interrupt*/ + uint32_t rtc_saradc2_w1tc: 1; /*enable saradc2 interrupt*/ + uint32_t rtc_swd_w1tc: 1; /*enable super watch dog interrupt*/ + uint32_t rtc_xtal32k_dead_w1tc: 1; /*enable xtal32k_dead interrupt*/ + uint32_t rtc_cocpu_trap_w1tc: 1; /*enable cocpu trap interrupt*/ + uint32_t rtc_touch_timeout_w1tc: 1; /*enable touch timeout interrupt*/ + uint32_t rtc_glitch_det_w1tc: 1; /*enbale gitch det interrupt*/ + uint32_t rtc_touch_approach_loop_done_w1tc: 1; + uint32_t reserved21: 11; }; uint32_t val; } int_ena_w1tc; union { struct { - uint32_t reserved0 : 26; - uint32_t retention_en : 1; - uint32_t retention_wait : 5; /*wait cycles for rention operation*/ + uint32_t reserved0: 18; + uint32_t retention_clk_sel: 1; + uint32_t retention_done_wait: 3; + uint32_t retention_clkoff_wait: 4; + uint32_t retention_en: 1; + uint32_t retention_wait: 5; /*wait cycles for rention operation*/ }; uint32_t val; } retention_ctrl; union { struct { - uint32_t rtc_fib_sel : 3; /*select use analog fib signal*/ - uint32_t reserved3 : 29; + uint32_t rtc_fib_sel: 3; /*select use analog fib signal*/ + uint32_t reserved3: 29; }; uint32_t val; } fib_sel; union { struct { - uint32_t date : 28; - uint32_t reserved28 : 4; + uint32_t date: 28; + uint32_t reserved28: 4; }; uint32_t val; } date; @@ -965,6 +947,4 @@ extern rtc_cntl_dev_t RTCCNTL; } #endif - - -#endif /*_SOC_RTC_CNTL_STRUCT_H_ */ +#endif /* _SOC_RTC_CNTL_STRUCT_H_ */