diff --git a/components/efuse/esp32s3/esp_efuse_table.c b/components/efuse/esp32s3/esp_efuse_table.c index 0b71165ba9..b2a99a0b83 100644 --- a/components/efuse/esp32s3/esp_efuse_table.c +++ b/components/efuse/esp32s3/esp_efuse_table.c @@ -9,7 +9,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table 8c7a031bb0def28f2123ac5ee2a48d43 +// md5_digest_table 87c5ae68b74dbafb114e14f6febff9e2 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -549,6 +549,26 @@ static const esp_efuse_desc_t SYS_DATA_PART2[] = { {EFUSE_BLK10, 0, 256}, // System configuration, }; +static const esp_efuse_desc_t K_RTC_LDO[] = { + {EFUSE_BLK1, 141, 7}, // BLOCK1 K_RTC_LDO, +}; + +static const esp_efuse_desc_t K_DIG_LDO[] = { + {EFUSE_BLK1, 148, 7}, // BLOCK1 K_DIG_LDO, +}; + +static const esp_efuse_desc_t V_RTC_DBIAS20[] = { + {EFUSE_BLK1, 155, 8}, // BLOCK1 voltage of rtc dbias20, +}; + +static const esp_efuse_desc_t V_DIG_DBIAS20[] = { + {EFUSE_BLK1, 163, 8}, // BLOCK1 voltage of digital dbias20, +}; + +static const esp_efuse_desc_t DIG_DBIAS_HVT[] = { + {EFUSE_BLK1, 171, 5}, // BLOCK1 digital dbias when hvt, +}; + @@ -1218,3 +1238,28 @@ const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = { &SYS_DATA_PART2[0], // System configuration NULL }; + +const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[] = { + &K_RTC_LDO[0], // BLOCK1 K_RTC_LDO + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[] = { + &K_DIG_LDO[0], // BLOCK1 K_DIG_LDO + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[] = { + &V_RTC_DBIAS20[0], // BLOCK1 voltage of rtc dbias20 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[] = { + &V_DIG_DBIAS20[0], // BLOCK1 voltage of digital dbias20 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[] = { + &DIG_DBIAS_HVT[0], // BLOCK1 digital dbias when hvt + NULL +}; diff --git a/components/efuse/esp32s3/esp_efuse_table.csv b/components/efuse/esp32s3/esp_efuse_table.csv index f7df89471d..8efee7c24b 100644 --- a/components/efuse/esp32s3/esp_efuse_table.csv +++ b/components/efuse/esp32s3/esp_efuse_table.csv @@ -183,3 +183,11 @@ KEY3, EFUSE_BLK7, 0, 256, Key3 or us KEY4, EFUSE_BLK8, 0, 256, Key4 or user data KEY5, EFUSE_BLK9, 0, 256, Key5 or user data SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration + +# AUTO CONFIG DIG&RTC DBIAS# +################ +K_RTC_LDO, EFUSE_BLK1, 141, 7, BLOCK1 K_RTC_LDO +K_DIG_LDO, EFUSE_BLK1, 148, 7, BLOCK1 K_DIG_LDO +V_RTC_DBIAS20, EFUSE_BLK1, 155, 8, BLOCK1 voltage of rtc dbias20 +V_DIG_DBIAS20, EFUSE_BLK1, 163, 8, BLOCK1 voltage of digital dbias20 +DIG_DBIAS_HVT, EFUSE_BLK1, 171, 5, BLOCK1 digital dbias when hvt diff --git a/components/efuse/esp32s3/include/esp_efuse_table.h b/components/efuse/esp32s3/include/esp_efuse_table.h index 2f347c4341..93be6aae49 100644 --- a/components/efuse/esp32s3/include/esp_efuse_table.h +++ b/components/efuse/esp32s3/include/esp_efuse_table.h @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table 8c7a031bb0def28f2123ac5ee2a48d43 +// md5_digest_table 87c5ae68b74dbafb114e14f6febff9e2 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -149,6 +149,11 @@ extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[]; extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[]; #ifdef __cplusplus } diff --git a/components/esp_hw_support/port/esp32s3/rtc_clk.c b/components/esp_hw_support/port/esp32s3/rtc_clk.c index 39c33ec6ec..d595ca20e2 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_clk.c +++ b/components/esp_hw_support/port/esp32s3/rtc_clk.c @@ -30,10 +30,15 @@ static uint32_t s_cur_pll_freq; static uint32_t s_apb_freq; -static void rtc_clk_cpu_freq_to_xtal(int freq, int div); +void rtc_clk_cpu_freq_to_xtal(int freq, int div); static void rtc_clk_cpu_freq_to_8m(void); static bool rtc_clk_set_bbpll_always_on(void); +extern uint32_t g_dig_dbias_pvt_240m; +extern uint32_t g_rtc_dbias_pvt_240m; +extern uint32_t g_dig_dbias_pvt_non_240m; +extern uint32_t g_rtc_dbias_pvt_non_240m; + void rtc_clk_32k_enable(bool enable) { if (enable) { @@ -94,18 +99,6 @@ bool rtc_clk_8md256_enabled(void) return clk_ll_rc_fast_d256_is_enabled(); } -static void wait_dig_dbias_valid(uint64_t rtc_cycles) -{ - soc_rtc_slow_clk_src_t slow_clk_freq = rtc_clk_slow_src_get(); - rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX; - if (slow_clk_freq == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { - cal_clk = RTC_CAL_32K_XTAL; - } else if (slow_clk_freq == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) { - cal_clk = RTC_CAL_8MD256; - } - rtc_clk_cal(cal_clk, rtc_cycles); -} - void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src) { clk_ll_rtc_slow_set_src(clk_src); @@ -182,17 +175,45 @@ static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq) */ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) { - int dbias = (cpu_freq_mhz == 240) ? DIG_DBIAS_240M : DIG_DBIAS_80M_160M; - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, dbias); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, dbias); - wait_dig_dbias_valid(2); + /* cpu_frequency < 240M: dbias = pvt-dig + 2; + cpu_frequency = 240M: dbias = pvt-dig + 3; + */ + if (cpu_freq_mhz != 240) { + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_non_240m); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_non_240m); + } else { + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_240m); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_240m); + } + esp_rom_delay_us(40); - clk_ll_cpu_set_freq_mhz_from_pll(cpu_freq_mhz); - clk_ll_cpu_set_divider(1); - /* switch clock source */ - clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL); - rtc_clk_apb_freq_update(80 * MHZ); - ets_update_cpu_frequency(cpu_freq_mhz); + /* There are totally 6 LDO slaves(all on by default). At the moment of swithing LDO slave, LDO voltage will also change instantaneously. + * LDO slave can reduce the voltage change caused by switching frequency. + * CPU frequency <= 40M : just open 3 LDO slaves; CPU frequency = 80M : open 4 LDO slaves; CPU frequency = 160M : open 5 LDO slaves; CPU frequency = 240M : open 6 LDO slaves; + * + * LDO voltage will decrease at the moment of switching from low frequency to high frequency; otherwise, LDO voltage will increase. + * In order to reduce LDO voltage drop, LDO voltage should rise first then fall. + */ + int pd_slave = cpu_freq_mhz / 80; + rtc_cpu_freq_config_t cur_config; + rtc_clk_cpu_freq_get_config(&cur_config); + if (cpu_freq_mhz > cur_config.freq_mhz) { + REG_SET_FIELD(RTC_CNTL_DATE_REG, RTC_CNTL_SLAVE_PD, DEFAULT_LDO_SLAVE >> pd_slave); + clk_ll_cpu_set_freq_mhz_from_pll(cpu_freq_mhz); + clk_ll_cpu_set_divider(1); + /* switch clock source */ + clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL); + rtc_clk_apb_freq_update(80 * MHZ); + ets_update_cpu_frequency(cpu_freq_mhz); + } else { + clk_ll_cpu_set_freq_mhz_from_pll(cpu_freq_mhz); + clk_ll_cpu_set_divider(1); + /* switch clock source */ + clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL); + rtc_clk_apb_freq_update(80 * MHZ); + ets_update_cpu_frequency(cpu_freq_mhz); + REG_SET_FIELD(RTC_CNTL_DATE_REG, RTC_CNTL_SLAVE_PD, DEFAULT_LDO_SLAVE >> pd_slave); + } } bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config) @@ -336,30 +357,33 @@ void rtc_clk_cpu_freq_set_xtal(void) /** * Switch to XTAL frequency. Does not disable the PLL. + * Public function for testing only. */ -static void rtc_clk_cpu_freq_to_xtal(int freq, int div) +void rtc_clk_cpu_freq_to_xtal(int freq, int div) { + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_non_240m); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_non_240m); + esp_rom_delay_us(40); ets_update_cpu_frequency(freq); - /* set digital voltage for different cpu freq from xtal */ - int dbias = (freq <= 2) ? DIG_DBIAS_2M : DIG_DBIAS_XTAL; - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, dbias); - wait_dig_dbias_valid(2); /* Set divider from XTAL to APB clock. Need to set divider to 1 (reg. value 0) first. */ clk_ll_cpu_set_divider(1); clk_ll_cpu_set_divider(div); /* switch clock source */ clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL); rtc_clk_apb_freq_update(freq * MHZ); + REG_SET_FIELD(RTC_CNTL_DATE_REG, RTC_CNTL_SLAVE_PD, DEFAULT_LDO_SLAVE); } static void rtc_clk_cpu_freq_to_8m(void) { ets_update_cpu_frequency(20); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, DIG_DBIAS_XTAL); - wait_dig_dbias_valid(2); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_non_240m); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_non_240m); + esp_rom_delay_us(40); clk_ll_cpu_set_divider(1); clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST); rtc_clk_apb_freq_update(SOC_CLK_RC_FAST_FREQ_APPROX); + REG_SET_FIELD(RTC_CNTL_DATE_REG, RTC_CNTL_SLAVE_PD, DEFAULT_LDO_SLAVE); } rtc_xtal_freq_t rtc_clk_xtal_freq_get(void) diff --git a/components/esp_hw_support/port/esp32s3/rtc_init.c b/components/esp_hw_support/port/esp32s3/rtc_init.c index 266e330c15..b4e364594f 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_init.c +++ b/components/esp_hw_support/port/esp32s3/rtc_init.c @@ -24,7 +24,7 @@ #include "esp_efuse.h" #include "esp_efuse_table.h" #include "esp_private/spi_flash_os.h" - +#include "hal/efuse_hal.h" #define RTC_CNTL_MEM_FORCE_NOISO (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO) @@ -32,6 +32,13 @@ static const char *TAG = "rtcinit"; static void set_ocode_by_efuse(int calib_version); static void calibrate_ocode(void); +static void rtc_set_stored_dbias(void); + +// Initial values are used for bootloader, and these variables will be re-assigned based on efuse values during application startup +uint32_t g_dig_dbias_pvt_240m = 28; +uint32_t g_rtc_dbias_pvt_240m = 28; +uint32_t g_dig_dbias_pvt_non_240m = 27; +uint32_t g_rtc_dbias_pvt_non_240m = 27; void rtc_init(rtc_config_t cfg) { @@ -89,6 +96,12 @@ void rtc_init(rtc_config_t cfg) } } + //LDO dbias initialization + rtc_set_stored_dbias(); + + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_non_240m); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_non_240m); + if (cfg.clkctl_init) { //clear CMMU clock force on CLEAR_PERI_REG_MASK(EXTMEM_CACHE_MMU_POWER_CTRL_REG, EXTMEM_CACHE_MMU_MEM_FORCE_ON); @@ -301,3 +314,116 @@ static void calibrate_ocode(void) spi_timing_change_speed_mode_cache_safe(false); #endif } + +static uint32_t get_dig_dbias_by_efuse(uint8_t pvt_scheme_ver) +{ + assert(pvt_scheme_ver == 1); + uint32_t dig_dbias = 28; + esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_DIG_DBIAS_HVT, &dig_dbias, ESP_EFUSE_DIG_DBIAS_HVT[0]->bit_count); + if (err != ESP_OK) { + dig_dbias = 28; + ESP_HW_LOGW(TAG, "efuse read fail, set default dig_dbias value: %d\n", dig_dbias); + } + return dig_dbias; +} + +static uint32_t get_rtc_dbias_by_efuse(uint8_t pvt_scheme_ver, uint32_t dig_dbias) +{ + assert(pvt_scheme_ver == 1); + uint32_t rtc_dbias = 0; + signed int k_rtc_ldo = 0, k_dig_ldo = 0, v_rtc_bias20 = 0, v_dig_bias20 = 0; + esp_err_t err0 = esp_efuse_read_field_blob(ESP_EFUSE_K_RTC_LDO, &k_rtc_ldo, ESP_EFUSE_K_RTC_LDO[0]->bit_count); + esp_err_t err1 = esp_efuse_read_field_blob(ESP_EFUSE_K_DIG_LDO, &k_dig_ldo, ESP_EFUSE_K_DIG_LDO[0]->bit_count); + esp_err_t err2 = esp_efuse_read_field_blob(ESP_EFUSE_V_RTC_DBIAS20, &v_rtc_bias20, ESP_EFUSE_V_RTC_DBIAS20[0]->bit_count); + esp_err_t err3 = esp_efuse_read_field_blob(ESP_EFUSE_V_DIG_DBIAS20, &v_dig_bias20, ESP_EFUSE_V_DIG_DBIAS20[0]->bit_count); + if ((err0 != ESP_OK) | (err1 != ESP_OK) | (err2 != ESP_OK) | (err3 != ESP_OK)) { + k_rtc_ldo = 0; + k_dig_ldo = 0; + v_rtc_bias20 = 0; + v_dig_bias20 = 0; + ESP_HW_LOGW(TAG, "efuse read fail, k_rtc_ldo: %d, k_dig_ldo: %d, v_rtc_bias20: %d, v_dig_bias20: %d\n", k_rtc_ldo, k_dig_ldo, v_rtc_bias20, v_dig_bias20); + } + + k_rtc_ldo = ((k_rtc_ldo & BIT(6)) != 0)? -(k_rtc_ldo & 0x3f): (uint8_t)k_rtc_ldo; + k_dig_ldo = ((k_dig_ldo & BIT(6)) != 0)? -(k_dig_ldo & 0x3f): (uint8_t)k_dig_ldo; + v_rtc_bias20 = ((v_rtc_bias20 & BIT(7)) != 0)? -(v_rtc_bias20 & 0x7f): (uint8_t)v_rtc_bias20; + v_dig_bias20 = ((v_dig_bias20 & BIT(7)) != 0)? -(v_dig_bias20 & 0x7f): (uint8_t)v_dig_bias20; + + uint32_t v_rtc_dbias20_real_mul10000 = V_RTC_MID_MUL10000 + v_rtc_bias20 * 10000 / 500; + uint32_t v_dig_dbias20_real_mul10000 = V_DIG_MID_MUL10000 + v_dig_bias20 * 10000 / 500; + signed int k_rtc_ldo_real_mul10000 = K_RTC_MID_MUL10000 + k_rtc_ldo; + signed int k_dig_ldo_real_mul10000 = K_DIG_MID_MUL10000 + k_dig_ldo; + uint32_t v_dig_nearest_1v15_mul10000 = v_dig_dbias20_real_mul10000 + k_dig_ldo_real_mul10000 * (dig_dbias - 20); + for (rtc_dbias = 15; rtc_dbias < 31; rtc_dbias++) { + uint32_t v_rtc_nearest_1v15_mul10000 = 0; + v_rtc_nearest_1v15_mul10000 = v_rtc_dbias20_real_mul10000 + k_rtc_ldo_real_mul10000 * (rtc_dbias - 20); + if (v_rtc_nearest_1v15_mul10000 >= v_dig_nearest_1v15_mul10000 - 250) { + break; + } + } + return rtc_dbias; +} + +static uint32_t get_dig1v3_dbias_by_efuse(uint8_t pvt_scheme_ver) +{ + assert(pvt_scheme_ver == 1); + signed int k_dig_ldo = 0, v_dig_bias20 = 0; + esp_err_t err0 = esp_efuse_read_field_blob(ESP_EFUSE_K_DIG_LDO, &k_dig_ldo, ESP_EFUSE_K_DIG_LDO[0]->bit_count); + esp_err_t err1 = esp_efuse_read_field_blob(ESP_EFUSE_V_DIG_DBIAS20, &v_dig_bias20, ESP_EFUSE_V_DIG_DBIAS20[0]->bit_count); + if ((err0 != ESP_OK) | (err1 != ESP_OK)) { + k_dig_ldo = 0; + v_dig_bias20 = 0; + ESP_HW_LOGW(TAG, "efuse read fail, k_dig_ldo: %d, v_dig_bias20: %d\n", k_dig_ldo, v_dig_bias20); + } + + k_dig_ldo = ((k_dig_ldo & BIT(6)) != 0)? -(k_dig_ldo & 0x3f): (uint8_t)k_dig_ldo; + v_dig_bias20 = ((v_dig_bias20 & BIT(7)) != 0)? -(v_dig_bias20 & 0x7f): (uint8_t)v_dig_bias20; + + uint32_t v_dig_dbias20_real_mul10000 = V_DIG_MID_MUL10000 + v_dig_bias20 * 10000 / 500; + signed int k_dig_ldo_real_mul10000 = K_DIG_MID_MUL10000 + k_dig_ldo; + uint32_t dig_dbias =15; + for (dig_dbias = 15; dig_dbias < 31; dig_dbias++) { + uint32_t v_dig_nearest_1v3_mul10000 = 0; + v_dig_nearest_1v3_mul10000 = v_dig_dbias20_real_mul10000 + k_dig_ldo_real_mul10000 * (dig_dbias - 20); + if (v_dig_nearest_1v3_mul10000 >= 13000) { + break; + } + } + return dig_dbias; +} + +static void rtc_set_stored_dbias(void) +{ + /* + 1. a reasonable dig_dbias which by scaning pvt to make 240 CPU run successful stored in efuse; + 2. also we store some value in efuse, include: + k_rtc_ldo (slope of rtc voltage & rtc_dbias); + k_dig_ldo (slope of digital voltage & digital_dbias); + v_rtc_bias20 (rtc voltage when rtc dbais is 20); + v_dig_bias20 (digital voltage when digital dbais is 20). + 3. a reasonable rtc_dbias can be calculated by a certion formula. + 4. save these values for reuse + */ + uint8_t blk_minor = efuse_ll_get_blk_version_minor(); + uint8_t blk_major = efuse_ll_get_blk_version_major(); + uint8_t pvt_scheme_ver = 0; + if ( (blk_major <= 1 && blk_minor == 1) || blk_major > 1 || (blk_major == 1 && blk_minor >= 2) ) { + /* PVT supported after blk_ver 1.2 */ + pvt_scheme_ver = 1; + } + + if (pvt_scheme_ver == 1) { + uint32_t dig1v3_dbias = get_dig1v3_dbias_by_efuse(pvt_scheme_ver); + uint32_t dig_dbias = get_dig_dbias_by_efuse(pvt_scheme_ver); + if (dig_dbias != 0) { + g_dig_dbias_pvt_240m = MIN(dig1v3_dbias, dig_dbias + 3); + g_dig_dbias_pvt_non_240m = MIN(dig1v3_dbias, dig_dbias + 2); + g_rtc_dbias_pvt_240m = get_rtc_dbias_by_efuse(pvt_scheme_ver, g_dig_dbias_pvt_240m); + g_rtc_dbias_pvt_non_240m = get_rtc_dbias_by_efuse(pvt_scheme_ver, g_dig_dbias_pvt_non_240m); + } else { + ESP_HW_LOGD(TAG, "not burn core voltage in efuse or burn wrong voltage value in blk version: 0%d\n", pvt_scheme_ver); + } + } else { + ESP_HW_LOGD(TAG, "core voltage not decided in efuse, use default value."); + } +} diff --git a/components/soc/esp32s3/include/soc/rtc.h b/components/soc/esp32s3/include/soc/rtc.h index a67396f1c8..bd2ad0492d 100644 --- a/components/soc/esp32s3/include/soc/rtc.h +++ b/components/soc/esp32s3/include/soc/rtc.h @@ -126,6 +126,22 @@ set sleep_init default param #define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 0xf +/* +The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value +storing in efuse +*/ +#define K_RTC_MID_MUL10000 198 +#define K_DIG_MID_MUL10000 211 +#define V_RTC_MID_MUL10000 10181 +#define V_DIG_MID_MUL10000 10841 + +/* +set LDO slave during CPU switch +*/ +#define DEFAULT_LDO_SLAVE 0x7 + + + /** * @brief Possible main XTAL frequency values. * diff --git a/components/soc/esp32s3/include/soc/rtc_cntl_reg.h b/components/soc/esp32s3/include/soc/rtc_cntl_reg.h index 19cdfeb234..48927f3d53 100644 --- a/components/soc/esp32s3/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32s3/include/soc/rtc_cntl_reg.h @@ -3683,6 +3683,9 @@ ork.*/ #define RTC_CNTL_DISABLE_RTC_CPU_V 0x1 #define RTC_CNTL_DISABLE_RTC_CPU_S 31 +/* +Due to the LDO slaves, RTC_CNTL_DATE_REG[18:13] can only be used for LDO adjustment. +*/ #define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x1FC) /* RTC_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101271 ; */ /*description: .*/ @@ -3690,7 +3693,12 @@ ork.*/ #define RTC_CNTL_DATE_M ((RTC_CNTL_DATE_V)<<(RTC_CNTL_DATE_S)) #define RTC_CNTL_DATE_V 0xFFFFFFF #define RTC_CNTL_DATE_S 0 - +/*LDO SLAVE : R/W ;bitpos:[18:13] ; default: 6'd0 ;*/ +/*description: .*/ +#define RTC_CNTL_SLAVE_PD 0x0000003F +#define RTC_CNTL_SLAVE_PD_M ((RTC_CNTL_SLAVE_V)<<(RTC_CNTL_SLAVE_S)) +#define RTC_CNTL_SLAVE_PD_V 0x3F +#define RTC_CNTL_SLAVE_PD_S 13 #ifdef __cplusplus }