kopia lustrzana https://github.com/espressif/esp-idf
esp_psram: fixed 40mhz cs signal glitch issue
rodzic
91e6b5de70
commit
d08be42a53
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@ -123,6 +123,17 @@ typedef enum {
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#define PICO_V3_02_PSRAM_CLK_IO 10
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#define PICO_V3_02_PSRAM_CS_IO 9
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#if CONFIG_SPIRAM_SPEED_40M && CONFIG_ESPTOOLPY_FLASHFREQ_40M
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#define PSRAM_CS_HOLD_TIME 0
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#elif CONFIG_SPIRAM_SPEED_40M && CONFIG_ESPTOOLPY_FLASHFREQ_80M
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#define PSRAM_CS_HOLD_TIME 0
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#elif CONFIG_SPIRAM_SPEED_80M && CONFIG_ESPTOOLPY_FLASHFREQ_80M
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#define PSRAM_CS_HOLD_TIME 1
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#else
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#error "FLASH speed can only be equal to or higher than SRAM speed while SRAM is enabled!"
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#endif
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typedef struct {
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uint8_t flash_clk_io;
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uint8_t flash_cs_io;
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@ -659,7 +670,7 @@ void psram_set_cs_timing(psram_spi_num_t spi_num, psram_clk_mode_t clk_mode)
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if (clk_mode == PSRAM_CLK_MODE_NORM) {
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SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
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// Set cs time.
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SET_PERI_REG_BITS(SPI_CTRL2_REG(spi_num), SPI_HOLD_TIME_V, 1, SPI_HOLD_TIME_S);
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SET_PERI_REG_BITS(SPI_CTRL2_REG(spi_num), SPI_HOLD_TIME_V, PSRAM_CS_HOLD_TIME, SPI_HOLD_TIME_S);
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SET_PERI_REG_BITS(SPI_CTRL2_REG(spi_num), SPI_SETUP_TIME_V, 0, SPI_SETUP_TIME_S);
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} else {
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
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