From d08be42a53bf6ee4493b38537eae78912e201e2c Mon Sep 17 00:00:00 2001 From: Armando Date: Thu, 18 Aug 2022 20:33:12 +0800 Subject: [PATCH] esp_psram: fixed 40mhz cs signal glitch issue --- components/esp_hw_support/port/esp32/spiram_psram.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/components/esp_hw_support/port/esp32/spiram_psram.c b/components/esp_hw_support/port/esp32/spiram_psram.c index e6507d906a..addd97ba11 100644 --- a/components/esp_hw_support/port/esp32/spiram_psram.c +++ b/components/esp_hw_support/port/esp32/spiram_psram.c @@ -123,6 +123,17 @@ typedef enum { #define PICO_V3_02_PSRAM_CLK_IO 10 #define PICO_V3_02_PSRAM_CS_IO 9 +#if CONFIG_SPIRAM_SPEED_40M && CONFIG_ESPTOOLPY_FLASHFREQ_40M +#define PSRAM_CS_HOLD_TIME 0 +#elif CONFIG_SPIRAM_SPEED_40M && CONFIG_ESPTOOLPY_FLASHFREQ_80M +#define PSRAM_CS_HOLD_TIME 0 +#elif CONFIG_SPIRAM_SPEED_80M && CONFIG_ESPTOOLPY_FLASHFREQ_80M +#define PSRAM_CS_HOLD_TIME 1 +#else +#error "FLASH speed can only be equal to or higher than SRAM speed while SRAM is enabled!" +#endif + + typedef struct { uint8_t flash_clk_io; uint8_t flash_cs_io; @@ -659,7 +670,7 @@ void psram_set_cs_timing(psram_spi_num_t spi_num, psram_clk_mode_t clk_mode) if (clk_mode == PSRAM_CLK_MODE_NORM) { SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_CS_HOLD_M | SPI_CS_SETUP_M); // Set cs time. - SET_PERI_REG_BITS(SPI_CTRL2_REG(spi_num), SPI_HOLD_TIME_V, 1, SPI_HOLD_TIME_S); + SET_PERI_REG_BITS(SPI_CTRL2_REG(spi_num), SPI_HOLD_TIME_V, PSRAM_CS_HOLD_TIME, SPI_HOLD_TIME_S); SET_PERI_REG_BITS(SPI_CTRL2_REG(spi_num), SPI_SETUP_TIME_V, 0, SPI_SETUP_TIME_S); } else { CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_CS_HOLD_M | SPI_CS_SETUP_M);