kopia lustrzana https://github.com/espressif/esp-idf
codeclean: clean esp32c6 rtc_sleep related code
rodzic
68594abe05
commit
cd9d914ba0
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@ -95,8 +95,8 @@ __attribute__((weak)) void bootloader_clock_configure(void)
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CLEAR_PERI_REG_MASK(LP_TIMER_LP_INT_ENA_REG, LP_TIMER_MAIN_TIMER_LP_INT_ENA); /* MAIN_TIMER */
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CLEAR_PERI_REG_MASK(LP_ANALOG_PERI_LP_ANA_LP_INT_ENA_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA); /* BROWN_OUT */
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CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_LP_WDT_INT_ENA); /* WDT */
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// CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_WAKEUP_INT_ENA); // TODO: IDF-5348 /* SLP_REJECT */
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// CLEAR_PERI_REG_MASK(PMU_SOC_SLEEP_REJECT_INT_ENA, PMU_SOC_SLEEP_REJECT_INT_ENA); /* SLP_WAKEUP */
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CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_WAKEUP_INT_ENA); /* SLP_REJECT */
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CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_SLEEP_REJECT_INT_ENA); /* SLP_WAKEUP */
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// SET CLR
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SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_SUPER_WDT_INT_CLR); /* SWD */
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SET_PERI_REG_MASK(LP_TIMER_LP_INT_CLR_REG, LP_TIMER_MAIN_TIMER_LP_INT_CLR); /* MAIN_TIMER */
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@ -108,13 +108,13 @@ __attribute__((weak)) void bootloader_clock_configure(void)
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CLEAR_PERI_REG_MASK(LP_ANALOG_PERI_LP_ANA_LP_INT_ENA_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_ENA); /* BROWN_OUT */
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CLEAR_PERI_REG_MASK(LP_WDT_INT_ENA_REG, LP_WDT_LP_WDT_INT_ENA); /* WDT */
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CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_WAKEUP_INT_ENA); /* SLP_REJECT */
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CLEAR_PERI_REG_MASK(PMU_SOC_SLEEP_REJECT_INT_ENA, PMU_SOC_SLEEP_REJECT_INT_ENA); /* SLP_WAKEUP */
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CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_SLEEP_REJECT_INT_ENA); /* SLP_WAKEUP */
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// SET CLR
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SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_SUPER_WDT_INT_CLR); /* SWD */
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SET_PERI_REG_MASK(LP_ANALOG_PERI_LP_ANA_LP_INT_CLR_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR); /* BROWN_OUT */
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SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_LP_WDT_INT_CLR); /* WDT */
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// SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SOC_WAKEUP_INT_CLR); // TODO: IDF-5348 /* SLP_REJECT */
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// SET_PERI_REG_MASK(PMU_SOC_SLEEP_REJECT_INT_CLR, PMU_SOC_SLEEP_REJECT_INT_CLR); /* SLP_WAKEUP */
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SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SOC_WAKEUP_INT_CLR); /* SLP_REJECT */
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SET_PERI_REG_MASK(PMU_SOC_SLEEP_REJECT_INT_CLR, PMU_SOC_SLEEP_REJECT_INT_CLR); /* SLP_WAKEUP */
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#else
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REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
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REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
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@ -1,7 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// TODO: IDF-5645
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@ -1312,9 +1312,7 @@ esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause(void)
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return ESP_SLEEP_WAKEUP_UNDEFINED;
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}
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#ifdef CONFIG_IDF_TARGET_ESP32
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uint32_t wakeup_cause = REG_GET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_CAUSE);
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#elif SOC_PMU_SUPPORTED
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#if SOC_PMU_SUPPORTED
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uint32_t wakeup_cause = pmu_ll_hp_get_wakeup_cause(&PMU);
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#else
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uint32_t wakeup_cause = rtc_cntl_ll_get_wakeup_cause();
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@ -23,6 +23,11 @@
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#else
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#include "hal/rtc_cntl_ll.h"
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#endif
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#if SOC_PMU_SUPPORTED
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#include "hal/pmu_ll.h"
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#endif
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#include "sdkconfig.h"
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#include "esp_rom_uart.h"
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#include "esp_rom_sys.h"
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@ -62,7 +67,12 @@ void RTC_IRAM_ATTR esp_wake_stub_sleep(esp_deep_sleep_wake_stub_fn_t new_stub)
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#endif // SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_MEM
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// Go to sleep.
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#if SOC_PMU_SUPPORTED
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pmu_ll_hp_set_sleep_enable(&PMU);
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#else
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rtc_cntl_ll_sleep_enable();
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#endif
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// A few CPU cycles may be necessary for the sleep to start...
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while (true) {};
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// never reaches here.
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@ -89,5 +99,9 @@ void RTC_IRAM_ATTR esp_wake_stub_set_wakeup_time(uint64_t time_in_us)
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uint32_t RTC_IRAM_ATTR esp_wake_stub_get_wakeup_cause(void)
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{
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#if SOC_PMU_SUPPORTED
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return pmu_ll_hp_get_wakeup_cause(&PMU);
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#else
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return rtc_cntl_ll_get_wakeup_cause();
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#endif
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}
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@ -1,89 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "soc/soc.h"
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#include "soc/rtc.h"
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#include "soc/lp_aon_reg.h"
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#include "esp_attr.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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FORCE_INLINE_ATTR void rtc_cntl_ll_set_wakeup_timer(uint64_t t)
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{
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// TODO: IDF-5645
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}
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FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_gpio_get_wakeup_status(void)
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{
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// TODO: IDF-5645
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return 0;
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_gpio_clear_wakeup_status(void)
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{
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// TODO: IDF-5645
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_set_cpu_retention_link_addr(uint32_t addr)
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{
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// TODO: IDF-5718 has removed the retention feature
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_enable_cpu_retention_clock(void)
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{
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// TODO: IDF-5718 has removed the retention feature
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_enable_cpu_retention(void)
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{
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// TODO: IDF-5718 has removed the retention feature
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_disable_cpu_retention(void)
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{
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// TODO: IDF-5718 has removed the retention feature
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_reset_system(void)
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{
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REG_SET_BIT(LP_AON_SYS_CFG_REG, LP_AON_HPSYS_SW_RESET);
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_reset_cpu(int cpu_no)
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{
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REG_SET_BIT(LP_AON_CPUCORE0_CFG_REG, LP_AON_CPU_CORE0_SW_RESET);
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}
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FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void)
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{
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// TODO: IDF-6064
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}
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FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_get_rtc_time(void)
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{
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// TODO: IDF-6064
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return 0;
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}
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FORCE_INLINE_ATTR uint64_t rtc_cntl_ll_time_to_count(uint64_t time_in_us)
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{
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// TODO: IDF-6064
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return 0;
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}
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FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void)
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{
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// TODO: IDF-6064
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return 0;
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}
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#ifdef __cplusplus
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}
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#endif
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@ -17,7 +17,7 @@ extern "C" {
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/**
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* @file rtc.h
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* @brief Low-level RTC power, clock, and sleep functions.
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* @brief Low-level RTC power, clock functions.
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*
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* Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral.
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* RTC_CNTL peripheral handles many functions:
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@ -514,164 +514,8 @@ bool rtc_dig_8m_enabled(void);
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*/
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uint32_t rtc_clk_freq_cal(uint32_t cal_val);
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/**
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* @brief Power down flags for rtc_sleep_pd function
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*/
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typedef struct {
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uint32_t dig_fpu : 1; //!< Set to 1 to power UP digital part in sleep
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uint32_t rtc_fpu : 1; //!< Set to 1 to power UP RTC memories in sleep
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uint32_t cpu_fpu : 1; //!< Set to 1 to power UP digital memories and CPU in sleep
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uint32_t i2s_fpu : 1; //!< Set to 1 to power UP I2S in sleep
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uint32_t bb_fpu : 1; //!< Set to 1 to power UP WiFi in sleep
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uint32_t nrx_fpu : 1; //!< Set to 1 to power UP WiFi in sleep
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uint32_t fe_fpu : 1; //!< Set to 1 to power UP WiFi in sleep
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uint32_t sram_fpu : 1; //!< Set to 1 to power UP SRAM in sleep
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uint32_t rom_ram_fpu : 1; //!< Set to 1 to power UP ROM/IRAM0_DRAM0 in sleep
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} rtc_sleep_pu_config_t;
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/**
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* Initializer for rtc_sleep_pu_config_t which sets all flags to the same value
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*/
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#define RTC_SLEEP_PU_CONFIG_ALL(val) {\
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.dig_fpu = (val), \
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.rtc_fpu = (val), \
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.cpu_fpu = (val), \
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.i2s_fpu = (val), \
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.bb_fpu = (val), \
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.nrx_fpu = (val), \
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.fe_fpu = (val), \
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.sram_fpu = (val), \
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.rom_ram_fpu = (val), \
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}
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void rtc_sleep_pu(rtc_sleep_pu_config_t cfg);
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/**
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* @brief sleep configuration for rtc_sleep_init function
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*/
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typedef struct {
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uint32_t lslp_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (digital domain memory)
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uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used)
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uint32_t rtc_fastmem_pd_en : 1; //!< power down RTC fast memory
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uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory
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uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals
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uint32_t wifi_pd_en : 1; //!< power down WiFi
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uint32_t bt_pd_en : 1; //!< power down BT
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uint32_t cpu_pd_en : 1; //!< power down CPU, but not restart when lightsleep.
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uint32_t int_8m_pd_en : 1; //!< Power down Internal 8M oscillator
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uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals
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uint32_t deep_slp : 1; //!< power down digital domain
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uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode
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uint32_t dig_dbias_wak : 5; //!< set bias for digital domain, in active mode
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uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode
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uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode
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uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode
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uint32_t dbg_atten_monitor : 4; //!< voltage parameter, in monitor mode
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uint32_t bias_sleep_monitor : 1; //!< circuit control parameter, in monitor mode
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uint32_t dbg_atten_slp : 4; //!< voltage parameter, in sleep mode
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uint32_t bias_sleep_slp : 1; //!< circuit control parameter, in sleep mode
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uint32_t pd_cur_monitor : 1; //!< circuit control parameter, in monitor mode
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uint32_t pd_cur_slp : 1; //!< circuit control parameter, in sleep mode
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uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator
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uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep
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uint32_t deep_slp_reject : 1; //!< enable deep sleep reject
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uint32_t light_slp_reject : 1; //!< enable light sleep reject
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} rtc_sleep_config_t;
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/**
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* Default initializer for rtc_sleep_config_t
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*
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* This initializer sets all fields to "reasonable" values (e.g. suggested for
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* production use) based on a combination of RTC_SLEEP_PD_x flags.
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*
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* @param RTC_SLEEP_PD_x flags combined using bitwise OR
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*/
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void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config);
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/**
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* @brief Prepare the chip to enter sleep mode
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*
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* This function configures various power control state machines to handle
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* entry into light sleep or deep sleep mode, switches APB and CPU clock source
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* (usually to XTAL), and sets bias voltages for digital and RTC power domains.
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*
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* This function does not actually enter sleep mode; this is done using
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* rtc_sleep_start function. Software may do some other actions between
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* rtc_sleep_init and rtc_sleep_start, such as set wakeup timer and configure
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* wakeup sources.
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* @param cfg sleep mode configuration
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*/
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void rtc_sleep_init(rtc_sleep_config_t cfg);
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/**
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* @brief Low level initialize for rtc state machine waiting cycles after waking up
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*
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* This function configures the cycles chip need to wait for internal 8MHz
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* oscillator and external 40MHz crystal. As we configure fixed time for waiting
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* crystal, we need to pass period to calculate cycles. Now this function only
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* used in lightsleep mode.
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*
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* @param slowclk_period re-calibrated slow clock period
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*/
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void rtc_sleep_low_init(uint32_t slowclk_period);
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/**
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* @brief Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source
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* @param t value of RTC counter at which wakeup from sleep will happen;
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* only the lower 48 bits are used
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*/
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void rtc_sleep_set_wakeup_time(uint64_t t);
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/**
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* @brief Enter deep or light sleep mode
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*
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* This function enters the sleep mode previously configured using rtc_sleep_init
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* function. Before entering sleep, software should configure wake up sources
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* appropriately (set up GPIO wakeup registers, timer wakeup registers,
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* and so on).
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*
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* If deep sleep mode was configured using rtc_sleep_init, and sleep is not
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* rejected by hardware (based on reject_opt flags), this function never returns.
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* When the chip wakes up from deep sleep, CPU is reset and execution starts
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* from ROM bootloader.
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*
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* If light sleep mode was configured using rtc_sleep_init, this function
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* returns on wakeup, or if sleep is rejected by hardware.
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*
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* @param wakeup_opt bit mask wake up reasons to enable (RTC_xxx_TRIG_EN flags
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* combined with OR)
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* @param reject_opt bit mask of sleep reject reasons:
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* - RTC_CNTL_GPIO_REJECT_EN
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* - RTC_CNTL_SDIO_REJECT_EN
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* These flags are used to prevent entering sleep when e.g.
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* an external host is communicating via SDIO slave
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* @return non-zero if sleep was rejected by hardware
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*/
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uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu);
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/**
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* @brief Enter deep sleep mode
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*
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* Similar to rtc_sleep_start(), but additionally uses hardware to calculate the CRC value
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* of RTC FAST memory. On wake, this CRC is used to determine if a deep sleep wake
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* stub is valid to execute (if a wake address is set).
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*
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* No RAM is accessed while calculating the CRC and going into deep sleep, which makes
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* this function safe to use even if the caller's stack is in RTC FAST memory.
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*
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* @note If no deep sleep wake stub address is set then calling rtc_sleep_start() will
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* have the same effect and takes less time as CRC calculation is skipped.
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*
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* @note This function should only be called after rtc_sleep_init() has been called to
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* configure the system for deep sleep.
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*
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* @param wakeup_opt - same as for rtc_sleep_start
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* @param reject_opt - same as for rtc_sleep_start
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*
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* @return non-zero if sleep was rejected by hardware
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*/
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uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt);
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/**
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* RTC power and clock control initialization settings
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