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Merge branch 'bugfix/cpu_reset_perip_clk_disable_v4.2' into 'release/v4.2' 

esp_system: Peripheral clocks faulty become disabled during cpu reset (backport v4.2)

See merge request espressif/esp-idf!15486
release/v4.2
Jiang Jiang Jian 2022-07-11 16:44:32 +08:00
rodzic 443d8a187b affb956da5
commit a07f18ff9f
2 zmienionych plików z 6 dodań i 5 usunięć
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4
components/esp32/clk.c
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@ -263,9 +263,9 @@ void esp_perip_clk_init(void)
/* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset.
*/
if ((rst_reas[0] >= TGWDT_CPU_RESET && rst_reas[0] <= RTCWDT_CPU_RESET)
if ((rst_reas[0] == TGWDT_CPU_RESET || rst_reas[0] == SW_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET)
#if !CONFIG_FREERTOS_UNICORE
|| (rst_reas[1] >= TGWDT_CPU_RESET && rst_reas[1] <= RTCWDT_CPU_RESET)
|| (rst_reas[1] == TGWDT_CPU_RESET || rst_reas[1] == SW_CPU_RESET || rst_reas[1] == RTCWDT_CPU_RESET)
#endif
) {
common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);

7
components/esp32s2/clk.c
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@ -229,9 +229,10 @@ void esp_perip_clk_init(void)
/* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset.
*/
if (rst_reas[0] >= TG0WDT_CPU_RESET &&
rst_reas[0] <= TG0WDT_CPU_RESET &&
rst_reas[0] != RTCWDT_BROWN_OUT_RESET) {
if (rst_reas[0] == TG0WDT_CPU_RESET ||
rst_reas[0] == RTC_SW_CPU_RESET ||
rst_reas[0] == RTCWDT_CPU_RESET ||
rst_reas[0] == TG1WDT_CPU_RESET) {
common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN1_REG);
wifi_bt_sdio_clk = ~DPORT_READ_PERI_REG(DPORT_WIFI_CLK_EN_REG);