kopia lustrzana https://github.com/espressif/esp-idf
fix(flash_mmap): fixed limited free I/D pages on ESP32S3, C3
Armando
Armando (Dou Yiwen)
rodzic
3f81b1a387
commit
7911e997ff
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@ -34,9 +34,14 @@ if(target STREQUAL "esp32s3")
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list(APPEND sources "patches/esp_rom_cache_writeback_esp32s3.S")
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endif()
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if(target STREQUAL "esp32s3" OR target STREQUAL "esp32c3" OR target STREQUAL "esp32h2")
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list(APPEND sources "patches/esp_rom_mmap.c")
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endif()
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idf_component_register(SRCS ${sources}
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INCLUDE_DIRS ${include_dirs}
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PRIV_REQUIRES ${private_required_comp})
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PRIV_REQUIRES ${private_required_comp}
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LDFRAGMENTS linker.lf)
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# Append a target linker script at the target-specific path,
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# only the 'name' part is different for each script
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@ -7,6 +7,8 @@ ifdef IS_BOOTLOADER_BUILD
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COMPONENT_OBJEXCLUDE += patches/esp_rom_longjmp.o
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endif
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COMPONENT_OBJEXCLUDE := patches/esp_rom_mmap.o
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#Linker scripts used to link the final application.
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#Warning: These linker scripts are only used when the normal app is compiled; the bootloader
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#specifies its own scripts.
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@ -0,0 +1,6 @@
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[mapping:esp_rom]
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archive: libesp_rom.a
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entries:
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if IDF_TARGET_ESP32S3 = y || IDF_TARGET_ESP32C3 = y
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|| IDF_TARGET_ESP32H2 = y:
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esp_rom_mmap (noflash)
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@ -0,0 +1,34 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <stdbool.h>
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#include "sdkconfig.h"
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#include "esp_rom_sys.h"
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#include "assert.h"
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uint32_t Cache_Get_IROM_MMU_End(void)
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{
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#if CONFIG_IDF_TARGET_ESP32S3
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esp_rom_printf("0x800\n");
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return 0x800;
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#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
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return 0x200;
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#else
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assert(false);
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#endif
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}
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uint32_t Cache_Get_DROM_MMU_End(void)
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{
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#if CONFIG_IDF_TARGET_ESP32S3
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return 0x800;
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#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
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return 0x200;
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#else
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assert(false);
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#endif
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}
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@ -0,0 +1,17 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define MMU_INVALID BIT(8)
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#ifdef __cplusplus
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}
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#endif
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@ -54,7 +54,7 @@ extern "C" {
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#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
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#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
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#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
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#define CACHE_DROM_MMU_START 0
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#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
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#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
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@ -55,7 +55,7 @@ extern "C" {
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#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
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#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
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#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
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#define CACHE_DROM_MMU_START 0
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#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
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#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
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@ -31,6 +31,7 @@ extern "C" {
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#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL
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#define SOC_MMU_ADDR_MASK MMU_ADDRESS_MASK
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#define SOC_MMU_PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH)
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#define SOC_MMU_PAGE_IN_PSRAM(page) ((page) | MMU_ACCESS_SPIRAM)
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#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE
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#define SOC_MMU_VADDR1_START_ADDR SOC_IROM_MASK_LOW
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#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE ((SOC_MMU_VADDR1_FIRST_USABLE_ADDR - SOC_MMU_VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + SOC_MMU_IROM0_PAGES_START)
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@ -53,7 +53,7 @@ extern "C" {
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#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
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#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
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#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
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#define CACHE_DROM_MMU_START 0
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#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
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#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
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@ -31,6 +31,7 @@ extern "C" {
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#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL
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#define SOC_MMU_ADDR_MASK MMU_ADDRESS_MASK
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#define SOC_MMU_PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH)
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#define SOC_MMU_PAGE_IN_PSRAM(page) ((page) | MMU_ACCESS_SPIRAM)
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#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE
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#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW
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#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START
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@ -29,6 +29,7 @@
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#include "esp_flash_encrypt.h"
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#include "esp_log.h"
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#include "cache_utils.h"
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#include "soc/cache_memory.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "soc/dport_reg.h"
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@ -41,24 +42,20 @@
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#include "esp32s2/rom/spi_flash.h"
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#include "esp32s2/spiram.h"
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#include "soc/extmem_reg.h"
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#include "soc/cache_memory.h"
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#include "soc/mmu.h"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/rom/spi_flash.h"
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#include "esp32s3/rom/cache.h"
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#include "esp32s3/spiram.h"
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#include "soc/extmem_reg.h"
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#include "soc/cache_memory.h"
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#include "soc/mmu.h"
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#elif CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/rom/cache.h"
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#include "esp32c3/rom/spi_flash.h"
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#include "soc/cache_memory.h"
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#include "soc/mmu.h"
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#elif CONFIG_IDF_TARGET_ESP32H2
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#include "esp32h2/rom/cache.h"
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#include "esp32h2/rom/spi_flash.h"
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#include "soc/cache_memory.h"
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#include "soc/mmu.h"
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#endif
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@ -207,6 +204,13 @@ esp_err_t IRAM_ATTR spi_flash_mmap_pages(const int *pages, size_t page_count, sp
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for (pos = start; pos < start + page_count; ++pos, ++pageno) {
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int table_val = (int) DPORT_SEQUENCE_REG_READ((uint32_t)&SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE[pos]);
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uint8_t refcnt = s_mmap_page_refcnt[pos];
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#if !CONFIG_IDF_TARGET_ESP32 && SOC_SPIRAM_SUPPORTED
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if (table_val & MMU_ACCESS_SPIRAM) {
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break;
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}
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#endif //#if !CONFIG_IDF_TARGET_ESP32
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if (refcnt != 0 && table_val != SOC_MMU_PAGE_IN_FLASH(pages[pageno])) {
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break;
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}
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@ -237,6 +241,10 @@ esp_err_t IRAM_ATTR spi_flash_mmap_pages(const int *pages, size_t page_count, sp
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#endif
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));
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if (s_mmap_page_refcnt[i] == 0) {
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assert(DPORT_SEQUENCE_REG_READ((uint32_t)&SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE[i]) & MMU_INVALID);
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#if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32
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assert(DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_APP_FLASH_MMU_TABLE[i]) & MMU_INVALID);
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#endif
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if (entry_pro != SOC_MMU_PAGE_IN_FLASH(pages[pageno])
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#if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32
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|| entry_app != SOC_MMU_PAGE_IN_FLASH(pages[pageno])
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