diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt index 36cd409550..b748253c86 100644 --- a/components/esp_rom/CMakeLists.txt +++ b/components/esp_rom/CMakeLists.txt @@ -34,9 +34,14 @@ if(target STREQUAL "esp32s3") list(APPEND sources "patches/esp_rom_cache_writeback_esp32s3.S") endif() +if(target STREQUAL "esp32s3" OR target STREQUAL "esp32c3" OR target STREQUAL "esp32h2") + list(APPEND sources "patches/esp_rom_mmap.c") +endif() + idf_component_register(SRCS ${sources} INCLUDE_DIRS ${include_dirs} - PRIV_REQUIRES ${private_required_comp}) + PRIV_REQUIRES ${private_required_comp} + LDFRAGMENTS linker.lf) # Append a target linker script at the target-specific path, # only the 'name' part is different for each script diff --git a/components/esp_rom/component.mk b/components/esp_rom/component.mk index 161c8ef480..7607cd4a60 100644 --- a/components/esp_rom/component.mk +++ b/components/esp_rom/component.mk @@ -7,6 +7,8 @@ ifdef IS_BOOTLOADER_BUILD COMPONENT_OBJEXCLUDE += patches/esp_rom_longjmp.o endif +COMPONENT_OBJEXCLUDE := patches/esp_rom_mmap.o + #Linker scripts used to link the final application. #Warning: These linker scripts are only used when the normal app is compiled; the bootloader #specifies its own scripts. diff --git a/components/esp_rom/linker.lf b/components/esp_rom/linker.lf new file mode 100644 index 0000000000..5ee1b9adaf --- /dev/null +++ b/components/esp_rom/linker.lf @@ -0,0 +1,6 @@ +[mapping:esp_rom] +archive: libesp_rom.a +entries: + if IDF_TARGET_ESP32S3 = y || IDF_TARGET_ESP32C3 = y + || IDF_TARGET_ESP32H2 = y: + esp_rom_mmap (noflash) diff --git a/components/esp_rom/patches/esp_rom_mmap.c b/components/esp_rom/patches/esp_rom_mmap.c new file mode 100644 index 0000000000..a8cd91e353 --- /dev/null +++ b/components/esp_rom/patches/esp_rom_mmap.c @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "sdkconfig.h" +#include "esp_rom_sys.h" +#include "assert.h" + +uint32_t Cache_Get_IROM_MMU_End(void) +{ +#if CONFIG_IDF_TARGET_ESP32S3 + esp_rom_printf("0x800\n"); + return 0x800; +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 + return 0x200; +#else + assert(false); +#endif +} + +uint32_t Cache_Get_DROM_MMU_End(void) +{ +#if CONFIG_IDF_TARGET_ESP32S3 + return 0x800; +#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 + return 0x200; +#else + assert(false); +#endif +} diff --git a/components/soc/esp32/include/soc/cache_memory.h b/components/soc/esp32/include/soc/cache_memory.h new file mode 100644 index 0000000000..aade7c799b --- /dev/null +++ b/components/soc/esp32/include/soc/cache_memory.h @@ -0,0 +1,17 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define MMU_INVALID BIT(8) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c3/include/soc/cache_memory.h b/components/soc/esp32c3/include/soc/cache_memory.h index 350cc8dec9..aeb7365be9 100644 --- a/components/soc/esp32c3/include/soc/cache_memory.h +++ b/components/soc/esp32c3/include/soc/cache_memory.h @@ -54,7 +54,7 @@ extern "C" { #define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End() #define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START) -#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END +#define CACHE_DROM_MMU_START 0 #define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End() #define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START) diff --git a/components/soc/esp32h2/include/soc/cache_memory.h b/components/soc/esp32h2/include/soc/cache_memory.h index db558c4e50..b146eeb218 100644 --- a/components/soc/esp32h2/include/soc/cache_memory.h +++ b/components/soc/esp32h2/include/soc/cache_memory.h @@ -55,7 +55,7 @@ extern "C" { #define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End() #define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START) -#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END +#define CACHE_DROM_MMU_START 0 #define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End() #define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START) diff --git a/components/soc/esp32s2/include/soc/mmu.h b/components/soc/esp32s2/include/soc/mmu.h index 44f716f217..8d702a4812 100644 --- a/components/soc/esp32s2/include/soc/mmu.h +++ b/components/soc/esp32s2/include/soc/mmu.h @@ -31,6 +31,7 @@ extern "C" { #define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL #define SOC_MMU_ADDR_MASK MMU_ADDRESS_MASK #define SOC_MMU_PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH) +#define SOC_MMU_PAGE_IN_PSRAM(page) ((page) | MMU_ACCESS_SPIRAM) #define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE #define SOC_MMU_VADDR1_START_ADDR SOC_IROM_MASK_LOW #define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE ((SOC_MMU_VADDR1_FIRST_USABLE_ADDR - SOC_MMU_VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + SOC_MMU_IROM0_PAGES_START) diff --git a/components/soc/esp32s3/include/soc/cache_memory.h b/components/soc/esp32s3/include/soc/cache_memory.h index 221a77b503..6d4bee8b56 100644 --- a/components/soc/esp32s3/include/soc/cache_memory.h +++ b/components/soc/esp32s3/include/soc/cache_memory.h @@ -53,7 +53,7 @@ extern "C" { #define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End() #define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START) -#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END +#define CACHE_DROM_MMU_START 0 #define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End() #define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START) diff --git a/components/soc/esp32s3/include/soc/mmu.h b/components/soc/esp32s3/include/soc/mmu.h index a38cb9eb42..a0d62b2a76 100644 --- a/components/soc/esp32s3/include/soc/mmu.h +++ b/components/soc/esp32s3/include/soc/mmu.h @@ -31,6 +31,7 @@ extern "C" { #define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL #define SOC_MMU_ADDR_MASK MMU_ADDRESS_MASK #define SOC_MMU_PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH) +#define SOC_MMU_PAGE_IN_PSRAM(page) ((page) | MMU_ACCESS_SPIRAM) #define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE #define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW #define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START diff --git a/components/spi_flash/flash_mmap.c b/components/spi_flash/flash_mmap.c index 9523bc7959..90bf074d9c 100644 --- a/components/spi_flash/flash_mmap.c +++ b/components/spi_flash/flash_mmap.c @@ -29,6 +29,7 @@ #include "esp_flash_encrypt.h" #include "esp_log.h" #include "cache_utils.h" +#include "soc/cache_memory.h" #if CONFIG_IDF_TARGET_ESP32 #include "soc/dport_reg.h" @@ -41,24 +42,20 @@ #include "esp32s2/rom/spi_flash.h" #include "esp32s2/spiram.h" #include "soc/extmem_reg.h" -#include "soc/cache_memory.h" #include "soc/mmu.h" #elif CONFIG_IDF_TARGET_ESP32S3 #include "esp32s3/rom/spi_flash.h" #include "esp32s3/rom/cache.h" #include "esp32s3/spiram.h" #include "soc/extmem_reg.h" -#include "soc/cache_memory.h" #include "soc/mmu.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/cache.h" #include "esp32c3/rom/spi_flash.h" -#include "soc/cache_memory.h" #include "soc/mmu.h" #elif CONFIG_IDF_TARGET_ESP32H2 #include "esp32h2/rom/cache.h" #include "esp32h2/rom/spi_flash.h" -#include "soc/cache_memory.h" #include "soc/mmu.h" #endif @@ -207,6 +204,13 @@ esp_err_t IRAM_ATTR spi_flash_mmap_pages(const int *pages, size_t page_count, sp for (pos = start; pos < start + page_count; ++pos, ++pageno) { int table_val = (int) DPORT_SEQUENCE_REG_READ((uint32_t)&SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE[pos]); uint8_t refcnt = s_mmap_page_refcnt[pos]; + +#if !CONFIG_IDF_TARGET_ESP32 && SOC_SPIRAM_SUPPORTED + if (table_val & MMU_ACCESS_SPIRAM) { + break; + } +#endif //#if !CONFIG_IDF_TARGET_ESP32 + if (refcnt != 0 && table_val != SOC_MMU_PAGE_IN_FLASH(pages[pageno])) { break; } @@ -237,6 +241,10 @@ esp_err_t IRAM_ATTR spi_flash_mmap_pages(const int *pages, size_t page_count, sp #endif )); if (s_mmap_page_refcnt[i] == 0) { + assert(DPORT_SEQUENCE_REG_READ((uint32_t)&SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE[i]) & MMU_INVALID); +#if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32 + assert(DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_APP_FLASH_MMU_TABLE[i]) & MMU_INVALID); +#endif if (entry_pro != SOC_MMU_PAGE_IN_FLASH(pages[pageno]) #if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32 || entry_app != SOC_MMU_PAGE_IN_FLASH(pages[pageno])