kopia lustrzana https://github.com/espressif/esp-idf
Also update documentation to new conventions
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@ -27,18 +27,18 @@ The spi_master driver uses the following terms:
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now, only HSPI or VSPI are actually supported in the driver; it will support all 3 peripherals
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somewhere in the future.)
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* Bus: The SPI bus, common to all SPI devices connected to one host. In general the bus consists of the
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spid, spiq, spiclk and optionally spiwp and spihd signals. The SPI slaves are connected to these
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miso, mosi, sclk and optionally quadwp and quadhd signals. The SPI slaves are connected to these
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signals in parallel.
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- spiq - Also known as MISO, this is the input of the serial stream into the ESP32
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- miso - Also known as q, this is the input of the serial stream into the ESP32
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- spid - Also known as MOSI, this is the output of the serial stream from the ESP32
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- mosi - Also known as d, this is the output of the serial stream from the ESP32
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- spiclk - Clock signal. Each data bit is clocked out or in on the positive or negative edge of this signal
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- sclk - Clock signal. Each data bit is clocked out or in on the positive or negative edge of this signal
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- spiwp - Write Protect signal. Only used for 4-bit (qio/qout) transactions.
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- quadwp - Write Protect signal. Only used for 4-bit (qio/qout) transactions.
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- spihd - Hold signal. Only used for 4-bit (qio/qout) transactions.
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- quadhd - Hold signal. Only used for 4-bit (qio/qout) transactions.
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* Device: A SPI slave. Each SPI slave has its own chip select (CS) line, which is made active when
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a transmission to/from the SPI slave occurs.
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