kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'feature/support_7.2.9_soc/pvt_dig_v5.0' into 'release/v5.0'
ESP32C2:support auto adjust LDO voltage based on pvt-dig(backport 5.0) See merge request espressif/esp-idf!19628pull/9723/head
Michael (XIAO Xufeng)
commit
4a68f9e064
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@ -9,7 +9,7 @@
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#include <assert.h>
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#include "esp_efuse_table.h"
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// md5_digest_table ef050bc1e4bf0d8384aa3e4c0256d7d3
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// md5_digest_table 5bc3d3149d5d4c75461337fa415d6533
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// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
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// If you want to change some fields, you need to change esp_efuse_table.csv file
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// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
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@ -176,30 +176,10 @@ static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = {
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{EFUSE_BLK2, 60, 2}, // BLK_VERSION_MAJOR,
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};
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static const esp_efuse_desc_t LDO_VOL_BIAS_CONFIG_HIGH[] = {
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{EFUSE_BLK2, 64, 27}, // EFUSE_LDO_VOL_BIAS_CONFIG_HIGH,
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};
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static const esp_efuse_desc_t PVT_LOW[] = {
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{EFUSE_BLK2, 91, 5}, // EFUSE_PVT_LOW,
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};
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static const esp_efuse_desc_t PVT_HIGH[] = {
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{EFUSE_BLK2, 96, 10}, // EFUSE_PVT_HIGH,
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};
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static const esp_efuse_desc_t ADC_CALIBRATION_0[] = {
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{EFUSE_BLK2, 106, 22}, // EFUSE_ADC_CALIBRATION_0,
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};
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static const esp_efuse_desc_t ADC_CALIBRATION_1[] = {
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{EFUSE_BLK2, 128, 32}, // EFUSE_ADC_CALIBRATION_1,
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};
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static const esp_efuse_desc_t ADC_CALIBRATION_2[] = {
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{EFUSE_BLK2, 160, 32}, // EFUSE_ADC_CALIBRATION_2,
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};
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static const esp_efuse_desc_t KEY0[] = {
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{EFUSE_BLK3, 0, 256}, // [256bit FE key] or [128bit FE key and 128key SB key] or [user data],
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};
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@ -216,6 +196,50 @@ static const esp_efuse_desc_t KEY0_SB_128BIT[] = {
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{EFUSE_BLK3, 128, 128}, // [128bit SB key],
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};
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static const esp_efuse_desc_t OCODE[] = {
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{EFUSE_BLK2, 62, 7}, // OCode,
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};
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static const esp_efuse_desc_t DIG_DBIAS_HVT[] = {
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{EFUSE_BLK2, 105, 5}, // BLOCK2 digital dbias when hvt,
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};
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static const esp_efuse_desc_t DIG_LDO_SLP_DBIAS2[] = {
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{EFUSE_BLK2, 110, 7}, // BLOCK2 DIG_LDO_DBG0_DBIAS2,
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};
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static const esp_efuse_desc_t DIG_LDO_SLP_DBIAS26[] = {
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{EFUSE_BLK2, 117, 8}, // BLOCK2 DIG_LDO_DBG0_DBIAS26,
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};
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static const esp_efuse_desc_t DIG_LDO_ACT_DBIAS26[] = {
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{EFUSE_BLK2, 125, 6}, // BLOCK2 DIG_LDO_ACT_DBIAS26,
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};
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static const esp_efuse_desc_t DIG_LDO_ACT_STEPD10[] = {
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{EFUSE_BLK2, 131, 4}, // BLOCK2 DIG_LDO_ACT_STEPD10,
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};
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static const esp_efuse_desc_t RTC_LDO_SLP_DBIAS13[] = {
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{EFUSE_BLK2, 135, 7}, // BLOCK2 DIG_LDO_SLP_DBIAS13,
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};
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static const esp_efuse_desc_t RTC_LDO_SLP_DBIAS29[] = {
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{EFUSE_BLK2, 142, 9}, // BLOCK2 DIG_LDO_SLP_DBIAS29,
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};
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static const esp_efuse_desc_t RTC_LDO_SLP_DBIAS31[] = {
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{EFUSE_BLK2, 151, 6}, // BLOCK2 DIG_LDO_SLP_DBIAS31,
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};
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static const esp_efuse_desc_t RTC_LDO_ACT_DBIAS31[] = {
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{EFUSE_BLK2, 157, 6}, // BLOCK2 DIG_LDO_ACT_DBIAS31,
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};
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static const esp_efuse_desc_t RTC_LDO_ACT_DBIAS13[] = {
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{EFUSE_BLK2, 163, 8}, // BLOCK2 DIG_LDO_ACT_DBIAS13,
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};
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@ -420,36 +444,11 @@ const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = {
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_LDO_VOL_BIAS_CONFIG_HIGH[] = {
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&LDO_VOL_BIAS_CONFIG_HIGH[0], // EFUSE_LDO_VOL_BIAS_CONFIG_HIGH
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_PVT_LOW[] = {
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&PVT_LOW[0], // EFUSE_PVT_LOW
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_PVT_HIGH[] = {
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&PVT_HIGH[0], // EFUSE_PVT_HIGH
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ADC_CALIBRATION_0[] = {
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&ADC_CALIBRATION_0[0], // EFUSE_ADC_CALIBRATION_0
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ADC_CALIBRATION_1[] = {
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&ADC_CALIBRATION_1[0], // EFUSE_ADC_CALIBRATION_1
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_ADC_CALIBRATION_2[] = {
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&ADC_CALIBRATION_2[0], // EFUSE_ADC_CALIBRATION_2
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = {
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&KEY0[0], // [256bit FE key] or [128bit FE key and 128key SB key] or [user data]
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NULL
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@ -469,3 +468,58 @@ const esp_efuse_desc_t* ESP_EFUSE_KEY0_SB_128BIT[] = {
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&KEY0_SB_128BIT[0], // [128bit SB key]
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = {
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&OCODE[0], // OCode
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[] = {
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&DIG_DBIAS_HVT[0], // BLOCK2 digital dbias when hvt
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_DIG_LDO_SLP_DBIAS2[] = {
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&DIG_LDO_SLP_DBIAS2[0], // BLOCK2 DIG_LDO_DBG0_DBIAS2
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_DIG_LDO_SLP_DBIAS26[] = {
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&DIG_LDO_SLP_DBIAS26[0], // BLOCK2 DIG_LDO_DBG0_DBIAS26
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_DIG_LDO_ACT_DBIAS26[] = {
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&DIG_LDO_ACT_DBIAS26[0], // BLOCK2 DIG_LDO_ACT_DBIAS26
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_DIG_LDO_ACT_STEPD10[] = {
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&DIG_LDO_ACT_STEPD10[0], // BLOCK2 DIG_LDO_ACT_STEPD10
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_SLP_DBIAS13[] = {
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&RTC_LDO_SLP_DBIAS13[0], // BLOCK2 DIG_LDO_SLP_DBIAS13
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_SLP_DBIAS29[] = {
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&RTC_LDO_SLP_DBIAS29[0], // BLOCK2 DIG_LDO_SLP_DBIAS29
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_SLP_DBIAS31[] = {
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&RTC_LDO_SLP_DBIAS31[0], // BLOCK2 DIG_LDO_SLP_DBIAS31
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_ACT_DBIAS31[] = {
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&RTC_LDO_ACT_DBIAS31[0], // BLOCK2 DIG_LDO_ACT_DBIAS31
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_ACT_DBIAS13[] = {
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&RTC_LDO_ACT_DBIAS13[0], // BLOCK2 DIG_LDO_ACT_DBIAS13
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NULL
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};
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@ -71,22 +71,25 @@
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BLK_VERSION_MAJOR, EFUSE_BLK2, 60, 2, BLK_VERSION_MAJOR
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# EFUSE_RD_BLK2_DATA2_REG
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LDO_VOL_BIAS_CONFIG_HIGH, EFUSE_BLK2, 64, 27, EFUSE_LDO_VOL_BIAS_CONFIG_HIGH
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PVT_LOW, EFUSE_BLK2, 91, 5, EFUSE_PVT_LOW
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# EFUSE_RD_BLK2_DATA3_REG
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PVT_HIGH, EFUSE_BLK2, 96, 10, EFUSE_PVT_HIGH
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ADC_CALIBRATION_0, EFUSE_BLK2, 106, 22, EFUSE_ADC_CALIBRATION_0
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# EFUSE_RD_BLK2_DATA4_REG
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ADC_CALIBRATION_1, EFUSE_BLK2, 128, 32, EFUSE_ADC_CALIBRATION_1
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# EFUSE_RD_BLK2_DATA5_REG
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ADC_CALIBRATION_2, EFUSE_BLK2, 160, 32, EFUSE_ADC_CALIBRATION_2
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################
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KEY0, EFUSE_BLK3, 0, 256, [256bit FE key] or [128bit FE key and 128key SB key] or [user data]
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KEY0.FE_256BIT, EFUSE_BLK3, 0, 256, [256bit FE key]
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KEY0.FE_128BIT, EFUSE_BLK3, 0, 128, [128bit FE key]
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KEY0.SB_128BIT, EFUSE_BLK3, 128, 128, [128bit SB key]
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# AUTO CONFIG DIG&RTC DBIAS#
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################
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OCODE, EFUSE_BLK2, 62, 7, OCode
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DIG_DBIAS_HVT, EFUSE_BLK2, 105, 5, BLOCK2 digital dbias when hvt
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DIG_LDO_SLP_DBIAS2, EFUSE_BLK2, 110, 7, BLOCK2 DIG_LDO_DBG0_DBIAS2
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DIG_LDO_SLP_DBIAS26, EFUSE_BLK2, 117, 8, BLOCK2 DIG_LDO_DBG0_DBIAS26
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DIG_LDO_ACT_DBIAS26, EFUSE_BLK2, 125, 6, BLOCK2 DIG_LDO_ACT_DBIAS26
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DIG_LDO_ACT_STEPD10, EFUSE_BLK2, 131, 4, BLOCK2 DIG_LDO_ACT_STEPD10
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RTC_LDO_SLP_DBIAS13, EFUSE_BLK2, 135, 7, BLOCK2 DIG_LDO_SLP_DBIAS13
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RTC_LDO_SLP_DBIAS29, EFUSE_BLK2, 142, 9, BLOCK2 DIG_LDO_SLP_DBIAS29
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RTC_LDO_SLP_DBIAS31, EFUSE_BLK2, 151, 6, BLOCK2 DIG_LDO_SLP_DBIAS31
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RTC_LDO_ACT_DBIAS31, EFUSE_BLK2, 157, 6, BLOCK2 DIG_LDO_ACT_DBIAS31
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RTC_LDO_ACT_DBIAS13, EFUSE_BLK2, 163, 8, BLOCK2 DIG_LDO_ACT_DBIAS13
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Nie można renderować tego pliku, ponieważ zawiera nieoczekiwany znak w wierszu 7 i kolumnie 53.
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@ -10,7 +10,7 @@ extern "C" {
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#include "esp_efuse.h"
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// md5_digest_table ef050bc1e4bf0d8384aa3e4c0256d7d3
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// md5_digest_table 5bc3d3149d5d4c75461337fa415d6533
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// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
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// If you want to change some fields, you need to change esp_efuse_table.csv file
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// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
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@ -56,16 +56,22 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
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extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
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extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
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extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
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extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VOL_BIAS_CONFIG_HIGH[];
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extern const esp_efuse_desc_t* ESP_EFUSE_PVT_LOW[];
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extern const esp_efuse_desc_t* ESP_EFUSE_PVT_HIGH[];
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extern const esp_efuse_desc_t* ESP_EFUSE_ADC_CALIBRATION_0[];
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extern const esp_efuse_desc_t* ESP_EFUSE_ADC_CALIBRATION_1[];
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extern const esp_efuse_desc_t* ESP_EFUSE_ADC_CALIBRATION_2[];
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extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
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extern const esp_efuse_desc_t* ESP_EFUSE_KEY0_FE_256BIT[];
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extern const esp_efuse_desc_t* ESP_EFUSE_KEY0_FE_128BIT[];
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extern const esp_efuse_desc_t* ESP_EFUSE_KEY0_SB_128BIT[];
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extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
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extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[];
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extern const esp_efuse_desc_t* ESP_EFUSE_DIG_LDO_SLP_DBIAS2[];
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extern const esp_efuse_desc_t* ESP_EFUSE_DIG_LDO_SLP_DBIAS26[];
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extern const esp_efuse_desc_t* ESP_EFUSE_DIG_LDO_ACT_DBIAS26[];
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extern const esp_efuse_desc_t* ESP_EFUSE_DIG_LDO_ACT_STEPD10[];
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extern const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_SLP_DBIAS13[];
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extern const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_SLP_DBIAS29[];
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extern const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_SLP_DBIAS31[];
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extern const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_ACT_DBIAS31[];
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extern const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_ACT_DBIAS13[];
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#ifdef __cplusplus
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}
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@ -126,6 +126,10 @@ static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
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/* Analog part */
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regi2c_ctrl_ll_bbpll_calibration_start();
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clk_ll_bbpll_set_config(pll_freq, xtal_freq);
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/* WAIT CALIBRATION DONE */
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while(!regi2c_ctrl_ll_bbpll_calibration_is_done());
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/* BBPLL CALIBRATION STOP */
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regi2c_ctrl_ll_bbpll_calibration_stop();
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s_cur_pll_freq = pll_freq;
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}
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@ -24,7 +24,7 @@
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static const char *TAG = "rtc_init";
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static void set_ocode_by_efuse(int calib_version);
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static void set_ocode_by_efuse(int ocode_scheme_ver);
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static void calibrate_ocode(void);
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static void set_rtc_dig_dbias(void);
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@ -38,14 +38,21 @@ void rtc_init(rtc_config_t cfg)
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REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_MIN_SLP_VAL, RTC_CNTL_MIN_SLP_VAL_MIN);
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if (cfg.cali_ocode) {
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uint32_t rtc_calib_version = 0;
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esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MINOR, &rtc_calib_version, ESP_EFUSE_BLK_VERSION_MINOR[0]->bit_count); // IDF-5366
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if (err != ESP_OK) {
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rtc_calib_version = 0;
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ESP_HW_LOGW(TAG, "efuse read fail, set default rtc_calib_version: %d\n", rtc_calib_version);
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uint8_t blk_version_minor = efuse_ll_get_blk_version_minor();
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uint8_t blk_version_major = efuse_ll_get_blk_version_major();
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bool ignore_major = efuse_ll_get_disable_blk_version_major();
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uint8_t ocode_scheme_ver = 0;
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if(blk_version_major > 0 && !ignore_major) {
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ESP_HW_LOGE(TAG, "Invalid blk_version_major.\n");
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abort();
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}
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if (rtc_calib_version == 1) {
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set_ocode_by_efuse(rtc_calib_version);
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if((blk_version_major > 0) || (blk_version_major == 0 && blk_version_minor >= 1)) {
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ocode_scheme_ver = 1;
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}
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if (ocode_scheme_ver == 1) {
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set_ocode_by_efuse(ocode_scheme_ver);
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} else {
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calibrate_ocode();
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}
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@ -126,10 +133,22 @@ void rtc_vddsdio_set_config(rtc_vddsdio_config_t config)
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{
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}
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static void set_ocode_by_efuse(int calib_version)
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static void set_ocode_by_efuse(int ocode_scheme_ver)
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{
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// ESP32C2-TODO: IDF-4940
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ESP_HW_LOGW(TAG, "set_ocode_by_efuse not supported yet");
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assert(ocode_scheme_ver == 1);
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// use efuse ocode.
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signed int ocode = 0;
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esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_OCODE, &ocode, ESP_EFUSE_OCODE[0]->bit_count);
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assert(err == ESP_OK);
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(void) err;
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//recover efuse data
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ocode = ((ocode & BIT(6)) != 0)? -(ocode & 0x3f): ocode;
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ocode = ocode + 100;
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//set ext_ocode
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REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_EXT_CODE, ocode);
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REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE, 1);
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}
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static void calibrate_ocode(void)
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@ -181,91 +200,113 @@ static void calibrate_ocode(void)
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rtc_clk_cpu_freq_set_config(&old_config);
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}
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static uint32_t get_dig_dbias_by_efuse(uint8_t chip_version)
|
||||
static uint32_t get_dig_dbias_by_efuse(uint8_t dbias_scheme_ver)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C2 //TODO: Need check for esp32c2
|
||||
return 0;
|
||||
#else
|
||||
assert(chip_version >= 3);
|
||||
uint32_t dig_dbias = 28;
|
||||
esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_DIG_DBIAS_HVT, &dig_dbias, 5);
|
||||
assert(dbias_scheme_ver == 1);
|
||||
uint32_t dig_dbias = 26;
|
||||
esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_DIG_DBIAS_HVT, &dig_dbias, ESP_EFUSE_DIG_DBIAS_HVT[0]->bit_count);
|
||||
if (err != ESP_OK) {
|
||||
dig_dbias = 28;
|
||||
dig_dbias = 26;
|
||||
ESP_HW_LOGW(TAG, "efuse read fail, set default dig_dbias value: %d\n", dig_dbias);
|
||||
}
|
||||
return dig_dbias;
|
||||
#endif
|
||||
}
|
||||
|
||||
uint32_t get_rtc_dbias_by_efuse(uint8_t chip_version, uint32_t dig_dbias)
|
||||
uint32_t get_rtc_dbias_by_efuse(uint8_t dbias_scheme_ver, uint32_t dig_dbias)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32C2 //TODO: Need check for esp32c2
|
||||
return 0;
|
||||
#else
|
||||
assert(chip_version >= 3);
|
||||
uint32_t rtc_dbias = 0;
|
||||
signed int k_rtc_ldo = 0, k_dig_ldo = 0, v_rtc_bias20 = 0, v_dig_bias20 = 0;
|
||||
esp_err_t err0 = esp_efuse_read_field_blob(ESP_EFUSE_K_RTC_LDO, &k_rtc_ldo, 7);
|
||||
esp_err_t err1 = esp_efuse_read_field_blob(ESP_EFUSE_K_DIG_LDO, &k_dig_ldo, 7);
|
||||
esp_err_t err2 = esp_efuse_read_field_blob(ESP_EFUSE_V_RTC_DBIAS20, &v_rtc_bias20, 8);
|
||||
esp_err_t err3 = esp_efuse_read_field_blob(ESP_EFUSE_V_DIG_DBIAS20, &v_dig_bias20, 8);
|
||||
if ((err0 != ESP_OK) | (err1 != ESP_OK) | (err2 != ESP_OK) | (err3 != ESP_OK)) {
|
||||
k_rtc_ldo = 0;
|
||||
k_dig_ldo = 0;
|
||||
v_rtc_bias20 = 0;
|
||||
v_dig_bias20 = 0;
|
||||
ESP_HW_LOGW(TAG, "efuse read fail, k_rtc_ldo: %d, k_dig_ldo: %d, v_rtc_bias20: %d, v_dig_bias20: %d\n", k_rtc_ldo, k_dig_ldo, v_rtc_bias20, v_dig_bias20);
|
||||
assert(dbias_scheme_ver == 1);
|
||||
uint32_t rtc_dbias = 31;
|
||||
|
||||
//read efuse data
|
||||
signed int dig_slp_dbias2 = 0, dig_slp_dbias26 = 0, dig_act_dbias26 = 0, dig_act_step = 0, rtc_slp_dbias29 = 0, rtc_slp_dbias31 = 0, rtc_act_dbias31 = 0, rtc_act_dbias13 = 0;
|
||||
esp_err_t err0 = esp_efuse_read_field_blob(ESP_EFUSE_DIG_LDO_SLP_DBIAS2, &dig_slp_dbias2, ESP_EFUSE_DIG_LDO_SLP_DBIAS2[0]->bit_count);
|
||||
esp_err_t err1 = esp_efuse_read_field_blob(ESP_EFUSE_DIG_LDO_SLP_DBIAS26, &dig_slp_dbias26, ESP_EFUSE_DIG_LDO_SLP_DBIAS26[0]->bit_count);
|
||||
esp_err_t err2 = esp_efuse_read_field_blob(ESP_EFUSE_DIG_LDO_ACT_DBIAS26, &dig_act_dbias26, ESP_EFUSE_DIG_LDO_ACT_DBIAS26[0]->bit_count);
|
||||
esp_err_t err3 = esp_efuse_read_field_blob(ESP_EFUSE_DIG_LDO_ACT_STEPD10, &dig_act_step, ESP_EFUSE_DIG_LDO_ACT_STEPD10[0]->bit_count);
|
||||
esp_err_t err4 = esp_efuse_read_field_blob(ESP_EFUSE_RTC_LDO_SLP_DBIAS29, &rtc_slp_dbias29, ESP_EFUSE_RTC_LDO_SLP_DBIAS29[0]->bit_count);
|
||||
esp_err_t err5 = esp_efuse_read_field_blob(ESP_EFUSE_RTC_LDO_SLP_DBIAS31, &rtc_slp_dbias31, ESP_EFUSE_RTC_LDO_SLP_DBIAS31[0]->bit_count);
|
||||
esp_err_t err6 = esp_efuse_read_field_blob(ESP_EFUSE_RTC_LDO_ACT_DBIAS31, &rtc_act_dbias31, ESP_EFUSE_RTC_LDO_ACT_DBIAS31[0]->bit_count);
|
||||
esp_err_t err7 = esp_efuse_read_field_blob(ESP_EFUSE_RTC_LDO_ACT_DBIAS13, &rtc_act_dbias13, ESP_EFUSE_RTC_LDO_ACT_DBIAS13[0]->bit_count);
|
||||
|
||||
if ((err0 != ESP_OK) | (err1 != ESP_OK) | (err2 != ESP_OK) | (err3 != ESP_OK) | (err4 != ESP_OK) | (err5 != ESP_OK) | (err6 != ESP_OK) | (err7 != ESP_OK)) {
|
||||
ESP_HW_LOGW(TAG, "efuse read fail, set default rtc_dbias value: %d\n", rtc_dbias);
|
||||
return rtc_dbias;
|
||||
}
|
||||
|
||||
k_rtc_ldo = ((k_rtc_ldo & BIT(6)) != 0)? -(k_rtc_ldo & 0x3f): k_rtc_ldo;
|
||||
k_dig_ldo = ((k_dig_ldo & BIT(6)) != 0)? -(k_dig_ldo & 0x3f): (uint8_t)k_dig_ldo;
|
||||
v_rtc_bias20 = ((v_rtc_bias20 & BIT(7)) != 0)? -(v_rtc_bias20 & 0x7f): (uint8_t)v_rtc_bias20;
|
||||
v_dig_bias20 = ((v_dig_bias20 & BIT(7)) != 0)? -(v_dig_bias20 & 0x7f): (uint8_t)v_dig_bias20;
|
||||
//recover dig&rtc parameter
|
||||
dig_slp_dbias2 = ((dig_slp_dbias2 & BIT(6)) != 0)? -(dig_slp_dbias2 & 0x3f): dig_slp_dbias2;
|
||||
dig_slp_dbias26 = ((dig_slp_dbias26 & BIT(7)) != 0)? -(dig_slp_dbias26 & 0x7f): dig_slp_dbias26;
|
||||
dig_act_dbias26 = ((dig_act_dbias26 & BIT(5)) != 0)? -(dig_act_dbias26 & 0x1f): dig_act_dbias26;
|
||||
dig_act_step = ((dig_act_step & BIT(3)) != 0)? -(dig_act_step & 0x7): dig_act_step;
|
||||
rtc_slp_dbias29 = ((rtc_slp_dbias29 & BIT(8)) != 0)? -(rtc_slp_dbias29 & 0xff): rtc_slp_dbias29;
|
||||
rtc_slp_dbias31 = ((rtc_slp_dbias31 & BIT(5)) != 0)? -(rtc_slp_dbias31 & 0x1f): rtc_slp_dbias31;
|
||||
rtc_act_dbias31 = ((rtc_act_dbias31 & BIT(5)) != 0)? -(rtc_act_dbias31 & 0x1f): rtc_act_dbias31;
|
||||
rtc_act_dbias13 = ((rtc_act_dbias13 & BIT(7)) != 0)? -(rtc_act_dbias13 & 0x7f): rtc_act_dbias13;
|
||||
|
||||
uint32_t v_rtc_dbias20_real_mul10000 = V_RTC_MID_MUL10000 + v_rtc_bias20 * 10000 / 500;
|
||||
uint32_t v_dig_dbias20_real_mul10000 = V_DIG_MID_MUL10000 + v_dig_bias20 * 10000 / 500;
|
||||
signed int k_rtc_ldo_real_mul10000 = K_RTC_MID_MUL10000 + k_rtc_ldo;
|
||||
signed int k_dig_ldo_real_mul10000 = K_DIG_MID_MUL10000 + k_dig_ldo;
|
||||
uint32_t v_dig_nearest_1v15_mul10000 = v_dig_dbias20_real_mul10000 + k_dig_ldo_real_mul10000 * (dig_dbias - 20);
|
||||
uint32_t v_rtc_nearest_1v15_mul10000 = 0;
|
||||
dig_slp_dbias2 = dig_slp_dbias2 + 705;
|
||||
dig_slp_dbias26 = dig_slp_dbias26 + dig_slp_dbias2 + 502;
|
||||
dig_act_dbias26 = dig_act_dbias26 + dig_slp_dbias26 + 10;
|
||||
signed int dig_slp_dbias9 = dig_slp_dbias26 - (dig_slp_dbias26 - dig_slp_dbias2) * 17 / 24;
|
||||
signed int dig_act_dbias9 = dig_slp_dbias9 + (dig_act_dbias26 - dig_slp_dbias26) - dig_act_step * 17 / 10;
|
||||
|
||||
rtc_slp_dbias29 = rtc_slp_dbias29 + 1160;
|
||||
rtc_slp_dbias31 = rtc_slp_dbias31 + rtc_slp_dbias29 + 37;
|
||||
rtc_act_dbias31 = rtc_act_dbias31 + rtc_slp_dbias31 + 8;
|
||||
rtc_act_dbias13 = rtc_act_dbias13 + 860;
|
||||
|
||||
//calculate digital LDO volt
|
||||
signed int dig_k_act = (dig_act_dbias26 - dig_act_dbias9) / 17;
|
||||
signed int dig_b_act = dig_act_dbias26 - dig_k_act * 26;
|
||||
uint32_t v_dig_cal = dig_k_act * dig_dbias + dig_b_act;
|
||||
|
||||
//calculate rtc_dbias with dig_volt
|
||||
signed int rtc_k_act = (rtc_act_dbias31 - rtc_act_dbias13) / 18;
|
||||
signed int rtc_b_act = rtc_act_dbias31 - rtc_k_act * 31;
|
||||
|
||||
uint32_t v_rtc_cal = 0;
|
||||
for (rtc_dbias = 15; rtc_dbias < 32; rtc_dbias++) {
|
||||
v_rtc_nearest_1v15_mul10000 = v_rtc_dbias20_real_mul10000 + k_rtc_ldo_real_mul10000 * (rtc_dbias - 20);
|
||||
if (v_rtc_nearest_1v15_mul10000 >= v_dig_nearest_1v15_mul10000 - 250)
|
||||
break;
|
||||
v_rtc_cal = rtc_k_act * rtc_dbias + rtc_b_act;
|
||||
if (v_rtc_cal >= v_dig_cal) {
|
||||
return rtc_dbias;
|
||||
}
|
||||
}
|
||||
|
||||
//can't find correct rtc-volt, rtc_dbias can use default value.
|
||||
rtc_dbias = 31;
|
||||
return rtc_dbias;
|
||||
#endif
|
||||
}
|
||||
|
||||
static void set_rtc_dig_dbias()
|
||||
{
|
||||
/*
|
||||
1. a reasonable dig_dbias which by scaning pvt to make 120 CPU run successful stored in efuse;
|
||||
2. also we store some value in efuse, include:
|
||||
k_rtc_ldo (slope of rtc voltage & rtc_dbias);
|
||||
k_dig_ldo (slope of digital voltage & digital_dbias);
|
||||
v_rtc_bias20 (rtc voltage when rtc dbais is 20);
|
||||
v_dig_bias20 (digital voltage when digital dbais is 20).
|
||||
3. a reasonable rtc_dbias can be calculated by a certion formula.
|
||||
2. a reasonable rtc_dbias can be calculated by a certion formula.
|
||||
*/
|
||||
uint32_t rtc_dbias = 31, dig_dbias = 26;
|
||||
uint8_t chip_version = efuse_hal_get_minor_chip_version();
|
||||
if (chip_version >= 3) {
|
||||
dig_dbias = get_dig_dbias_by_efuse(chip_version);
|
||||
uint8_t blk_version_minor = efuse_ll_get_blk_version_minor();
|
||||
uint8_t blk_version_major = efuse_ll_get_blk_version_major();
|
||||
bool ignore_major = efuse_ll_get_disable_blk_version_major();
|
||||
|
||||
uint8_t dbias_scheme_ver = 0;
|
||||
if(blk_version_major > 0 && !ignore_major) {
|
||||
ESP_HW_LOGE(TAG, "Invalid blk_version_major.\n");
|
||||
abort();
|
||||
}
|
||||
if((blk_version_major > 0) || (blk_version_major == 0 && blk_version_minor >= 1)) {
|
||||
dbias_scheme_ver = 1;
|
||||
}
|
||||
|
||||
if (dbias_scheme_ver == 1) {
|
||||
dig_dbias = get_dig_dbias_by_efuse(dbias_scheme_ver);
|
||||
if (dig_dbias != 0) {
|
||||
if (dig_dbias + 4 > 28) {
|
||||
dig_dbias = 28;
|
||||
} else {
|
||||
dig_dbias += 4;
|
||||
}
|
||||
rtc_dbias = get_rtc_dbias_by_efuse(chip_version, dig_dbias); // already burn dig_dbias in efuse
|
||||
rtc_dbias = get_rtc_dbias_by_efuse(dbias_scheme_ver, dig_dbias); // already burn dig_dbias in efuse
|
||||
} else {
|
||||
dig_dbias = 28;
|
||||
ESP_HW_LOGD(TAG, "not burn core voltage in efuse or burn wrong voltage value in chip version: 0%d\n", chip_version);
|
||||
dig_dbias = 26;
|
||||
ESP_HW_LOGD(TAG, "not burn core voltage in efuse or burn wrong voltage value. blk_ver: %d.%d\n", blk_version_major, blk_version_minor);
|
||||
}
|
||||
}
|
||||
else {
|
||||
ESP_HW_LOGD(TAG, "chip_version is less than 3, not burn core voltage in efuse\n");
|
||||
ESP_HW_LOGD(TAG, "core voltage not burnt in efuse. blk_ver: %d.%d\n", blk_version_major, blk_version_minor);
|
||||
}
|
||||
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, rtc_dbias);
|
||||
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, dig_dbias);
|
||||
|
|
|
|||
|
|
@ -39,6 +39,25 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibrati
|
|||
REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop BBPLL self-calibration
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_stop(void)
|
||||
{
|
||||
REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
|
||||
REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check whether BBPLL calibration is done
|
||||
*
|
||||
* @return True if calibration is done; otherwise false
|
||||
*/
|
||||
static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibration_is_done(void)
|
||||
{
|
||||
return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
#define I2C_MST_ANA_CONF0_REG 0x6004E840
|
||||
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
|
||||
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
|
||||
#define I2C_MST_BBPLL_CAL_DONE (BIT(24))
|
||||
|
||||
#define ANA_CONFIG_REG 0x6004E844
|
||||
#define ANA_CONFIG_S (8)
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue