From 3dc89437cc22968148efc15bd54c754cdd22a485 Mon Sep 17 00:00:00 2001 From: zlq Date: Wed, 17 Aug 2022 17:25:59 +0800 Subject: [PATCH] support auto adjust LDO voltage based on pvt-dig --- components/efuse/esp32c2/esp_efuse_table.c | 146 +++++++++----- components/efuse/esp32c2/esp_efuse_table.csv | 25 +-- .../efuse/esp32c2/include/esp_efuse_table.h | 18 +- .../esp_hw_support/port/esp32c2/rtc_clk.c | 4 + .../esp_hw_support/port/esp32c2/rtc_init.c | 179 +++++++++++------- .../hal/esp32c2/include/hal/regi2c_ctrl_ll.h | 19 ++ .../soc/esp32c2/include/soc/regi2c_defs.h | 1 + 7 files changed, 260 insertions(+), 132 deletions(-) diff --git a/components/efuse/esp32c2/esp_efuse_table.c b/components/efuse/esp32c2/esp_efuse_table.c index fc2a0102e8..695b589801 100644 --- a/components/efuse/esp32c2/esp_efuse_table.c +++ b/components/efuse/esp32c2/esp_efuse_table.c @@ -9,7 +9,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table ef050bc1e4bf0d8384aa3e4c0256d7d3 +// md5_digest_table 5bc3d3149d5d4c75461337fa415d6533 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -176,30 +176,10 @@ static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = { {EFUSE_BLK2, 60, 2}, // BLK_VERSION_MAJOR, }; -static const esp_efuse_desc_t LDO_VOL_BIAS_CONFIG_HIGH[] = { - {EFUSE_BLK2, 64, 27}, // EFUSE_LDO_VOL_BIAS_CONFIG_HIGH, -}; - static const esp_efuse_desc_t PVT_LOW[] = { {EFUSE_BLK2, 91, 5}, // EFUSE_PVT_LOW, }; -static const esp_efuse_desc_t PVT_HIGH[] = { - {EFUSE_BLK2, 96, 10}, // EFUSE_PVT_HIGH, -}; - -static const esp_efuse_desc_t ADC_CALIBRATION_0[] = { - {EFUSE_BLK2, 106, 22}, // EFUSE_ADC_CALIBRATION_0, -}; - -static const esp_efuse_desc_t ADC_CALIBRATION_1[] = { - {EFUSE_BLK2, 128, 32}, // EFUSE_ADC_CALIBRATION_1, -}; - -static const esp_efuse_desc_t ADC_CALIBRATION_2[] = { - {EFUSE_BLK2, 160, 32}, // EFUSE_ADC_CALIBRATION_2, -}; - static const esp_efuse_desc_t KEY0[] = { {EFUSE_BLK3, 0, 256}, // [256bit FE key] or [128bit FE key and 128key SB key] or [user data], }; @@ -216,6 +196,50 @@ static const esp_efuse_desc_t KEY0_SB_128BIT[] = { {EFUSE_BLK3, 128, 128}, // [128bit SB key], }; +static const esp_efuse_desc_t OCODE[] = { + {EFUSE_BLK2, 62, 7}, // OCode, +}; + +static const esp_efuse_desc_t DIG_DBIAS_HVT[] = { + {EFUSE_BLK2, 105, 5}, // BLOCK2 digital dbias when hvt, +}; + +static const esp_efuse_desc_t DIG_LDO_SLP_DBIAS2[] = { + {EFUSE_BLK2, 110, 7}, // BLOCK2 DIG_LDO_DBG0_DBIAS2, +}; + +static const esp_efuse_desc_t DIG_LDO_SLP_DBIAS26[] = { + {EFUSE_BLK2, 117, 8}, // BLOCK2 DIG_LDO_DBG0_DBIAS26, +}; + +static const esp_efuse_desc_t DIG_LDO_ACT_DBIAS26[] = { + {EFUSE_BLK2, 125, 6}, // BLOCK2 DIG_LDO_ACT_DBIAS26, +}; + +static const esp_efuse_desc_t DIG_LDO_ACT_STEPD10[] = { + {EFUSE_BLK2, 131, 4}, // BLOCK2 DIG_LDO_ACT_STEPD10, +}; + +static const esp_efuse_desc_t RTC_LDO_SLP_DBIAS13[] = { + {EFUSE_BLK2, 135, 7}, // BLOCK2 DIG_LDO_SLP_DBIAS13, +}; + +static const esp_efuse_desc_t RTC_LDO_SLP_DBIAS29[] = { + {EFUSE_BLK2, 142, 9}, // BLOCK2 DIG_LDO_SLP_DBIAS29, +}; + +static const esp_efuse_desc_t RTC_LDO_SLP_DBIAS31[] = { + {EFUSE_BLK2, 151, 6}, // BLOCK2 DIG_LDO_SLP_DBIAS31, +}; + +static const esp_efuse_desc_t RTC_LDO_ACT_DBIAS31[] = { + {EFUSE_BLK2, 157, 6}, // BLOCK2 DIG_LDO_ACT_DBIAS31, +}; + +static const esp_efuse_desc_t RTC_LDO_ACT_DBIAS13[] = { + {EFUSE_BLK2, 163, 8}, // BLOCK2 DIG_LDO_ACT_DBIAS13, +}; + @@ -420,36 +444,11 @@ const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_LDO_VOL_BIAS_CONFIG_HIGH[] = { - &LDO_VOL_BIAS_CONFIG_HIGH[0], // EFUSE_LDO_VOL_BIAS_CONFIG_HIGH - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_PVT_LOW[] = { &PVT_LOW[0], // EFUSE_PVT_LOW NULL }; -const esp_efuse_desc_t* ESP_EFUSE_PVT_HIGH[] = { - &PVT_HIGH[0], // EFUSE_PVT_HIGH - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC_CALIBRATION_0[] = { - &ADC_CALIBRATION_0[0], // EFUSE_ADC_CALIBRATION_0 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC_CALIBRATION_1[] = { - &ADC_CALIBRATION_1[0], // EFUSE_ADC_CALIBRATION_1 - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_ADC_CALIBRATION_2[] = { - &ADC_CALIBRATION_2[0], // EFUSE_ADC_CALIBRATION_2 - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = { &KEY0[0], // [256bit FE key] or [128bit FE key and 128key SB key] or [user data] NULL @@ -469,3 +468,58 @@ const esp_efuse_desc_t* ESP_EFUSE_KEY0_SB_128BIT[] = { &KEY0_SB_128BIT[0], // [128bit SB key] NULL }; + +const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = { + &OCODE[0], // OCode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[] = { + &DIG_DBIAS_HVT[0], // BLOCK2 digital dbias when hvt + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIG_LDO_SLP_DBIAS2[] = { + &DIG_LDO_SLP_DBIAS2[0], // BLOCK2 DIG_LDO_DBG0_DBIAS2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIG_LDO_SLP_DBIAS26[] = { + &DIG_LDO_SLP_DBIAS26[0], // BLOCK2 DIG_LDO_DBG0_DBIAS26 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIG_LDO_ACT_DBIAS26[] = { + &DIG_LDO_ACT_DBIAS26[0], // BLOCK2 DIG_LDO_ACT_DBIAS26 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIG_LDO_ACT_STEPD10[] = { + &DIG_LDO_ACT_STEPD10[0], // BLOCK2 DIG_LDO_ACT_STEPD10 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_SLP_DBIAS13[] = { + &RTC_LDO_SLP_DBIAS13[0], // BLOCK2 DIG_LDO_SLP_DBIAS13 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_SLP_DBIAS29[] = { + &RTC_LDO_SLP_DBIAS29[0], // BLOCK2 DIG_LDO_SLP_DBIAS29 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_SLP_DBIAS31[] = { + &RTC_LDO_SLP_DBIAS31[0], // BLOCK2 DIG_LDO_SLP_DBIAS31 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_ACT_DBIAS31[] = { + &RTC_LDO_ACT_DBIAS31[0], // BLOCK2 DIG_LDO_ACT_DBIAS31 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_ACT_DBIAS13[] = { + &RTC_LDO_ACT_DBIAS13[0], // BLOCK2 DIG_LDO_ACT_DBIAS13 + NULL +}; diff --git a/components/efuse/esp32c2/esp_efuse_table.csv b/components/efuse/esp32c2/esp_efuse_table.csv index 1980df2b2f..fc3826c903 100644 --- a/components/efuse/esp32c2/esp_efuse_table.csv +++ b/components/efuse/esp32c2/esp_efuse_table.csv @@ -71,22 +71,25 @@ BLK_VERSION_MAJOR, EFUSE_BLK2, 60, 2, BLK_VERSION_MAJOR # EFUSE_RD_BLK2_DATA2_REG - LDO_VOL_BIAS_CONFIG_HIGH, EFUSE_BLK2, 64, 27, EFUSE_LDO_VOL_BIAS_CONFIG_HIGH PVT_LOW, EFUSE_BLK2, 91, 5, EFUSE_PVT_LOW - # EFUSE_RD_BLK2_DATA3_REG - PVT_HIGH, EFUSE_BLK2, 96, 10, EFUSE_PVT_HIGH - ADC_CALIBRATION_0, EFUSE_BLK2, 106, 22, EFUSE_ADC_CALIBRATION_0 - - # EFUSE_RD_BLK2_DATA4_REG - ADC_CALIBRATION_1, EFUSE_BLK2, 128, 32, EFUSE_ADC_CALIBRATION_1 - - # EFUSE_RD_BLK2_DATA5_REG - ADC_CALIBRATION_2, EFUSE_BLK2, 160, 32, EFUSE_ADC_CALIBRATION_2 - ################ KEY0, EFUSE_BLK3, 0, 256, [256bit FE key] or [128bit FE key and 128key SB key] or [user data] KEY0.FE_256BIT, EFUSE_BLK3, 0, 256, [256bit FE key] KEY0.FE_128BIT, EFUSE_BLK3, 0, 128, [128bit FE key] KEY0.SB_128BIT, EFUSE_BLK3, 128, 128, [128bit SB key] + +# AUTO CONFIG DIG&RTC DBIAS# +################ +OCODE, EFUSE_BLK2, 62, 7, OCode +DIG_DBIAS_HVT, EFUSE_BLK2, 105, 5, BLOCK2 digital dbias when hvt +DIG_LDO_SLP_DBIAS2, EFUSE_BLK2, 110, 7, BLOCK2 DIG_LDO_DBG0_DBIAS2 +DIG_LDO_SLP_DBIAS26, EFUSE_BLK2, 117, 8, BLOCK2 DIG_LDO_DBG0_DBIAS26 +DIG_LDO_ACT_DBIAS26, EFUSE_BLK2, 125, 6, BLOCK2 DIG_LDO_ACT_DBIAS26 +DIG_LDO_ACT_STEPD10, EFUSE_BLK2, 131, 4, BLOCK2 DIG_LDO_ACT_STEPD10 +RTC_LDO_SLP_DBIAS13, EFUSE_BLK2, 135, 7, BLOCK2 DIG_LDO_SLP_DBIAS13 +RTC_LDO_SLP_DBIAS29, EFUSE_BLK2, 142, 9, BLOCK2 DIG_LDO_SLP_DBIAS29 +RTC_LDO_SLP_DBIAS31, EFUSE_BLK2, 151, 6, BLOCK2 DIG_LDO_SLP_DBIAS31 +RTC_LDO_ACT_DBIAS31, EFUSE_BLK2, 157, 6, BLOCK2 DIG_LDO_ACT_DBIAS31 +RTC_LDO_ACT_DBIAS13, EFUSE_BLK2, 163, 8, BLOCK2 DIG_LDO_ACT_DBIAS13 diff --git a/components/efuse/esp32c2/include/esp_efuse_table.h b/components/efuse/esp32c2/include/esp_efuse_table.h index ac64e1d74f..9d348f1971 100644 --- a/components/efuse/esp32c2/include/esp_efuse_table.h +++ b/components/efuse/esp32c2/include/esp_efuse_table.h @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table ef050bc1e4bf0d8384aa3e4c0256d7d3 +// md5_digest_table 5bc3d3149d5d4c75461337fa415d6533 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -56,16 +56,22 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VOL_BIAS_CONFIG_HIGH[]; extern const esp_efuse_desc_t* ESP_EFUSE_PVT_LOW[]; -extern const esp_efuse_desc_t* ESP_EFUSE_PVT_HIGH[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC_CALIBRATION_0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC_CALIBRATION_1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC_CALIBRATION_2[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY0_FE_256BIT[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY0_FE_128BIT[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY0_SB_128BIT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIG_LDO_SLP_DBIAS2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIG_LDO_SLP_DBIAS26[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIG_LDO_ACT_DBIAS26[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIG_LDO_ACT_STEPD10[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_SLP_DBIAS13[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_SLP_DBIAS29[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_SLP_DBIAS31[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_ACT_DBIAS31[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RTC_LDO_ACT_DBIAS13[]; #ifdef __cplusplus } diff --git a/components/esp_hw_support/port/esp32c2/rtc_clk.c b/components/esp_hw_support/port/esp32c2/rtc_clk.c index 405da8a802..73516f5865 100644 --- a/components/esp_hw_support/port/esp32c2/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c2/rtc_clk.c @@ -126,6 +126,10 @@ static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq) /* Analog part */ regi2c_ctrl_ll_bbpll_calibration_start(); clk_ll_bbpll_set_config(pll_freq, xtal_freq); + /* WAIT CALIBRATION DONE */ + while(!regi2c_ctrl_ll_bbpll_calibration_is_done()); + /* BBPLL CALIBRATION STOP */ + regi2c_ctrl_ll_bbpll_calibration_stop(); s_cur_pll_freq = pll_freq; } diff --git a/components/esp_hw_support/port/esp32c2/rtc_init.c b/components/esp_hw_support/port/esp32c2/rtc_init.c index 1399d91b50..a3740c788e 100644 --- a/components/esp_hw_support/port/esp32c2/rtc_init.c +++ b/components/esp_hw_support/port/esp32c2/rtc_init.c @@ -24,7 +24,7 @@ static const char *TAG = "rtc_init"; -static void set_ocode_by_efuse(int calib_version); +static void set_ocode_by_efuse(int ocode_scheme_ver); static void calibrate_ocode(void); static void set_rtc_dig_dbias(void); @@ -38,14 +38,21 @@ void rtc_init(rtc_config_t cfg) REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_MIN_SLP_VAL, RTC_CNTL_MIN_SLP_VAL_MIN); if (cfg.cali_ocode) { - uint32_t rtc_calib_version = 0; - esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MINOR, &rtc_calib_version, ESP_EFUSE_BLK_VERSION_MINOR[0]->bit_count); // IDF-5366 - if (err != ESP_OK) { - rtc_calib_version = 0; - ESP_HW_LOGW(TAG, "efuse read fail, set default rtc_calib_version: %d\n", rtc_calib_version); + uint8_t blk_version_minor = efuse_ll_get_blk_version_minor(); + uint8_t blk_version_major = efuse_ll_get_blk_version_major(); + bool ignore_major = efuse_ll_get_disable_blk_version_major(); + + uint8_t ocode_scheme_ver = 0; + if(blk_version_major > 0 && !ignore_major) { + ESP_HW_LOGE(TAG, "Invalid blk_version_major.\n"); + abort(); } - if (rtc_calib_version == 1) { - set_ocode_by_efuse(rtc_calib_version); + if((blk_version_major > 0) || (blk_version_major == 0 && blk_version_minor >= 1)) { + ocode_scheme_ver = 1; + } + + if (ocode_scheme_ver == 1) { + set_ocode_by_efuse(ocode_scheme_ver); } else { calibrate_ocode(); } @@ -126,10 +133,22 @@ void rtc_vddsdio_set_config(rtc_vddsdio_config_t config) { } -static void set_ocode_by_efuse(int calib_version) +static void set_ocode_by_efuse(int ocode_scheme_ver) { - // ESP32C2-TODO: IDF-4940 - ESP_HW_LOGW(TAG, "set_ocode_by_efuse not supported yet"); + assert(ocode_scheme_ver == 1); + // use efuse ocode. + signed int ocode = 0; + esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_OCODE, &ocode, ESP_EFUSE_OCODE[0]->bit_count); + assert(err == ESP_OK); + (void) err; + + //recover efuse data + ocode = ((ocode & BIT(6)) != 0)? -(ocode & 0x3f): ocode; + ocode = ocode + 100; + + //set ext_ocode + REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_EXT_CODE, ocode); + REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE, 1); } static void calibrate_ocode(void) @@ -181,91 +200,113 @@ static void calibrate_ocode(void) rtc_clk_cpu_freq_set_config(&old_config); } -static uint32_t get_dig_dbias_by_efuse(uint8_t chip_version) +static uint32_t get_dig_dbias_by_efuse(uint8_t dbias_scheme_ver) { -#if CONFIG_IDF_TARGET_ESP32C2 //TODO: Need check for esp32c2 - return 0; -#else - assert(chip_version >= 3); - uint32_t dig_dbias = 28; - esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_DIG_DBIAS_HVT, &dig_dbias, 5); + assert(dbias_scheme_ver == 1); + uint32_t dig_dbias = 26; + esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_DIG_DBIAS_HVT, &dig_dbias, ESP_EFUSE_DIG_DBIAS_HVT[0]->bit_count); if (err != ESP_OK) { - dig_dbias = 28; + dig_dbias = 26; ESP_HW_LOGW(TAG, "efuse read fail, set default dig_dbias value: %d\n", dig_dbias); } return dig_dbias; -#endif } -uint32_t get_rtc_dbias_by_efuse(uint8_t chip_version, uint32_t dig_dbias) +uint32_t get_rtc_dbias_by_efuse(uint8_t dbias_scheme_ver, uint32_t dig_dbias) { -#if CONFIG_IDF_TARGET_ESP32C2 //TODO: Need check for esp32c2 - return 0; -#else - assert(chip_version >= 3); - uint32_t rtc_dbias = 0; - signed int k_rtc_ldo = 0, k_dig_ldo = 0, v_rtc_bias20 = 0, v_dig_bias20 = 0; - esp_err_t err0 = esp_efuse_read_field_blob(ESP_EFUSE_K_RTC_LDO, &k_rtc_ldo, 7); - esp_err_t err1 = esp_efuse_read_field_blob(ESP_EFUSE_K_DIG_LDO, &k_dig_ldo, 7); - esp_err_t err2 = esp_efuse_read_field_blob(ESP_EFUSE_V_RTC_DBIAS20, &v_rtc_bias20, 8); - esp_err_t err3 = esp_efuse_read_field_blob(ESP_EFUSE_V_DIG_DBIAS20, &v_dig_bias20, 8); - if ((err0 != ESP_OK) | (err1 != ESP_OK) | (err2 != ESP_OK) | (err3 != ESP_OK)) { - k_rtc_ldo = 0; - k_dig_ldo = 0; - v_rtc_bias20 = 0; - v_dig_bias20 = 0; - ESP_HW_LOGW(TAG, "efuse read fail, k_rtc_ldo: %d, k_dig_ldo: %d, v_rtc_bias20: %d, v_dig_bias20: %d\n", k_rtc_ldo, k_dig_ldo, v_rtc_bias20, v_dig_bias20); + assert(dbias_scheme_ver == 1); + uint32_t rtc_dbias = 31; + + //read efuse data + signed int dig_slp_dbias2 = 0, dig_slp_dbias26 = 0, dig_act_dbias26 = 0, dig_act_step = 0, rtc_slp_dbias29 = 0, rtc_slp_dbias31 = 0, rtc_act_dbias31 = 0, rtc_act_dbias13 = 0; + esp_err_t err0 = esp_efuse_read_field_blob(ESP_EFUSE_DIG_LDO_SLP_DBIAS2, &dig_slp_dbias2, ESP_EFUSE_DIG_LDO_SLP_DBIAS2[0]->bit_count); + esp_err_t err1 = esp_efuse_read_field_blob(ESP_EFUSE_DIG_LDO_SLP_DBIAS26, &dig_slp_dbias26, ESP_EFUSE_DIG_LDO_SLP_DBIAS26[0]->bit_count); + esp_err_t err2 = esp_efuse_read_field_blob(ESP_EFUSE_DIG_LDO_ACT_DBIAS26, &dig_act_dbias26, ESP_EFUSE_DIG_LDO_ACT_DBIAS26[0]->bit_count); + esp_err_t err3 = esp_efuse_read_field_blob(ESP_EFUSE_DIG_LDO_ACT_STEPD10, &dig_act_step, ESP_EFUSE_DIG_LDO_ACT_STEPD10[0]->bit_count); + esp_err_t err4 = esp_efuse_read_field_blob(ESP_EFUSE_RTC_LDO_SLP_DBIAS29, &rtc_slp_dbias29, ESP_EFUSE_RTC_LDO_SLP_DBIAS29[0]->bit_count); + esp_err_t err5 = esp_efuse_read_field_blob(ESP_EFUSE_RTC_LDO_SLP_DBIAS31, &rtc_slp_dbias31, ESP_EFUSE_RTC_LDO_SLP_DBIAS31[0]->bit_count); + esp_err_t err6 = esp_efuse_read_field_blob(ESP_EFUSE_RTC_LDO_ACT_DBIAS31, &rtc_act_dbias31, ESP_EFUSE_RTC_LDO_ACT_DBIAS31[0]->bit_count); + esp_err_t err7 = esp_efuse_read_field_blob(ESP_EFUSE_RTC_LDO_ACT_DBIAS13, &rtc_act_dbias13, ESP_EFUSE_RTC_LDO_ACT_DBIAS13[0]->bit_count); + + if ((err0 != ESP_OK) | (err1 != ESP_OK) | (err2 != ESP_OK) | (err3 != ESP_OK) | (err4 != ESP_OK) | (err5 != ESP_OK) | (err6 != ESP_OK) | (err7 != ESP_OK)) { + ESP_HW_LOGW(TAG, "efuse read fail, set default rtc_dbias value: %d\n", rtc_dbias); + return rtc_dbias; } - k_rtc_ldo = ((k_rtc_ldo & BIT(6)) != 0)? -(k_rtc_ldo & 0x3f): k_rtc_ldo; - k_dig_ldo = ((k_dig_ldo & BIT(6)) != 0)? -(k_dig_ldo & 0x3f): (uint8_t)k_dig_ldo; - v_rtc_bias20 = ((v_rtc_bias20 & BIT(7)) != 0)? -(v_rtc_bias20 & 0x7f): (uint8_t)v_rtc_bias20; - v_dig_bias20 = ((v_dig_bias20 & BIT(7)) != 0)? -(v_dig_bias20 & 0x7f): (uint8_t)v_dig_bias20; + //recover dig&rtc parameter + dig_slp_dbias2 = ((dig_slp_dbias2 & BIT(6)) != 0)? -(dig_slp_dbias2 & 0x3f): dig_slp_dbias2; + dig_slp_dbias26 = ((dig_slp_dbias26 & BIT(7)) != 0)? -(dig_slp_dbias26 & 0x7f): dig_slp_dbias26; + dig_act_dbias26 = ((dig_act_dbias26 & BIT(5)) != 0)? -(dig_act_dbias26 & 0x1f): dig_act_dbias26; + dig_act_step = ((dig_act_step & BIT(3)) != 0)? -(dig_act_step & 0x7): dig_act_step; + rtc_slp_dbias29 = ((rtc_slp_dbias29 & BIT(8)) != 0)? -(rtc_slp_dbias29 & 0xff): rtc_slp_dbias29; + rtc_slp_dbias31 = ((rtc_slp_dbias31 & BIT(5)) != 0)? -(rtc_slp_dbias31 & 0x1f): rtc_slp_dbias31; + rtc_act_dbias31 = ((rtc_act_dbias31 & BIT(5)) != 0)? -(rtc_act_dbias31 & 0x1f): rtc_act_dbias31; + rtc_act_dbias13 = ((rtc_act_dbias13 & BIT(7)) != 0)? -(rtc_act_dbias13 & 0x7f): rtc_act_dbias13; - uint32_t v_rtc_dbias20_real_mul10000 = V_RTC_MID_MUL10000 + v_rtc_bias20 * 10000 / 500; - uint32_t v_dig_dbias20_real_mul10000 = V_DIG_MID_MUL10000 + v_dig_bias20 * 10000 / 500; - signed int k_rtc_ldo_real_mul10000 = K_RTC_MID_MUL10000 + k_rtc_ldo; - signed int k_dig_ldo_real_mul10000 = K_DIG_MID_MUL10000 + k_dig_ldo; - uint32_t v_dig_nearest_1v15_mul10000 = v_dig_dbias20_real_mul10000 + k_dig_ldo_real_mul10000 * (dig_dbias - 20); - uint32_t v_rtc_nearest_1v15_mul10000 = 0; + dig_slp_dbias2 = dig_slp_dbias2 + 705; + dig_slp_dbias26 = dig_slp_dbias26 + dig_slp_dbias2 + 502; + dig_act_dbias26 = dig_act_dbias26 + dig_slp_dbias26 + 10; + signed int dig_slp_dbias9 = dig_slp_dbias26 - (dig_slp_dbias26 - dig_slp_dbias2) * 17 / 24; + signed int dig_act_dbias9 = dig_slp_dbias9 + (dig_act_dbias26 - dig_slp_dbias26) - dig_act_step * 17 / 10; + + rtc_slp_dbias29 = rtc_slp_dbias29 + 1160; + rtc_slp_dbias31 = rtc_slp_dbias31 + rtc_slp_dbias29 + 37; + rtc_act_dbias31 = rtc_act_dbias31 + rtc_slp_dbias31 + 8; + rtc_act_dbias13 = rtc_act_dbias13 + 860; + + //calculate digital LDO volt + signed int dig_k_act = (dig_act_dbias26 - dig_act_dbias9) / 17; + signed int dig_b_act = dig_act_dbias26 - dig_k_act * 26; + uint32_t v_dig_cal = dig_k_act * dig_dbias + dig_b_act; + + //calculate rtc_dbias with dig_volt + signed int rtc_k_act = (rtc_act_dbias31 - rtc_act_dbias13) / 18; + signed int rtc_b_act = rtc_act_dbias31 - rtc_k_act * 31; + + uint32_t v_rtc_cal = 0; for (rtc_dbias = 15; rtc_dbias < 32; rtc_dbias++) { - v_rtc_nearest_1v15_mul10000 = v_rtc_dbias20_real_mul10000 + k_rtc_ldo_real_mul10000 * (rtc_dbias - 20); - if (v_rtc_nearest_1v15_mul10000 >= v_dig_nearest_1v15_mul10000 - 250) - break; + v_rtc_cal = rtc_k_act * rtc_dbias + rtc_b_act; + if (v_rtc_cal >= v_dig_cal) { + return rtc_dbias; + } } + + //can't find correct rtc-volt, rtc_dbias can use default value. + rtc_dbias = 31; return rtc_dbias; -#endif } static void set_rtc_dig_dbias() { /* 1. a reasonable dig_dbias which by scaning pvt to make 120 CPU run successful stored in efuse; - 2. also we store some value in efuse, include: - k_rtc_ldo (slope of rtc voltage & rtc_dbias); - k_dig_ldo (slope of digital voltage & digital_dbias); - v_rtc_bias20 (rtc voltage when rtc dbais is 20); - v_dig_bias20 (digital voltage when digital dbais is 20). - 3. a reasonable rtc_dbias can be calculated by a certion formula. + 2. a reasonable rtc_dbias can be calculated by a certion formula. */ uint32_t rtc_dbias = 31, dig_dbias = 26; - uint8_t chip_version = efuse_hal_get_minor_chip_version(); - if (chip_version >= 3) { - dig_dbias = get_dig_dbias_by_efuse(chip_version); + uint8_t blk_version_minor = efuse_ll_get_blk_version_minor(); + uint8_t blk_version_major = efuse_ll_get_blk_version_major(); + bool ignore_major = efuse_ll_get_disable_blk_version_major(); + + uint8_t dbias_scheme_ver = 0; + if(blk_version_major > 0 && !ignore_major) { + ESP_HW_LOGE(TAG, "Invalid blk_version_major.\n"); + abort(); + } + if((blk_version_major > 0) || (blk_version_major == 0 && blk_version_minor >= 1)) { + dbias_scheme_ver = 1; + } + + if (dbias_scheme_ver == 1) { + dig_dbias = get_dig_dbias_by_efuse(dbias_scheme_ver); if (dig_dbias != 0) { - if (dig_dbias + 4 > 28) { - dig_dbias = 28; - } else { - dig_dbias += 4; - } - rtc_dbias = get_rtc_dbias_by_efuse(chip_version, dig_dbias); // already burn dig_dbias in efuse + rtc_dbias = get_rtc_dbias_by_efuse(dbias_scheme_ver, dig_dbias); // already burn dig_dbias in efuse } else { - dig_dbias = 28; - ESP_HW_LOGD(TAG, "not burn core voltage in efuse or burn wrong voltage value in chip version: 0%d\n", chip_version); + dig_dbias = 26; + ESP_HW_LOGD(TAG, "not burn core voltage in efuse or burn wrong voltage value. blk_ver: %d.%d\n", blk_version_major, blk_version_minor); } } else { - ESP_HW_LOGD(TAG, "chip_version is less than 3, not burn core voltage in efuse\n"); + ESP_HW_LOGD(TAG, "core voltage not burnt in efuse. blk_ver: %d.%d\n", blk_version_major, blk_version_minor); } REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, rtc_dbias); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, dig_dbias); diff --git a/components/hal/esp32c2/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32c2/include/hal/regi2c_ctrl_ll.h index 53c0a9c8e3..3c222e38e4 100644 --- a/components/hal/esp32c2/include/hal/regi2c_ctrl_ll.h +++ b/components/hal/esp32c2/include/hal/regi2c_ctrl_ll.h @@ -39,6 +39,25 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibrati REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); } +/** + * @brief Stop BBPLL self-calibration + */ +static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_stop(void) +{ + REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW); + REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH); +} + +/** + * @brief Check whether BBPLL calibration is done + * + * @return True if calibration is done; otherwise false + */ +static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibration_is_done(void) +{ + return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE); +} + /** * @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC register */ diff --git a/components/soc/esp32c2/include/soc/regi2c_defs.h b/components/soc/esp32c2/include/soc/regi2c_defs.h index cf181685ed..715a62271b 100644 --- a/components/soc/esp32c2/include/soc/regi2c_defs.h +++ b/components/soc/esp32c2/include/soc/regi2c_defs.h @@ -13,6 +13,7 @@ #define I2C_MST_ANA_CONF0_REG 0x6004E840 #define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2)) #define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3)) +#define I2C_MST_BBPLL_CAL_DONE (BIT(24)) #define ANA_CONFIG_REG 0x6004E844 #define ANA_CONFIG_S (8)