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Merge branch 'refactor/common_rom_uart_apis' into 'master' 

esp_rom: extract common uart apis into esp_rom_uart.h

See merge request espressif/esp-idf!9313
pull/5688/head
Angus Gratton 2020-07-21 15:24:21 +08:00
rodzic 3755fb6597 345606e7f3
commit 442736c5d6
44 zmienionych plików z 274 dodań i 150 usunięć
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5
components/bootloader/subproject/Makefile
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@ -8,15 +8,14 @@ endif
PROJECT_NAME := bootloader
COMPONENTS := esptool_py bootloader_support log spi_flash micro-ecc soc main efuse
COMPONENTS := esptool_py bootloader_support log spi_flash micro-ecc soc main efuse esp_rom
# Clear C and CXX from top level project
CFLAGS =
CXXFLAGS =
#We cannot include the idf_target, esp_rom, esp_common component directly but we need their includes.
#We cannot include the idf_target, esp_common component directly but we need their includes.
CFLAGS += -I $(IDF_PATH)/components/$(IDF_TARGET)/include
CFLAGS += -I $(IDF_PATH)/components/esp_rom/include
CFLAGS += -I $(IDF_PATH)/components/esp_common/include
CFLAGS += -I $(IDF_PATH)/components/xtensa/include -I $(IDF_PATH)/components/xtensa/$(IDF_TARGET)/include

5
components/bootloader_support/src/bootloader_clock.c
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@ -19,14 +19,13 @@
#include "soc/rtc_cntl_reg.h"
#ifdef CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/uart.h"
#include "esp32/rom/rtc.h"
#define CPU_RESET_REASON SW_CPU_RESET
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/uart.h"
#include "esp32s2/rom/rtc.h"
#define CPU_RESET_REASON RTC_SW_CPU_RESET
#endif
#include "esp_rom_uart.h"
void bootloader_clock_configure(void)
{
@ -35,7 +34,7 @@ void bootloader_clock_configure(void)
// This is not needed on power on reset, when ROM bootloader is running at
// 40 MHz. But in case of TG WDT reset, CPU may still be running at >80 MHZ,
// and will be done with the bootloader much earlier than UART FIFO is empty.
uart_tx_wait_idle(0);
esp_rom_uart_tx_wait_idle(0);
/* Set CPU to 80MHz. Keep other clocks unmodified. */
int cpu_freq_mhz = 80;

16
components/bootloader_support/src/bootloader_console.c
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@ -23,14 +23,13 @@
#include "hal/clk_gate_ll.h"
#ifdef CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/uart.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/rom/uart.h"
#include "esp32s2/rom/usb/cdc_acm.h"
#include "esp32s2/rom/usb/usb_common.h"
#endif
#include "esp_rom_gpio.h"
#include "esp_rom_uart.h"
#ifdef CONFIG_ESP_CONSOLE_UART_NONE
void bootloader_console_init(void)
@ -48,7 +47,7 @@ void bootloader_console_init(void)
ets_install_uart_printf();
// Wait for UART FIFO to be empty.
uart_tx_wait_idle(0);
esp_rom_uart_tx_wait_idle(0);
#if CONFIG_ESP_CONSOLE_UART_CUSTOM
// Some constants to make the following code less upper-case
@ -56,7 +55,7 @@ void bootloader_console_init(void)
const int uart_rx_gpio = CONFIG_ESP_CONSOLE_UART_RX_GPIO;
// Switch to the new UART (this just changes UART number used for
// ets_printf in ROM code).
uart_tx_switch(uart_num);
esp_rom_uart_set_as_console(uart_num);
// If console is attached to UART1 or if non-default pins are used,
// need to reconfigure pins using GPIO matrix
if (uart_num != 0 ||
@ -78,14 +77,13 @@ void bootloader_console_init(void)
#endif // CONFIG_ESP_CONSOLE_UART_CUSTOM
// Set configured UART console baud rate
const int uart_baud = CONFIG_ESP_CONSOLE_UART_BAUDRATE;
uart_div_modify(uart_num, (rtc_clk_apb_freq_get() << 4) / uart_baud);
esp_rom_uart_set_clock_baudrate(uart_num, rtc_clk_apb_freq_get(), CONFIG_ESP_CONSOLE_UART_BAUDRATE);
}
#endif // CONFIG_ESP_CONSOLE_UART
#ifdef CONFIG_ESP_CONSOLE_USB_CDC
/* Buffer for CDC data structures. No RX buffer allocated. */
static char s_usb_cdc_buf[CDC_ACM_WORK_BUF_MIN];
static char s_usb_cdc_buf[ESP_ROM_CDC_ACM_WORK_BUF_MIN];
void bootloader_console_init(void)
{
@ -96,8 +94,8 @@ void bootloader_console_init(void)
rom_usb_cdc_set_descriptor_patch();
#endif
Uart_Init_USB(s_usb_cdc_buf, sizeof(s_usb_cdc_buf));
uart_tx_switch(ROM_UART_USB);
esp_rom_uart_usb_acm_init(s_usb_cdc_buf, sizeof(s_usb_cdc_buf));
esp_rom_uart_set_as_console(ESP_ROM_UART_USB);
ets_install_putc1(bootloader_console_write_char_usb);
}
#endif //CONFIG_ESP_CONSOLE_USB_CDC

7
components/bootloader_support/src/bootloader_console_loader.c
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@ -20,12 +20,11 @@
#include <stddef.h>
#include "sdkconfig.h"
#include "bootloader_console.h"
#include "esp_rom_uart.h"
#ifdef CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/uart.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/rom/uart.h"
#include "esp32s2/rom/usb/chip_usb_dw_wrapper.h"
#include "esp32s2/rom/usb/usb_dc.h"
#include "esp32s2/rom/usb/cdc_acm.h"
@ -33,7 +32,7 @@
#endif
#ifdef CONFIG_ESP_CONSOLE_USB_CDC
/* The following functions replace ets_write_char_uart, uart_tx_one_char,
/* The following functions replace ets_write_char_uart, esp_rom_uart_tx_one_char,
* and uart_tx_one_char_uart ROM functions. The main difference is that
* uart_tx_one_char_uart calls cdc_acm_fifo_fill for each byte passed to it,
* which results in very slow console output. The version here uses a TX buffer.
@ -73,7 +72,7 @@ void bootloader_console_deinit(void)
{
#ifdef CONFIG_ESP_CONSOLE_UART
/* Ensure any buffered log output is displayed */
uart_tx_flush(CONFIG_ESP_CONSOLE_UART_NUM);
esp_rom_uart_flush_tx(CONFIG_ESP_CONSOLE_UART_NUM);
#endif // CONFIG_ESP_CONSOLE_UART
#ifdef CONFIG_ESP_CONSOLE_USB_CDC

5
components/bootloader_support/src/bootloader_utility.c
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@ -24,20 +24,19 @@
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/rtc.h"
#include "esp32/rom/uart.h"
#include "esp32/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/cache.h"
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/rom/spi_flash.h"
#include "esp32s2/rom/rtc.h"
#include "esp32s2/rom/uart.h"
#include "esp32s2/rom/secure_boot.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#else
#error "Unsupported IDF_TARGET"
#endif
#include "esp_rom_uart.h"
#include "soc/soc.h"
#include "soc/cpu.h"
@ -612,7 +611,7 @@ static void load_image(const esp_image_metadata_t *image_data)
so issue a system reset to ensure flash encryption
cache resets properly */
ESP_LOGI(TAG, "Resetting with flash encryption enabled...");
uart_tx_wait_idle(0);
esp_rom_uart_tx_wait_idle(0);
bootloader_reset();
}
#endif

1
components/bootloader_support/src/esp32/bootloader_esp32.c
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@ -40,7 +40,6 @@
#include "esp_rom_efuse.h"
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/rtc.h"
#include "esp32/rom/uart.h"
static const char *TAG = "boot.esp32";

11
components/driver/test/test_gpio.c
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@ -13,12 +13,7 @@
#include "freertos/task.h"
#include "freertos/queue.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/uart.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/uart.h"
#endif
#include "esp_rom_uart.h"
#define WAKE_UP_IGNORE 1 // gpio_wakeup function development is not completed yet, set it deprecated.
@ -130,10 +125,10 @@ static void prompt_to_continue(const char* str)
char sign[5] = {0};
while(strlen(sign) == 0) {
/* Flush anything already in the RX buffer */
while(uart_rx_one_char((uint8_t *) sign) == OK) {
while(esp_rom_uart_rx_one_char((uint8_t *) sign) == ETS_OK) {
}
/* Read line */
UartRxString((uint8_t*) sign, sizeof(sign) - 1);
esp_rom_uart_rx_string((uint8_t*) sign, sizeof(sign) - 1);
}
}

11
components/driver/test/touch_sensor_test/touch_scope.c
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@ -15,7 +15,7 @@
#include <string.h>
#include "esp_err.h"
#include "driver/uart.h"
#include "esp32s2/rom/uart.h"
#include "esp_rom_uart.h"
#define ROM_UART_DRIVER_ENABLE 0
@ -128,9 +128,9 @@ int test_tp_print_to_scope(float *data, unsigned char channel_num)
return 0;
} else {
#if ROM_UART_DRIVER_ENABLE
uart_tx_wait_idle(uart_num); // Default print uart mumber is 0.
esp_rom_uart_tx_wait_idle(uart_num); // Default print uart mumber is 0.
for(int i=0; i<out_len; i++) {
uart_tx_one_char(out_data[i]);
esp_rom_uart_tx_one_char(out_data[i]);
}
return out_len;
#else
@ -162,10 +162,9 @@ int test_tp_print_to_scope(float *data, unsigned char channel_num)
esp_err_t test_tp_scope_debug_init(uint8_t uart_num, int tx_io_num, int rx_io_num, int baud_rate)
{
#if ROM_UART_DRIVER_ENABLE
uart_tx_wait_idle(0); // Default print uart mumber is 0.
esp_rom_uart_tx_wait_idle(0); // Default print uart mumber is 0.
if(uart_num != 0) {
uart_tx_switch(uart_num);
// uart_div_modify(uart_num, baud_rate); //DivLatchValue : (clock << 4)/baudrate.
esp_rom_uart_set_as_console(uart_num);
}
#else
if(uart_used == uart_num) {

1
components/esp32/crosscore_int.c
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@ -20,7 +20,6 @@
#include "esp_debug_helpers.h"
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/uart.h"
#include "soc/cpu.h"
#include "soc/dport_reg.h"

1
components/esp32/dport_access.c
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@ -27,7 +27,6 @@
#include "esp_err.h"
#include "esp_intr_alloc.h"
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/uart.h"
#include "soc/cpu.h"
#include "soc/dport_reg.h"

4
components/esp32/sleep_modes.c
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@ -24,7 +24,7 @@
#include "esp_spi_flash.h"
#include "esp32/rom/cache.h"
#include "esp32/rom/rtc.h"
#include "esp32/rom/uart.h"
#include "esp_rom_uart.h"
#include "soc/cpu.h"
#include "soc/rtc.h"
#include "soc/spi_periph.h"
@ -151,7 +151,7 @@ void esp_deep_sleep(uint64_t time_in_us)
static void IRAM_ATTR flush_uarts(void)
{
for (int i = 0; i < 3; ++i) {
uart_tx_wait_idle(i);
esp_rom_uart_tx_wait_idle(i);
}
}

8
components/esp32/system_api_esp32.c
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@ -21,7 +21,7 @@
#include "esp_log.h"
#include "sdkconfig.h"
#include "esp32/rom/cache.h"
#include "esp32/rom/uart.h"
#include "esp_rom_uart.h"
#include "soc/dport_reg.h"
#include "soc/gpio_periph.h"
#include "soc/efuse_periph.h"
@ -78,9 +78,9 @@ void IRAM_ATTR esp_restart_noos(void)
wdt_hal_write_protect_enable(&wdt1_context);
// Flush any data left in UART FIFOs
uart_tx_wait_idle(0);
uart_tx_wait_idle(1);
uart_tx_wait_idle(2);
esp_rom_uart_tx_wait_idle(0);
esp_rom_uart_tx_wait_idle(1);
esp_rom_uart_tx_wait_idle(2);
#ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
if (esp_ptr_external_ram(get_sp())) {

1
components/esp32/test/test_aes_sha_rsa.c
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@ -10,7 +10,6 @@
#include "soc/cpu.h"
#include "unity.h"
#include "test_utils.h"
#include "esp32/rom/uart.h"
#include "esp32/rom/sha.h"
#include "soc/uart_periph.h"
#include "soc/dport_reg.h"

13
components/esp32/test/test_dport.c
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@ -12,8 +12,9 @@
#include "soc/cpu.h"
#include "unity.h"
#include "test_utils.h"
#include "esp32/rom/uart.h"
#include "soc/uart_periph.h"
#include "esp_rom_uart.h"
#include "hal/uart_types.h"
#include "hal/uart_ll.h"
#include "soc/dport_reg.h"
#include "soc/rtc.h"
#include "esp_intr_alloc.h"
@ -127,9 +128,9 @@ void run_tasks_with_change_freq_cpu(int cpu_freq_mhz)
bool res = rtc_clk_cpu_freq_mhz_to_config(cpu_freq_mhz, &new_config);
assert(res && "invalid frequency value");
uart_tx_wait_idle(uart_num);
esp_rom_uart_tx_wait_idle(uart_num);
rtc_clk_cpu_freq_set_config(&new_config);
uart_div_modify(uart_num, (rtc_clk_apb_freq_get() << 4) / uart_baud);
uart_ll_set_baudrate(UART_LL_GET_HW(uart_num), UART_SCLK_APB, uart_baud);
/* adjust RTOS ticks */
_xt_tick_divisor = cpu_freq_mhz * 1000000 / XT_TICK_PER_SEC;
vTaskDelay(2);
@ -139,9 +140,9 @@ void run_tasks_with_change_freq_cpu(int cpu_freq_mhz)
run_tasks("accessDPORT", accessDPORT, "accessAPB", accessAPB, 10000);
// return old freq.
uart_tx_wait_idle(uart_num);
esp_rom_uart_tx_wait_idle(uart_num);
rtc_clk_cpu_freq_set_config(&old_config);
uart_div_modify(uart_num, (rtc_clk_apb_freq_get() << 4) / uart_baud);
uart_ll_set_baudrate(UART_LL_GET_HW(uart_num), UART_SCLK_APB, uart_baud);
_xt_tick_divisor = old_config.freq_mhz * 1000000 / XT_TICK_PER_SEC;
}

9
components/esp32/test/test_sleep.c
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@ -4,12 +4,13 @@
#include "esp_sleep.h"
#include "esp32/clk.h"
#include "driver/rtc_io.h"
#include "esp32/rom/uart.h"
#include "esp_rom_uart.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "soc/gpio_periph.h"
#include "soc/uart_periph.h"
#include "hal/uart_types.h"
#include "hal/uart_ll.h"
#include "soc/rtc.h" // for wakeup trigger defines
#include "soc/rtc_periph.h" // for read rtc registers directly (cause)
#include "soc/soc.h" // for direct register read macros
@ -175,9 +176,7 @@ TEST_CASE("light sleep duration is correct", "[deepsleep][ignore]")
TEST_CASE("light sleep and frequency switching", "[deepsleep]")
{
#ifndef CONFIG_PM_ENABLE
const int uart_clk_freq = REF_CLK_FREQ;
CLEAR_PERI_REG_MASK(UART_CONF0_REG(CONFIG_ESP_CONSOLE_UART_NUM), UART_TICK_REF_ALWAYS_ON);
uart_div_modify(CONFIG_ESP_CONSOLE_UART_NUM, (uart_clk_freq << 4) / CONFIG_ESP_CONSOLE_UART_BAUDRATE);
uart_ll_set_baudrate(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), UART_SCLK_REF_TICK, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
#endif
rtc_cpu_freq_config_t config_xtal, config_default;

2
components/esp32s2/CMakeLists.txt
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@ -30,7 +30,7 @@ else()
set(include_dirs "include")
set(requires driver efuse soc) #unfortunately rom/uart uses SOC registers directly
set(requires driver efuse)
# driver is a public requirement because esp_sleep.h uses gpio_num_t & touch_pad_t
# app_update is added here because cpu_start.c uses esp_ota_get_app_description() function.

1
components/esp32s2/crosscore_int.c
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@ -20,7 +20,6 @@
#include "esp_debug_helpers.h"
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/rom/uart.h"
#include "soc/cpu.h"
#include "soc/dport_reg.h"

4
components/esp32s2/sleep_modes.c
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@ -24,8 +24,8 @@
#include "esp_spi_flash.h"
#include "esp32s2/rom/cache.h"
#include "esp32s2/rom/rtc.h"
#include "esp32s2/rom/uart.h"
#include "esp32s2/rom/ets_sys.h"
#include "esp_rom_uart.h"
#include "soc/cpu.h"
#include "soc/rtc.h"
#include "soc/spi_periph.h"
@ -145,7 +145,7 @@ static void IRAM_ATTR flush_uarts(void)
{
for (int i = 0; i < SOC_UART_NUM; ++i) {
if (periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) {
uart_tx_wait_idle(i);
esp_rom_uart_tx_wait_idle(i);
}
}
}

6
components/esp32s2/system_api_esp32s2.c
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@ -20,7 +20,7 @@
#include "esp_wifi.h"
#include "esp_log.h"
#include "esp32s2/rom/cache.h"
#include "esp32s2/rom/uart.h"
#include "esp_rom_uart.h"
#include "soc/dport_reg.h"
#include "soc/gpio_reg.h"
#include "soc/rtc_cntl_reg.h"
@ -70,8 +70,8 @@ void IRAM_ATTR esp_restart_noos(void)
wdt_hal_write_protect_enable(&wdt1_context);
// Flush any data left in UART FIFOs
uart_tx_wait_idle(0);
uart_tx_wait_idle(1);
esp_rom_uart_tx_wait_idle(0);
esp_rom_uart_tx_wait_idle(1);
// Disable cache
Cache_Disable_ICache();
Cache_Disable_DCache();

2
components/esp_rom/CMakeLists.txt
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@ -1,6 +1,6 @@
idf_build_get_property(target IDF_TARGET)
idf_component_register(SRCS "patches/esp_rom_crc.c"
idf_component_register(SRCS "patches/esp_rom_crc.c" "patches/esp_rom_uart.c"
INCLUDE_DIRS include
PRIV_INCLUDE_DIRS "${target}"
PRIV_REQUIRES soc)

4
components/esp_rom/component.mk
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@ -1,3 +1,7 @@
COMPONENT_ADD_INCLUDEDIRS := include
COMPONENT_SRCDIRS := patches
COMPONENT_PRIV_INCLUDEDIRS := esp32
#Linker scripts used to link the final application.
#Warning: These linker scripts are only used when the normal app is compiled; the bootloader
#specifies its own scripts.

7
components/esp_rom/esp32/ld/esp32.rom.api.ld
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@ -19,3 +19,10 @@ PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out );
PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 );
PROVIDE ( esp_rom_efuse_get_flash_gpio_info = ets_efuse_get_spiconfig );
PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled );
PROVIDE ( esp_rom_uart_flush_tx = uart_tx_flush );
PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char );
PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle );
PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char );
PROVIDE ( esp_rom_uart_rx_string = UartRxString );
PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );

8
components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld
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@ -17,3 +17,11 @@ PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 );
PROVIDE ( esp_rom_efuse_get_flash_gpio_info = ets_efuse_get_spiconfig );
PROVIDE ( esp_rom_efuse_get_flash_wp_gpio = ets_efuse_get_wp_pad );
PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled );
PROVIDE ( esp_rom_uart_flush_tx = uart_tx_flush );
PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char );
PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle );
PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char );
PROVIDE ( esp_rom_uart_rx_string = UartRxString );
PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
PROVIDE ( esp_rom_uart_usb_acm_init = Uart_Init_USB );

8
components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld
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@ -20,3 +20,11 @@ PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 );
PROVIDE ( esp_rom_efuse_get_flash_gpio_info = ets_efuse_get_spiconfig );
PROVIDE ( esp_rom_efuse_get_flash_wp_gpio = ets_efuse_get_wp_pad );
PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled );
PROVIDE ( esp_rom_uart_flush_tx = uart_tx_flush );
PROVIDE ( esp_rom_uart_tx_one_char = uart_tx_one_char );
PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle );
PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char );
PROVIDE ( esp_rom_uart_rx_string = UartRxString );
PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
PROVIDE ( esp_rom_uart_usb_acm_init = Uart_Init_USB );

10
components/esp_rom/include/esp32s2/rom/uart.h
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@ -162,14 +162,6 @@ typedef struct {
int received;
} UartDevice;
typedef enum {
ROM_UART_0,
ROM_UART_1,
ROM_UART_USB
} rom_uart_num_t;
#define CDC_ACM_WORK_BUF_MIN 128
/**
* @brief Init uart device struct value and reset uart0/uart1 rx.
* Please do not call this function in SDK.
@ -436,7 +428,7 @@ uint8_t UartConnCheck(uint8_t uart_no);
/**
* @brief Initialize the USB ACM UART
* Needs to be fed a buffer of at least 128 bytes (CDC_ACM_WORK_BUF_MIN),
* Needs to be fed a buffer of at least 128 bytes (ESP_ROM_CDC_ACM_WORK_BUF_MIN),
* plus any rx buffer you may want to have.
*
* @param cdc_acm_work_mem Pointer to work mem for CDC-ACM code

101
components/esp_rom/include/esp_rom_uart.h 100644
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@ -0,0 +1,101 @@
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#define ESP_ROM_CDC_ACM_WORK_BUF_MIN 128
typedef enum {
ESP_ROM_UART_0,
ESP_ROM_UART_1,
ESP_ROM_UART_USB
} esp_rom_uart_num_t;
/**
* @brief Wait for UART TX FIFO is empty and all data has been sent out.
*
* @param uart_no UART port number
*/
void esp_rom_uart_tx_wait_idle(uint8_t uart_no);
/**
* @brief Set clock source and baud rate for UART.
*
* @param uart_no UART port number
* @param clock_hz Source clock (in Hz)
* @param baud_rate Baud rate to set
*/
void esp_rom_uart_set_clock_baudrate(uint8_t uart_no, uint32_t clock_hz, uint32_t baud_rate);
/**
* @brief Wait until UART TX FIFO is empty (i.e. flush TX FIFO)
*
* @param uart_no UART port number
*/
void esp_rom_uart_flush_tx(uint8_t uart_no);
/**
* @brief Transmit one character to the console channel.
*
* @param c Character to send
* @return
* - 0 on success
* - 1 on failure
*/
int esp_rom_uart_tx_one_char(uint8_t c);
/**
* @brief Get one character from the console channel.
*
* @param c Where to store the character
* @return
* - 0 on success
* - 1 on failure or no data available
*/
int esp_rom_uart_rx_one_char(uint8_t *c);
/**
* @brief Get one line of string from console channel (line ending won't be stored in the buffer).
*
* @param str Where to store the string
* @param max_len Maximum length of the buffer (including the NULL delimiter)
* @return always return 0 when on success or wait in a loop for rx data
*/
int esp_rom_uart_rx_string(uint8_t *str, uint8_t max_len);
/**
* @brief Set the UART port used by ets_printf.
*
* @param uart_no UART port number
*/
void esp_rom_uart_set_as_console(uint8_t uart_no);
/**
* @brief Initialize the USB ACM UART
* @note The ACM working memroy should be at least 128 bytes (ESP_ROM_CDC_ACM_WORK_BUF_MIN) in size.
*
* @param cdc_acm_work_mem Pointer to the work memroy used for CDC-ACM
* @param cdc_acm_work_mem_len Length of work memory
*/
void esp_rom_uart_usb_acm_init(void *cdc_acm_work_mem, int cdc_acm_work_mem_len);
#ifdef __cplusplus
}
#endif

48
components/esp_rom/patches/esp_rom_uart.c 100644
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@ -0,0 +1,48 @@
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stdint.h>
#include <stdlib.h>
#include "esp_attr.h"
#include "sdkconfig.h"
#include "hal/uart_ll.h"
#include "soc/uart_struct.h"
#if CONFIG_IDF_TARGET_ESP32
/**
* The function defined in ROM code has a bug, so we re-implement it here.
*/
IRAM_ATTR void esp_rom_uart_tx_wait_idle(uint8_t uart_no)
{
uart_dev_t *device = NULL;
switch (uart_no) {
case 0:
device = &UART0;
break;
case 1:
device = &UART1;
break;
default:
device = &UART2;
break;
}
while (!uart_ll_is_tx_idle(device));
}
#endif
IRAM_ATTR void esp_rom_uart_set_clock_baudrate(uint8_t uart_no, uint32_t clock_hz, uint32_t baud_rate)
{
extern void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue);
uart_div_modify(uart_no, (clock_hz << 4) / baud_rate);
}

28
components/esp_system/port/cpu_start.c
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@ -22,6 +22,8 @@
#include "esp_log.h"
#include "esp_system.h"
#include "esp_rom_uart.h"
#include "esp_clk_internal.h"
#include "esp_rom_efuse.h"
#include "sdkconfig.h"
@ -30,7 +32,6 @@
#include "esp32/cache_err_int.h"
#include "esp32/rom/cache.h"
#include "esp32/rom/rtc.h"
#include "esp32/rom/uart.h"
#include "esp32/spiram.h"
#include "esp32/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S2
@ -40,7 +41,6 @@
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/rom/rtc.h"
#include "esp32s2/spiram.h"
#include "esp32s2/rom/uart.h"
#include "soc/periph_defs.h"
#include "esp32s2/dport_access.h"
#include "esp32s2/memprot.h"
@ -116,9 +116,8 @@ void IRAM_ATTR call_start_cpu1(void)
ets_install_putc1(NULL);
ets_install_putc2(NULL);
#else // CONFIG_ESP_CONSOLE_UART_NONE
uartAttach();
ets_install_uart_printf();
uart_tx_switch(CONFIG_ESP_CONSOLE_UART_NUM);
esp_rom_uart_set_as_console(CONFIG_ESP_CONSOLE_UART_NUM);
#endif
DPORT_REG_SET_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_PDEBUG_ENABLE | DPORT_APP_CPU_RECORD_ENABLE);
@ -171,7 +170,7 @@ static void start_other_core(void)
volatile bool cpus_up = false;
while (!cpus_up){
while (!cpus_up) {
cpus_up = true;
for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
cpus_up &= s_cpu_up[i];
@ -218,9 +217,9 @@ void IRAM_ATTR call_start_cpu0(void)
// from panic handler we can be reset by RWDT or TG0WDT
if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
|| rst_reas[1] == RTCWDT_SYS_RESET || rst_reas[1] == TG0WDT_SYS_RESET
|| rst_reas[1] == RTCWDT_SYS_RESET || rst_reas[1] == TG0WDT_SYS_RESET
#endif
) {
) {
wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
wdt_hal_write_protect_disable(&rtc_wdt_ctx);
wdt_hal_disable(&rtc_wdt_ctx);
@ -339,11 +338,11 @@ void IRAM_ATTR call_start_cpu0(void)
//Enable trace memory and immediately start trace.
#if CONFIG_ESP32_TRAX || CONFIG_ESP32S2_TRAX
#if CONFIG_IDF_TARGET_ESP32
#if CONFIG_ESP32_TRAX_TWOBANKS
trax_enable(TRAX_ENA_PRO_APP);
#else
trax_enable(TRAX_ENA_PRO);
#endif
#if CONFIG_ESP32_TRAX_TWOBANKS
trax_enable(TRAX_ENA_PRO_APP);
#else
trax_enable(TRAX_ENA_PRO);
#endif
#elif CONFIG_IDF_TARGET_ESP32S2
trax_enable(TRAX_ENA_PRO);
#endif
@ -355,8 +354,7 @@ void IRAM_ATTR call_start_cpu0(void)
intr_matrix_clear();
#ifdef CONFIG_ESP_CONSOLE_UART
const int uart_clk_freq = APB_CLK_FREQ;
uart_div_modify(CONFIG_ESP_CONSOLE_UART_NUM, (uart_clk_freq << 4) / CONFIG_ESP_CONSOLE_UART_BAUDRATE);
esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_UART_NUM, APB_CLK_FREQ, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
#endif
rtcio_hal_unhold_all();
@ -389,7 +387,7 @@ void IRAM_ATTR call_start_cpu0(void)
#else
// This assumes that DROM is the first segment in the application binary, i.e. that we can read
// the binary header through cache by accessing SOC_DROM_LOW address.
memcpy(&fhdr, (void*) SOC_DROM_LOW, sizeof(fhdr));
memcpy(&fhdr, (void *) SOC_DROM_LOW, sizeof(fhdr));
#endif // CONFIG_APP_BUILD_TYPE_ELF_RAM
// If psram is uninitialized, we need to improve some flash configuration.

4
components/esp_system/port/esp32/clk.c
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@ -27,8 +27,8 @@
#include "esp_log.h"
#include "esp32/clk.h"
#include "esp32/rom/uart.h"
#include "esp32/rom/rtc.h"
#include "esp_rom_uart.h"
#include "sdkconfig.h"
@ -188,7 +188,7 @@ void esp_clk_init(void)
// Wait for UART TX to finish, otherwise some UART output will be lost
// when switching APB frequency
if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
}
rtc_clk_cpu_freq_set_config(&new_config);

4
components/esp_system/port/esp32s2/clk.c
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@ -23,8 +23,8 @@
#include "esp32s2/clk.h"
#include "esp_clk_internal.h"
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/rom/uart.h"
#include "esp32s2/rom/rtc.h"
#include "esp_rom_uart.h"
#include "soc/system_reg.h"
#include "soc/dport_access.h"
#include "soc/soc.h"
@ -133,7 +133,7 @@ void esp_clk_init(void)
// Wait for UART TX to finish, otherwise some UART output will be lost
// when switching APB frequency
if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
}
rtc_clk_cpu_freq_set_config(&new_config);

4
components/esp_system/port/esp32s2/usb_console.c
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@ -29,7 +29,7 @@
#include "soc/usb_reg.h"
#include "soc/spinlock.h"
#include "hal/soc_hal.h"
#include "esp32s2/rom/uart.h"
#include "esp_rom_uart.h"
#include "esp32s2/rom/usb/usb_dc.h"
#include "esp32s2/rom/usb/cdc_acm.h"
#include "esp32s2/rom/usb/usb_dfu.h"
@ -39,7 +39,7 @@
#include "esp32s2/rom/usb/chip_usb_dw_wrapper.h"
#define CDC_WORK_BUF_SIZE (CDC_ACM_WORK_BUF_MIN + CONFIG_ESP_CONSOLE_USB_CDC_RX_BUF_SIZE)
#define CDC_WORK_BUF_SIZE (ESP_ROM_CDC_ACM_WORK_BUF_MIN + CONFIG_ESP_CONSOLE_USB_CDC_RX_BUF_SIZE)
typedef enum {
REBOOT_NONE,

3
components/esp_system/port/panic_handler.c
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@ -35,14 +35,11 @@
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/cache_err_int.h"
#include "esp32/dport_access.h"
#include "esp32/rom/uart.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/cache_err_int.h"
#include "esp32s2/rom/uart.h"
#include "esp32s2/memprot.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"

8
components/esp_system/startup.c
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@ -26,6 +26,8 @@
#include "soc/soc_caps.h"
#include "hal/wdt_hal.h"
#include "hal/uart_types.h"
#include "hal/uart_ll.h"
#include "esp_system.h"
#include "esp_log.h"
@ -56,12 +58,10 @@
// [refactor-todo] make this file completely target-independent
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/uart.h"
#include "esp32/rom/ets_sys.h"
#include "esp32/spiram.h"
#include "esp32/brownout.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/uart.h"
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/spiram.h"
#include "esp32s2/brownout.h"
@ -355,10 +355,8 @@ void IRAM_ATTR start_cpu0_default(void)
IRAM_ATTR ESP_SYSTEM_INIT_FN(init_components0, BIT(0))
{
#if defined(CONFIG_PM_ENABLE) && defined(CONFIG_ESP_CONSOLE_UART)
const int uart_clk_freq = REF_CLK_FREQ;
/* When DFS is enabled, use REFTICK as UART clock source */
CLEAR_PERI_REG_MASK(UART_CONF0_REG(CONFIG_ESP_CONSOLE_UART_NUM), UART_TICK_REF_ALWAYS_ON);
uart_div_modify(CONFIG_ESP_CONSOLE_UART_NUM, (uart_clk_freq << 4) / CONFIG_ESP_CONSOLE_UART_BAUDRATE);
uart_ll_set_baudrate(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), UART_SCLK_REF_TICK, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
#endif // CONFIG_ESP_CONSOLE_UART_NONE
#ifdef CONFIG_PM_ENABLE

8
components/esp_system/system_api.c
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@ -7,10 +7,8 @@
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "panic_internal.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/uart.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/uart.h"
#include "esp_rom_uart.h"
#if CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/memprot.h"
#endif
@ -46,7 +44,7 @@ void IRAM_ATTR esp_restart_noos_dig(void)
{
// make sure all the panic handler output is sent from UART FIFO
if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
}
// switch to XTAL (otherwise we will keep running from the PLL)

11
components/newlib/syscalls.c
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@ -21,12 +21,7 @@
#include <reent.h>
#include <sys/fcntl.h>
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/uart.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/uart.h"
#endif
#include "esp_rom_uart.h"
static int syscall_not_implemented(void)
{
@ -44,7 +39,7 @@ ssize_t _write_r_console(struct _reent *r, int fd, const void * data, size_t siz
const char* cdata = (const char*) data;
if (fd == STDOUT_FILENO || fd == STDERR_FILENO) {
for (size_t i = 0; i < size; ++i) {
uart_tx_one_char(cdata[i]);
esp_rom_uart_tx_one_char(cdata[i]);
}
return size;
}
@ -58,7 +53,7 @@ ssize_t _read_r_console(struct _reent *r, int fd, void * data, size_t size)
if (fd == STDIN_FILENO) {
size_t received;
for (received = 0; received < size; ++received) {
int status = uart_rx_one_char((uint8_t*) &cdata[received]);
int status = esp_rom_uart_rx_one_char((uint8_t*) &cdata[received]);
if (status != 0) {
break;
}

1
components/soc/src/esp32/rtc_clk.c
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@ -18,7 +18,6 @@
#include <stdlib.h>
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/rtc.h"
#include "esp32/rom/uart.h"
#include "esp_rom_gpio.h"
#include "soc/rtc.h"
#include "soc/rtc_periph.h"

4
components/soc/src/esp32/rtc_clk_init.c
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@ -18,7 +18,7 @@
#include <stdlib.h>
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/rtc.h"
#include "esp32/rom/uart.h"
#include "esp_rom_uart.h"
#include "soc/rtc.h"
#include "soc/rtc_periph.h"
#include "soc/sens_periph.h"
@ -104,7 +104,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
xtal_freq, est_xtal_freq);
}
}
uart_tx_wait_idle(0);
esp_rom_uart_tx_wait_idle(0);
rtc_clk_xtal_freq_update(xtal_freq);
rtc_clk_apb_freq_update(xtal_freq * MHZ);

1
components/soc/src/esp32s2/rtc_clk.c
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@ -20,7 +20,6 @@
#include "sdkconfig.h"
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/rom/rtc.h"
#include "esp32s2/rom/uart.h"
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/rtc_io_reg.h"

5
components/soc/src/esp32s2/rtc_clk_init.c
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@ -16,9 +16,8 @@
#include <stdint.h>
#include <stddef.h>
#include <stdlib.h>
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/rom/rtc.h"
#include "esp32s2/rom/uart.h"
#include "esp_rom_uart.h"
#include "soc/rtc.h"
#include "soc/rtc_periph.h"
#include "soc/sens_periph.h"
@ -58,7 +57,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_APLL_M | I2C_BBPLL_M);
rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
uart_tx_wait_idle(0);
esp_rom_uart_tx_wait_idle(0);
rtc_clk_xtal_freq_update(xtal_freq);
rtc_clk_apb_freq_update(xtal_freq * MHZ);

5
components/soc/test/test_rtc_clk.c
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@ -13,13 +13,12 @@
#include "freertos/semphr.h"
#include "esp_rom_gpio.h"
extern void rtc_clk_select_rtc_slow_clk(void);
#include "esp_rom_uart.h"
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
#include "esp32/clk.h"
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/uart.h"
#define CALIBRATE_ONE(cali_clk) calibrate_one(cali_clk, #cali_clk)
@ -101,7 +100,7 @@ TEST_CASE("Output 8M XTAL clock to GPIO25", "[rtc_clk][ignore]")
static void test_clock_switching(void (*switch_func)(const rtc_cpu_freq_config_t* config))
{
uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
const int test_duration_sec = 10;
ref_clock_init();

17
components/unity/unity_port_esp32.c
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@ -15,12 +15,11 @@
#include "unity.h"
#include "sdkconfig.h"
#include "soc/cpu.h"
#include "esp_rom_uart.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/clk.h"
#include "esp32/rom/uart.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/clk.h"
#include "esp32s2/rom/uart.h"
#endif
static uint32_t s_test_start, s_test_stop;
@ -28,17 +27,17 @@ static uint32_t s_test_start, s_test_stop;
void unity_putc(int c)
{
if (c == '\n') {
uart_tx_one_char('\r');
uart_tx_one_char('\n');
esp_rom_uart_tx_one_char('\r');
esp_rom_uart_tx_one_char('\n');
} else if (c == '\r') {
} else {
uart_tx_one_char(c);
esp_rom_uart_tx_one_char(c);
}
}
void unity_flush(void)
{
uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
}
/* To start a unit test from a GDB session without console input,
@ -60,16 +59,16 @@ void unity_gets(char *dst, size_t len)
memset(unity_input_from_gdb, 0, sizeof(unity_input_from_gdb));
return;
}
/* UartRxString length argument is uint8_t */
/* esp_rom_uart_rx_string length argument is uint8_t */
if (len >= UINT8_MAX) {
len = UINT8_MAX;
}
/* Flush anything already in the RX buffer */
uint8_t ignore;
while (uart_rx_one_char(&ignore) == OK) {
while (esp_rom_uart_rx_one_char(&ignore) == 0) {
}
/* Read input */
UartRxString((uint8_t *) dst, len);
esp_rom_uart_rx_string((uint8_t *) dst, len);
}
void unity_exec_time_start(void)

12
components/vfs/test/test_vfs_uart.c
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@ -19,11 +19,7 @@
#include <sys/termios.h>
#include <sys/errno.h>
#include "unity.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/uart.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/uart.h"
#endif
#include "esp_rom_uart.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
@ -35,11 +31,11 @@
static void fwrite_str_loopback(const char* str, size_t size)
{
uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
UART0.conf0.loopback = 1;
fwrite(str, 1, size, stdout);
fflush(stdout);
uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
vTaskDelay(2 / portTICK_PERIOD_MS);
UART0.conf0.loopback = 0;
}
@ -52,7 +48,7 @@ static void flush_stdin_stdout(void)
;
}
fflush(stdout);
uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
}
TEST_CASE("can read from stdin", "[vfs]")

8
components/vfs/vfs_uart.c
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@ -26,11 +26,7 @@
#include "driver/uart.h"
#include "sdkconfig.h"
#include "driver/uart_select.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/uart.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/uart.h"
#endif
#include "esp_rom_uart.h"
// TODO: make the number of UARTs chip dependent
#define UART_NUM SOC_UART_NUM
@ -352,7 +348,7 @@ static int uart_fsync(int fd)
{
assert(fd >= 0 && fd < 3);
_lock_acquire_recursive(&s_ctx[fd]->write_lock);
uart_tx_wait_idle((uint8_t) fd);
esp_rom_uart_tx_wait_idle((uint8_t) fd);
_lock_release_recursive(&s_ctx[fd]->write_lock);
return 0;
}

2
tools/unit-test-app/components/test_utils/test_utils.c
Wyświetl plik

@ -73,7 +73,7 @@ static void wait_user_control(char* parameter_buf, uint8_t buf_len)
buffer = sign;
buffer_len = sizeof(sign) - 1;
}
// workaround that unity_gets (UartRxString) will not set '\0' correctly
// workaround that unity_gets (esp_rom_uart_rx_string) will not set '\0' correctly
bzero(buffer, buffer_len);
unity_gets(buffer, buffer_len);