Merge branch 'feature/fpga_warnings' into 'master'

esp_system: Add boot warning when running on FPGA, fix dropped log issue

Closes IDF-2687

See merge request espressif/esp-idf!12209

components/esp_common/src/fpga_overrides.c

@@ -13,17 +13,25 @@
 // limitations under the License.
 #include "sdkconfig.h"
 #include "soc/soc.h"
-#include "soc/system_reg.h"
 #include "soc/rtc.h"
 #include "soc/rtc_cntl_reg.h"
+#include "esp_log.h"
 #include "esp_rom_sys.h"
 #include "esp_rom_uart.h"
 #include "esp_attr.h"
 
+static const char *TAG = "fpga";
+
 extern void ets_update_cpu_frequency(uint32_t ticks_per_us);
 
+static void s_warn(void)
+{
+    ESP_EARLY_LOGW(TAG, "Project configuration is for internal FPGA use, not all functions will work");
+}
+
 void bootloader_clock_configure(void)
 {
+    s_warn();
     esp_rom_uart_tx_wait_idle(0);
 
     uint32_t xtal_freq_mhz = 40;
@@ -48,7 +56,7 @@ void IRAM_ATTR bootloader_fill_random(void *buffer, size_t length)
 
 void esp_clk_init(void)
 {
-
+    s_warn();
 }
 
 void esp_perip_clk_init(void)

components/esp_system/port/cpu_start.c

@@ -456,6 +456,7 @@ void IRAM_ATTR call_start_cpu0(void)
 #if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
     clock_hz = UART_CLK_FREQ_ROM; // From esp32-s3 on, UART clock source is selected to XTAL in ROM
 #endif
+    esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
     esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_UART_NUM, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
 #endif
 

tools/cmake/targets.cmake

@@ -32,7 +32,7 @@ macro(__target_init)
     set(env_idf_env_fpga $ENV{IDF_ENV_FPGA})
     if(${env_idf_env_fpga})
         idf_build_set_property(__IDF_ENV_FPGA "y")
-        message(STATUS "IDF_ENV_FPGA is set, building for FPGA environment")
+        message(NOTICE "IDF_ENV_FPGA is set, building for FPGA environment")
     endif()
 endmacro()