From 8dbb14b469c8b1bf01d3230a072fc56ff018a52f Mon Sep 17 00:00:00 2001
From: Angus Gratton <angus@espressif.com>
Date: Mon, 1 Feb 2021 14:22:50 +1100
Subject: [PATCH 1/2] system: Log a warning when booting bootloader or app
 configured for FPGA use

Such a firmware may appear to work on normal chip, but not everything will function as expected.
---
 components/esp_common/src/fpga_overrides.c | 12 ++++++++++--
 tools/cmake/targets.cmake                  |  2 +-
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/components/esp_common/src/fpga_overrides.c b/components/esp_common/src/fpga_overrides.c
index 57fc5bd5dc..b309bef623 100644
--- a/components/esp_common/src/fpga_overrides.c
+++ b/components/esp_common/src/fpga_overrides.c
@@ -13,17 +13,25 @@
 // limitations under the License.
 #include "sdkconfig.h"
 #include "soc/soc.h"
-#include "soc/system_reg.h"
 #include "soc/rtc.h"
 #include "soc/rtc_cntl_reg.h"
+#include "esp_log.h"
 #include "esp_rom_sys.h"
 #include "esp_rom_uart.h"
 #include "esp_attr.h"
 
+static const char *TAG = "fpga";
+
 extern void ets_update_cpu_frequency(uint32_t ticks_per_us);
 
+static void s_warn(void)
+{
+    ESP_EARLY_LOGW(TAG, "Project configuration is for internal FPGA use, not all functions will work");
+}
+
 void bootloader_clock_configure(void)
 {
+    s_warn();
     esp_rom_uart_tx_wait_idle(0);
 
     uint32_t xtal_freq_mhz = 40;
@@ -48,7 +56,7 @@ void IRAM_ATTR bootloader_fill_random(void *buffer, size_t length)
 
 void esp_clk_init(void)
 {
-
+    s_warn();
 }
 
 void esp_perip_clk_init(void)
diff --git a/tools/cmake/targets.cmake b/tools/cmake/targets.cmake
index dae1ea4ce6..22df06abcd 100644
--- a/tools/cmake/targets.cmake
+++ b/tools/cmake/targets.cmake
@@ -32,7 +32,7 @@ macro(__target_init)
     set(env_idf_env_fpga $ENV{IDF_ENV_FPGA})
     if(${env_idf_env_fpga})
         idf_build_set_property(__IDF_ENV_FPGA "y")
-        message(STATUS "IDF_ENV_FPGA is set, building for FPGA environment")
+        message(NOTICE "IDF_ENV_FPGA is set, building for FPGA environment")
     endif()
 endmacro()
 

From dfda84c2ab229d8c6cc5e78f42aa6e1a14f11f76 Mon Sep 17 00:00:00 2001
From: Angus Gratton <angus@espressif.com>
Date: Mon, 1 Feb 2021 14:23:53 +1100
Subject: [PATCH 2/2] esp_system: Fix some ESP_EARLY_LOG lines not being output
 fully

At least on ESP32, calling esp_rom_uart_set_clock_baudrate() causes the
contents of the UART FIFO to be discarded.
---
 components/esp_system/port/cpu_start.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c
index 9461f673f6..beca4ae893 100644
--- a/components/esp_system/port/cpu_start.c
+++ b/components/esp_system/port/cpu_start.c
@@ -456,6 +456,7 @@ void IRAM_ATTR call_start_cpu0(void)
 #if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
     clock_hz = UART_CLK_FREQ_ROM; // From esp32-s3 on, UART clock source is selected to XTAL in ROM
 #endif
+    esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
     esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_UART_NUM, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
 #endif