kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'feature/fpga_warnings' into 'master'
esp_system: Add boot warning when running on FPGA, fix dropped log issue Closes IDF-2687 See merge request espressif/esp-idf!12209pull/7261/head
commit
2b5cbcf852
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@ -13,17 +13,25 @@
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// limitations under the License.
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#include "sdkconfig.h"
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#include "soc/soc.h"
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#include "soc/system_reg.h"
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "esp_log.h"
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#include "esp_rom_sys.h"
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#include "esp_rom_uart.h"
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#include "esp_attr.h"
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static const char *TAG = "fpga";
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extern void ets_update_cpu_frequency(uint32_t ticks_per_us);
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static void s_warn(void)
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{
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ESP_EARLY_LOGW(TAG, "Project configuration is for internal FPGA use, not all functions will work");
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}
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void bootloader_clock_configure(void)
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{
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s_warn();
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esp_rom_uart_tx_wait_idle(0);
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uint32_t xtal_freq_mhz = 40;
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@ -48,7 +56,7 @@ void IRAM_ATTR bootloader_fill_random(void *buffer, size_t length)
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void esp_clk_init(void)
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{
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s_warn();
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}
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void esp_perip_clk_init(void)
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@ -456,6 +456,7 @@ void IRAM_ATTR call_start_cpu0(void)
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#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
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clock_hz = UART_CLK_FREQ_ROM; // From esp32-s3 on, UART clock source is selected to XTAL in ROM
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#endif
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esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
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esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_UART_NUM, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
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#endif
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@ -32,7 +32,7 @@ macro(__target_init)
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set(env_idf_env_fpga $ENV{IDF_ENV_FPGA})
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if(${env_idf_env_fpga})
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idf_build_set_property(__IDF_ENV_FPGA "y")
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message(STATUS "IDF_ENV_FPGA is set, building for FPGA environment")
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message(NOTICE "IDF_ENV_FPGA is set, building for FPGA environment")
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endif()
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endmacro()
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