kopia lustrzana https://github.com/espressif/esp-idf
intr_allocator: add abstractions for priority, type and edge-ack interrupt controller functions
rodzic
810be86f21
commit
09bc1580be
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@ -551,14 +551,11 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
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interrupt_controller_hal_set_int_handler(intr, handler, arg);
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#endif
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}
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#ifdef __XTENSA__ // TODO ESP32-C3 IDF-2126
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if (flags&ESP_INTR_FLAG_EDGE) xthal_set_intclear(1 << intr);
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#else
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if (flags & ESP_INTR_FLAG_EDGE) {
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ESP_INTR_DISABLE(intr);
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esprv_intc_int_set_priority(intr, 0);
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}
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#endif
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interrupt_controller_hal_edge_int_acknowledge(intr);
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}
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vd->source=source;
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}
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if (flags&ESP_INTR_FLAG_IRAM) {
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@ -585,12 +582,12 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
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esp_intr_disable(ret);
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}
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#if CONFIG_IDF_TARGET_ESP32C3
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// TODO ESP32-C3 IDF-2126, these need to be set or the new interrupt won't fire, but are currently hard-coded
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// for priority and level...
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esprv_intc_int_set_priority(intr, 1);
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esprv_intc_int_set_type(BIT(intr), INTR_TYPE_LEVEL);
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#endif
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//Set the level and type at controller level if needed:
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interrupt_controller_hal_set_int_level(intr,
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interrupt_controller_hal_desc_level(intr));
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interrupt_controller_hal_set_int_type(intr,
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interrupt_controller_hal_desc_type(intr));
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portEXIT_CRITICAL(&spinlock);
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@ -100,6 +100,46 @@ static inline void intr_cntrl_ll_enable_int_mask(uint32_t newmask)
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xt_int_enable_mask(newmask);
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}
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/**
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* @brief Acknowledge an edge-trigger interrupt by clearing its pending flag
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*
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* @param intr interrupt number ranged from 0 to 31
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*/
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static inline void intr_cntrl_ll_edge_int_acknowledge (int intr)
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{
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xthal_set_intclear(1 << intr);
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}
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/**
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* @brief Sets the interrupt level int the interrupt controller.
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*
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* @param interrupt_number Interrupt number 0 to 31
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* @param level priority between 1 (lowest) to 7 (highest)
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*/
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static inline void intr_cntrl_ll_set_int_level(int intr, int level)
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{
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/* Not needed currently for xtensa platforms since the level is already set
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* in interrupt table
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*/
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(void)intr;
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(void)level;
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}
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/**
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* @brief Set the type of an interrupt in the controller.
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*
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* @param interrupt_number Interrupt number 0 to 31
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* @param type interrupt type as edge or level triggered
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*/
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static inline void intr_cntrl_ll_set_int_type(int intr, int_type_t type)
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{
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/* Not needed currently for xtensa platforms since the type is already set
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* in interrupt table
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*/
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(void)intr;
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(void)type;
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}
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#ifdef __cplusplus
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}
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#endif
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@ -116,27 +116,40 @@ static inline void intr_cntrl_ll_enable_int_mask(uint32_t newmask)
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}
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/**
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* @brief Set the interrupt type given an interrupt number.
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*
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* @param interrupt_number number of the interrupt
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* @param type new type for this interrupt
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* @brief Acknowledge an edge-trigger interrupt by clearing its pending flag
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*
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* @param intr interrupt number ranged from 0 to 31
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*/
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static inline void intr_cntrl_ll_set_type(int interrupt_number, int_type_t type)
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static inline void intr_cntrl_ll_edge_int_acknowledge (int intr)
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{
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esprv_intc_int_set_type(BIT(interrupt_number), type);
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intr_cntrl_ll_disable_interrupts(1 << intr);
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esprv_intc_int_set_priority(intr, 0);
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}
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/**
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* @brief Set the interrupt level (priority) given an interrupt number.
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*
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* @param interrupt_number number of the interrupt
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* @param level new level for this interrupt
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* @brief Sets the interrupt level int the interrupt controller.
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*
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* @param interrupt_number Interrupt number 0 to 31
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* @param level priority between 1 (lowest) to 7 (highest)
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*/
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static inline void intr_cntrl_ll_set_level(int interrupt_number, int level)
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static inline void intr_cntrl_ll_set_int_level(int intr, int level)
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{
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esprv_intc_int_set_priority(interrupt_number, level);
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esprv_intc_int_set_priority(intr, level);
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}
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/**
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* @brief Set the type of an interrupt in the controller.
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*
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* @param interrupt_number Interrupt number 0 to 31
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* @param type interrupt type as edge or level triggered
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*/
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static inline void intr_cntrl_ll_set_int_type(int intr, int_type_t type)
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{
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/* Not needed currently for xtensa platforms since the type is already set
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* in interrupt table
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*/
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esprv_intc_int_set_type(BIT(intr), type);
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}
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#ifdef __cplusplus
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}
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@ -100,6 +100,47 @@ static inline void intr_cntrl_ll_enable_int_mask(uint32_t newmask)
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xt_int_enable_mask(newmask);
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}
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/**
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* @brief Acknowledge an edge-trigger interrupt by clearing its pending flag
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*
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* @param intr interrupt number ranged from 0 to 31
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*/
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static inline void intr_cntrl_ll_edge_int_acknowledge (int intr)
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{
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xthal_set_intclear(1 << intr);
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}
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/**
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* @brief Sets the interrupt level int the interrupt controller.
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*
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* @param interrupt_number Interrupt number 0 to 31
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* @param level priority between 1 (lowest) to 7 (highest)
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*/
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static inline void intr_cntrl_ll_set_int_level(int intr, int level)
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{
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/* Not needed currently for xtensa platforms since the level is already set
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* in interrupt table
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*/
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(void)intr;
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(void)level;
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}
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/**
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* @brief Set the type of an interrupt in the controller.
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*
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* @param interrupt_number Interrupt number 0 to 31
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* @param type interrupt type as edge or level triggered
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*/
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static inline void intr_cntrl_ll_set_int_type(int intr, int_type_t type)
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{
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/* Not needed currently for xtensa platforms since the type is already set
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* in interrupt table
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*/
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(void)intr;
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(void)type;
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}
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#ifdef __cplusplus
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}
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#endif
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@ -100,6 +100,46 @@ static inline void intr_cntrl_ll_enable_int_mask(uint32_t newmask)
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xt_int_enable_mask(newmask);
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}
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/**
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* @brief Acknowledge an edge-trigger interrupt by clearing its pending flag
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*
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* @param intr interrupt number ranged from 0 to 31
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*/
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static inline void intr_cntrl_ll_edge_int_acknowledge (int intr)
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{
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xthal_set_intclear(1 << intr);
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}
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/**
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* @brief Sets the interrupt level int the interrupt controller.
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*
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* @param interrupt_number Interrupt number 0 to 31
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* @param level priority between 1 (lowest) to 7 (highest)
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*/
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static inline void intr_cntrl_ll_set_int_level(int intr, int level)
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{
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/* Not needed currently for xtensa platforms since the level is already set
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* in interrupt table
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*/
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(void)intr;
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(void)level;
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}
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/**
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* @brief Set the type of an interrupt in the controller.
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*
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* @param interrupt_number Interrupt number 0 to 31
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* @param type interrupt type as edge or level triggered
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*/
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static inline void intr_cntrl_ll_set_int_type(int intr, int_type_t type)
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{
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/* Not needed currently for xtensa platforms since the type is already set
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* in interrupt table
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*/
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(void)intr;
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(void)type;
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}
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#ifdef __cplusplus
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}
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#endif
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@ -84,6 +84,17 @@ static inline int_type_t interrupt_controller_hal_get_type(int interrupt_number)
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return interrupt_controller_hal_desc_type(interrupt_number);
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}
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/**
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* @brief Set the type of an interrupt in the controller.
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*
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* @param interrupt_number Interrupt number 0 to 31
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* @param type interrupt type as edge or level triggered
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*/
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static inline void interrupt_controller_hal_set_int_type(int intr, int_type_t type)
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{
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intr_cntrl_ll_set_int_type(intr, type);
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}
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/**
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* @brief Gets the interrupt level given an interrupt number.
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*
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@ -95,6 +106,17 @@ static inline int interrupt_controller_hal_get_level(int interrupt_number)
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return interrupt_controller_hal_desc_level(interrupt_number);
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}
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/**
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* @brief Sets the interrupt level int the interrupt controller.
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*
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* @param interrupt_number Interrupt number 0 to 31
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* @param level priority between 1 (lowest) to 7 (highest)
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*/
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static inline void interrupt_controller_hal_set_int_level(int intr, int level)
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{
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intr_cntrl_ll_set_int_level(intr, level);
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}
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/**
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* @brief Gets the cpu flags given the interrupt number and target cpu.
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*
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@ -184,6 +206,16 @@ static inline void interrupt_controller_hal_enable_int_mask(uint32_t newmask)
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intr_cntrl_ll_enable_int_mask(newmask);
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}
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/**
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* @brief Acknowledge an edge-trigger interrupt by clearing its pending flag
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*
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* @param intr interrupt number ranged from 0 to 31
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*/
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static inline void interrupt_controller_hal_edge_int_acknowledge(int intr)
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{
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intr_cntrl_ll_edge_int_acknowledge(intr);
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}
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#ifdef __cplusplus
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}
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#endif
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