2021-05-24 00:09:38 +00:00
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/*
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* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2019-09-09 12:56:46 +00:00
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#include <esp_types.h>
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#include <stdlib.h>
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#include <ctype.h>
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#include "freertos/FreeRTOS.h"
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#include "freertos/semphr.h"
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#include "freertos/timers.h"
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#include "esp_log.h"
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2020-02-25 14:19:48 +00:00
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#include "esp_pm.h"
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2019-09-09 12:56:46 +00:00
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#include "soc/rtc.h"
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2020-04-02 03:20:38 +00:00
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#include "driver/rtc_io.h"
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2019-09-09 12:56:46 +00:00
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#include "sys/lock.h"
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#include "driver/gpio.h"
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2020-02-25 14:19:48 +00:00
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#include "driver/adc.h"
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#include "adc1_private.h"
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2019-09-09 12:56:46 +00:00
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#include "hal/adc_types.h"
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#include "hal/adc_hal.h"
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2021-09-07 03:21:35 +00:00
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#include "hal/adc_hal_conf.h"
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2020-11-26 08:56:13 +00:00
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2021-04-06 13:56:27 +00:00
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#if SOC_DAC_SUPPORTED
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2021-01-31 17:12:28 +00:00
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#include "driver/dac.h"
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2020-04-15 12:51:27 +00:00
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#include "hal/dac_hal.h"
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2021-01-31 17:12:28 +00:00
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#endif
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2021-09-07 03:21:35 +00:00
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#if CONFIG_IDF_TARGET_ESP32S3
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#include "esp_efuse_rtc_calib.h"
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#endif
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2019-09-09 12:56:46 +00:00
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#define ADC_CHECK_RET(fun_ret) ({ \
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if (fun_ret != ESP_OK) { \
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ESP_LOGE(ADC_TAG,"%s:%d\n",__FUNCTION__,__LINE__); \
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return ESP_FAIL; \
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} \
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})
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static const char *ADC_TAG = "ADC";
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#define ADC_CHECK(a, str, ret_val) ({ \
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if (!(a)) { \
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2020-07-29 12:46:37 +00:00
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ESP_LOGE(ADC_TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \
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2019-09-09 12:56:46 +00:00
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return (ret_val); \
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} \
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})
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#define ADC_GET_IO_NUM(periph, channel) (adc_channel_io_map[periph][channel])
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#define ADC_CHANNEL_CHECK(periph, channel) ADC_CHECK(channel < SOC_ADC_CHANNEL_NUM(periph), "ADC"#periph" channel error", ESP_ERR_INVALID_ARG)
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2021-01-31 17:12:28 +00:00
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//////////////////////// Locks ///////////////////////////////////////////
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2019-09-09 12:56:46 +00:00
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extern portMUX_TYPE rtc_spinlock; //TODO: Will be placed in the appropriate position after the rtc module is finished.
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2021-01-31 17:12:28 +00:00
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#define RTC_ENTER_CRITICAL() portENTER_CRITICAL(&rtc_spinlock)
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#define RTC_EXIT_CRITICAL() portEXIT_CRITICAL(&rtc_spinlock)
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#define DIGI_ENTER_CRITICAL()
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#define DIGI_EXIT_CRITICAL()
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#define ADC_POWER_ENTER() RTC_ENTER_CRITICAL()
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#define ADC_POWER_EXIT() RTC_EXIT_CRITICAL()
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#define DIGI_CONTROLLER_ENTER() DIGI_ENTER_CRITICAL()
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#define DIGI_CONTROLLER_EXIT() DIGI_EXIT_CRITICAL()
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#define SARADC1_ENTER() RTC_ENTER_CRITICAL()
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#define SARADC1_EXIT() RTC_EXIT_CRITICAL()
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#define SARADC2_ENTER() RTC_ENTER_CRITICAL()
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#define SARADC2_EXIT() RTC_EXIT_CRITICAL()
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//n stands for ADC unit: 1 for ADC1 and 2 for ADC2. Currently both unit touches the same registers
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#define VREF_ENTER(n) RTC_ENTER_CRITICAL()
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#define VREF_EXIT(n) RTC_EXIT_CRITICAL()
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#define FSM_ENTER() RTC_ENTER_CRITICAL()
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#define FSM_EXIT() RTC_EXIT_CRITICAL()
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2021-12-22 03:17:42 +00:00
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//TODO: IDF-3610
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2021-01-31 17:12:28 +00:00
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#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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//prevent ADC1 being used by I2S dma and other tasks at the same time.
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static _lock_t adc1_dma_lock;
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#define SARADC1_ACQUIRE() _lock_acquire( &adc1_dma_lock )
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#define SARADC1_RELEASE() _lock_release( &adc1_dma_lock )
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#endif
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2019-09-09 12:56:46 +00:00
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2021-12-22 03:17:42 +00:00
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2019-09-09 12:56:46 +00:00
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/*
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In ADC2, there're two locks used for different cases:
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2020-02-25 14:19:48 +00:00
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1. lock shared with app and Wi-Fi:
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ESP32:
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When Wi-Fi using the ADC2, we assume it will never stop, so app checks the lock and returns immediately if failed.
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ESP32S2:
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The controller's control over the ADC is determined by the arbiter. There is no need to control by lock.
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2019-09-09 12:56:46 +00:00
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2. lock shared between tasks:
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when several tasks sharing the ADC2, we want to guarantee
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all the requests will be handled.
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Since conversions are short (about 31us), app returns the lock very soon,
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we use a spinlock to stand there waiting to do conversions one by one.
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adc2_spinlock should be acquired first, then adc2_wifi_lock or rtc_spinlock.
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*/
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2020-12-03 05:58:24 +00:00
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2020-02-25 14:19:48 +00:00
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#ifdef CONFIG_IDF_TARGET_ESP32
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2019-09-09 12:56:46 +00:00
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//prevent ADC2 being used by wifi and other tasks at the same time.
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static _lock_t adc2_wifi_lock;
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2020-02-25 14:19:48 +00:00
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/** For ESP32S2 the ADC2 The right to use ADC2 is controlled by the arbiter, and there is no need to set a lock. */
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2021-01-31 17:12:28 +00:00
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#define SARADC2_ACQUIRE() _lock_acquire( &adc2_wifi_lock )
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#define SARADC2_RELEASE() _lock_release( &adc2_wifi_lock )
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#define SARADC2_TRY_ACQUIRE() _lock_try_acquire( &adc2_wifi_lock )
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#define SARADC2_LOCK_CHECK() ((uint32_t *)adc2_wifi_lock != NULL)
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2020-02-25 14:19:48 +00:00
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2021-01-31 17:12:28 +00:00
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#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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#define SARADC2_ACQUIRE()
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#define SARADC2_RELEASE()
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#define SARADC2_TRY_ACQUIRE() (0) //WIFI controller and rtc controller have independent parameter configuration.
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#define SARADC2_LOCK_CHECK() (true)
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2020-02-25 14:19:48 +00:00
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2021-01-31 17:12:28 +00:00
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#endif // CONFIG_IDF_TARGET_*
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2020-02-25 14:19:48 +00:00
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2021-06-08 09:38:46 +00:00
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#if CONFIG_IDF_TARGET_ESP32S2
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2020-02-25 14:19:48 +00:00
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#ifdef CONFIG_PM_ENABLE
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static esp_pm_lock_handle_t s_adc2_arbiter_lock;
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#endif //CONFIG_PM_ENABLE
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2020-11-26 08:56:13 +00:00
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#endif // !CONFIG_IDF_TARGET_ESP32
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2020-02-25 14:19:48 +00:00
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2021-09-07 03:21:35 +00:00
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2019-09-09 12:56:46 +00:00
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/*---------------------------------------------------------------
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ADC Common
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---------------------------------------------------------------*/
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2021-01-31 17:12:28 +00:00
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// ADC Power
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// This gets incremented when adc_power_acquire() is called, and decremented when
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// adc_power_release() is called. ADC is powered down when the value reaches zero.
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// Should be modified within critical section (ADC_ENTER/EXIT_CRITICAL).
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static int s_adc_power_on_cnt;
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static void adc_power_on_internal(void)
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{
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/* Set the power always on to increase precision. */
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adc_hal_set_power_manage(ADC_POWER_SW_ON);
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}
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2020-12-03 05:58:24 +00:00
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void adc_power_acquire(void)
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2020-12-03 05:58:24 +00:00
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{
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2021-01-31 17:12:28 +00:00
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ADC_POWER_ENTER();
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2020-12-03 05:58:24 +00:00
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s_adc_power_on_cnt++;
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if (s_adc_power_on_cnt == 1) {
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adc_power_on_internal();
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}
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2021-01-31 17:12:28 +00:00
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ADC_POWER_EXIT();
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2020-12-03 05:58:24 +00:00
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}
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2021-01-31 17:12:28 +00:00
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void adc_power_on(void)
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{
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ADC_POWER_ENTER();
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adc_power_on_internal();
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ADC_POWER_EXIT();
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}
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static void adc_power_off_internal(void)
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{
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2021-03-26 04:18:31 +00:00
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#if CONFIG_IDF_TARGET_ESP32
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2021-01-31 17:12:28 +00:00
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adc_hal_set_power_manage(ADC_POWER_SW_OFF);
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2021-03-26 04:18:31 +00:00
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#else
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adc_hal_set_power_manage(ADC_POWER_BY_FSM);
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#endif
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2021-01-31 17:12:28 +00:00
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}
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2020-12-03 05:58:24 +00:00
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void adc_power_release(void)
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{
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2021-01-31 17:12:28 +00:00
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ADC_POWER_ENTER();
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2020-12-03 05:58:24 +00:00
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s_adc_power_on_cnt--;
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/* Sanity check */
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if (s_adc_power_on_cnt < 0) {
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2021-01-31 17:12:28 +00:00
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ADC_POWER_EXIT();
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2020-12-03 05:58:24 +00:00
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ESP_LOGE(ADC_TAG, "%s called, but s_adc_power_on_cnt == 0", __func__);
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abort();
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} else if (s_adc_power_on_cnt == 0) {
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adc_power_off_internal();
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}
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2021-01-31 17:12:28 +00:00
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ADC_POWER_EXIT();
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2019-09-09 12:56:46 +00:00
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}
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2021-01-31 17:12:28 +00:00
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void adc_power_off(void)
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2019-09-09 12:56:46 +00:00
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{
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2021-01-31 17:12:28 +00:00
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ADC_POWER_ENTER();
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adc_power_off_internal();
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ADC_POWER_EXIT();
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2019-09-09 12:56:46 +00:00
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}
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2021-03-25 11:04:38 +00:00
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esp_err_t adc1_pad_get_io_num(adc1_channel_t channel, gpio_num_t *gpio_num)
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{
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ADC_CHANNEL_CHECK(ADC_NUM_1, channel);
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int io = ADC_GET_IO_NUM(ADC_NUM_1, channel);
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if (io < 0) {
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return ESP_ERR_INVALID_ARG;
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} else {
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*gpio_num = (gpio_num_t)io;
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}
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return ESP_OK;
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}
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esp_err_t adc2_pad_get_io_num(adc2_channel_t channel, gpio_num_t *gpio_num)
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{
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ADC_CHANNEL_CHECK(ADC_NUM_2, channel);
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int io = ADC_GET_IO_NUM(ADC_NUM_2, channel);
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if (io < 0) {
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return ESP_ERR_INVALID_ARG;
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} else {
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*gpio_num = (gpio_num_t)io;
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}
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return ESP_OK;
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}
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2020-12-03 05:58:24 +00:00
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2021-09-07 03:21:35 +00:00
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//------------------------------------------------------------RTC Single Read----------------------------------------------//
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#if SOC_ADC_RTC_CTRL_SUPPORTED
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#if SOC_ADC_CALIBRATION_V1_SUPPORTED
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static uint32_t get_calibration_offset(adc_ll_num_t adc_n, adc_channel_t chan)
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{
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2021-12-22 03:17:42 +00:00
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adc_atten_t atten = adc_ll_get_atten(adc_n, chan);
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extern uint32_t adc_get_calibration_offset(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten);
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2021-09-07 03:21:35 +00:00
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return adc_get_calibration_offset(adc_n, chan, atten);
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}
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2021-12-22 03:17:42 +00:00
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#endif //SOC_ADC_CALIBRATION_V1_SUPPORTED
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2021-09-07 03:21:35 +00:00
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2019-09-09 12:56:46 +00:00
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esp_err_t adc_set_clk_div(uint8_t clk_div)
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{
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2021-01-31 17:12:28 +00:00
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DIGI_CONTROLLER_ENTER();
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2021-12-22 03:17:42 +00:00
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adc_ll_digi_set_clk_div(clk_div);
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2021-01-31 17:12:28 +00:00
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DIGI_CONTROLLER_EXIT();
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2019-09-09 12:56:46 +00:00
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return ESP_OK;
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}
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2020-04-15 12:51:27 +00:00
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static void adc_rtc_chan_init(adc_unit_t adc_unit)
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{
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if (adc_unit & ADC_UNIT_1) {
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/* Workaround: Disable the synchronization operation function of ADC1 and DAC.
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If enabled(default), ADC RTC controller sampling will cause the DAC channel output voltage. */
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2021-04-06 13:56:27 +00:00
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#if SOC_DAC_SUPPORTED
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2020-04-15 12:51:27 +00:00
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dac_hal_rtc_sync_by_adc(false);
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2021-04-06 13:56:27 +00:00
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#endif
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2020-04-15 12:51:27 +00:00
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adc_hal_rtc_output_invert(ADC_NUM_1, SOC_ADC1_DATA_INVERT_DEFAULT);
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2021-12-22 03:17:42 +00:00
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adc_ll_set_sar_clk_div(ADC_NUM_1, SOC_ADC_SAR_CLK_DIV_DEFAULT(ADC_NUM_1));
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2020-04-15 12:51:27 +00:00
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#ifdef CONFIG_IDF_TARGET_ESP32
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2021-12-22 03:17:42 +00:00
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adc_ll_hall_disable(); //Disable other peripherals.
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adc_ll_amp_disable(); //Currently the LNA is not open, close it by default.
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2020-04-15 12:51:27 +00:00
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#endif
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}
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if (adc_unit & ADC_UNIT_2) {
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adc_hal_pwdet_set_cct(SOC_ADC_PWDET_CCT_DEFAULT);
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adc_hal_rtc_output_invert(ADC_NUM_2, SOC_ADC2_DATA_INVERT_DEFAULT);
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2021-12-22 03:17:42 +00:00
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adc_ll_set_sar_clk_div(ADC_NUM_2, SOC_ADC_SAR_CLK_DIV_DEFAULT(ADC_NUM_2));
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2020-04-15 12:51:27 +00:00
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}
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}
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2021-12-22 03:17:42 +00:00
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/**
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* This function is NOT an API.
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* Now some to-be-deprecated APIs are using this function, so don't make it static for now.
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* Will make this static on v5.0
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*/
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esp_err_t adc_common_gpio_init(adc_unit_t adc_unit, adc_channel_t channel)
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2019-09-09 12:56:46 +00:00
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{
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gpio_num_t gpio_num = 0;
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2020-12-10 07:42:12 +00:00
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//If called with `ADC_UNIT_BOTH (ADC_UNIT_1 | ADC_UNIT_2)`, both if blocks will be run
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2019-09-09 12:56:46 +00:00
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if (adc_unit & ADC_UNIT_1) {
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ADC_CHANNEL_CHECK(ADC_NUM_1, channel);
|
|
|
|
gpio_num = ADC_GET_IO_NUM(ADC_NUM_1, channel);
|
2020-12-10 07:42:12 +00:00
|
|
|
ADC_CHECK_RET(rtc_gpio_init(gpio_num));
|
|
|
|
ADC_CHECK_RET(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED));
|
|
|
|
ADC_CHECK_RET(rtc_gpio_pulldown_dis(gpio_num));
|
|
|
|
ADC_CHECK_RET(rtc_gpio_pullup_dis(gpio_num));
|
2019-09-09 12:56:46 +00:00
|
|
|
}
|
|
|
|
if (adc_unit & ADC_UNIT_2) {
|
|
|
|
ADC_CHANNEL_CHECK(ADC_NUM_2, channel);
|
|
|
|
gpio_num = ADC_GET_IO_NUM(ADC_NUM_2, channel);
|
2020-12-10 07:42:12 +00:00
|
|
|
ADC_CHECK_RET(rtc_gpio_init(gpio_num));
|
|
|
|
ADC_CHECK_RET(rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED));
|
|
|
|
ADC_CHECK_RET(rtc_gpio_pulldown_dis(gpio_num));
|
|
|
|
ADC_CHECK_RET(rtc_gpio_pullup_dis(gpio_num));
|
2019-09-09 12:56:46 +00:00
|
|
|
}
|
2020-12-10 07:42:12 +00:00
|
|
|
|
2019-09-09 12:56:46 +00:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t adc_set_data_inv(adc_unit_t adc_unit, bool inv_en)
|
|
|
|
{
|
|
|
|
if (adc_unit & ADC_UNIT_1) {
|
2021-01-31 17:12:28 +00:00
|
|
|
SARADC1_ENTER();
|
2020-02-25 14:19:48 +00:00
|
|
|
adc_hal_rtc_output_invert(ADC_NUM_1, inv_en);
|
2021-01-31 17:12:28 +00:00
|
|
|
SARADC1_EXIT();
|
2019-09-09 12:56:46 +00:00
|
|
|
}
|
|
|
|
if (adc_unit & ADC_UNIT_2) {
|
2021-01-31 17:12:28 +00:00
|
|
|
SARADC2_ENTER();
|
|
|
|
adc_hal_rtc_output_invert(ADC_NUM_2, inv_en);
|
|
|
|
SARADC2_EXIT();
|
2019-09-09 12:56:46 +00:00
|
|
|
}
|
2020-02-25 14:19:48 +00:00
|
|
|
|
2019-09-09 12:56:46 +00:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2021-12-22 03:17:42 +00:00
|
|
|
esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t width_bit)
|
2019-09-09 12:56:46 +00:00
|
|
|
{
|
2021-06-08 09:38:46 +00:00
|
|
|
#if CONFIG_IDF_TARGET_ESP32
|
2021-12-22 03:17:42 +00:00
|
|
|
ADC_CHECK(width_bit < ADC_WIDTH_MAX, "WIDTH ERR: ESP32 support 9 ~ 12 bit width", ESP_ERR_INVALID_ARG);
|
2020-11-26 08:56:13 +00:00
|
|
|
#else
|
2021-12-22 03:17:42 +00:00
|
|
|
ADC_CHECK(width_bit == ADC_WIDTH_MAX - 1, "WIDTH ERR: see `adc_bits_width_t` for supported bit width", ESP_ERR_INVALID_ARG);
|
2020-02-25 14:19:48 +00:00
|
|
|
#endif
|
|
|
|
|
2019-09-09 12:56:46 +00:00
|
|
|
if (adc_unit & ADC_UNIT_1) {
|
2021-01-31 17:12:28 +00:00
|
|
|
SARADC1_ENTER();
|
2021-12-22 03:17:42 +00:00
|
|
|
adc_hal_rtc_set_output_format(ADC_NUM_1, width_bit);
|
2021-01-31 17:12:28 +00:00
|
|
|
SARADC1_EXIT();
|
2019-09-09 12:56:46 +00:00
|
|
|
}
|
|
|
|
if (adc_unit & ADC_UNIT_2) {
|
2021-01-31 17:12:28 +00:00
|
|
|
SARADC2_ENTER();
|
2021-12-22 03:17:42 +00:00
|
|
|
adc_hal_rtc_set_output_format(ADC_NUM_2, width_bit);
|
2021-01-31 17:12:28 +00:00
|
|
|
SARADC2_EXIT();
|
2019-09-09 12:56:46 +00:00
|
|
|
}
|
|
|
|
|
2020-02-25 14:19:48 +00:00
|
|
|
return ESP_OK;
|
2019-09-09 12:56:46 +00:00
|
|
|
}
|
|
|
|
|
2020-02-25 14:19:48 +00:00
|
|
|
/**
|
|
|
|
* @brief Reset RTC controller FSM.
|
|
|
|
*
|
|
|
|
* @return
|
|
|
|
* - ESP_OK Success
|
|
|
|
*/
|
2020-11-26 08:56:13 +00:00
|
|
|
#if !CONFIG_IDF_TARGET_ESP32
|
2020-02-25 14:19:48 +00:00
|
|
|
esp_err_t adc_rtc_reset(void)
|
2019-09-09 12:56:46 +00:00
|
|
|
{
|
2021-01-31 17:12:28 +00:00
|
|
|
FSM_ENTER();
|
2021-06-08 09:38:46 +00:00
|
|
|
adc_ll_rtc_reset();
|
2021-01-31 17:12:28 +00:00
|
|
|
FSM_EXIT();
|
2019-09-09 12:56:46 +00:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
2020-02-25 14:19:48 +00:00
|
|
|
#endif
|
|
|
|
|
2019-09-09 12:56:46 +00:00
|
|
|
/*-------------------------------------------------------------------------------------
|
|
|
|
* ADC1
|
|
|
|
*------------------------------------------------------------------------------------*/
|
|
|
|
esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten)
|
|
|
|
{
|
|
|
|
ADC_CHANNEL_CHECK(ADC_NUM_1, channel);
|
|
|
|
ADC_CHECK(atten < ADC_ATTEN_MAX, "ADC Atten Err", ESP_ERR_INVALID_ARG);
|
2020-02-25 14:19:48 +00:00
|
|
|
|
2021-12-22 03:17:42 +00:00
|
|
|
adc_common_gpio_init(ADC_UNIT_1, channel);
|
2021-01-31 17:12:28 +00:00
|
|
|
SARADC1_ENTER();
|
2020-04-15 12:51:27 +00:00
|
|
|
adc_rtc_chan_init(ADC_UNIT_1);
|
2019-09-09 12:56:46 +00:00
|
|
|
adc_hal_set_atten(ADC_NUM_1, channel, atten);
|
2021-01-31 17:12:28 +00:00
|
|
|
SARADC1_EXIT();
|
2020-02-25 14:19:48 +00:00
|
|
|
|
2021-09-07 03:21:35 +00:00
|
|
|
#if SOC_ADC_CALIBRATION_V1_SUPPORTED
|
2021-01-19 12:00:01 +00:00
|
|
|
adc_hal_calibration_init(ADC_NUM_1);
|
|
|
|
#endif
|
|
|
|
|
2019-09-09 12:56:46 +00:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t adc1_config_width(adc_bits_width_t width_bit)
|
|
|
|
{
|
2021-06-08 09:38:46 +00:00
|
|
|
#if CONFIG_IDF_TARGET_ESP32
|
2020-02-25 14:19:48 +00:00
|
|
|
ADC_CHECK(width_bit < ADC_WIDTH_MAX, "WIDTH ERR: ESP32 support 9 ~ 12 bit width", ESP_ERR_INVALID_ARG);
|
2021-06-08 09:38:46 +00:00
|
|
|
#else
|
|
|
|
ADC_CHECK(width_bit == ADC_WIDTH_MAX - 1, "WIDTH ERR: see `adc_bits_width_t` for supported bit width", ESP_ERR_INVALID_ARG);
|
2020-02-25 14:19:48 +00:00
|
|
|
#endif
|
|
|
|
|
2021-01-31 17:12:28 +00:00
|
|
|
SARADC1_ENTER();
|
2019-09-09 12:56:46 +00:00
|
|
|
adc_hal_rtc_set_output_format(ADC_NUM_1, width_bit);
|
2021-01-31 17:12:28 +00:00
|
|
|
SARADC1_EXIT();
|
2020-02-25 14:19:48 +00:00
|
|
|
|
2019-09-09 12:56:46 +00:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2020-02-25 14:19:48 +00:00
|
|
|
esp_err_t adc1_dma_mode_acquire(void)
|
2019-09-09 12:56:46 +00:00
|
|
|
{
|
|
|
|
/* Use locks to avoid digtal and RTC controller conflicts.
|
|
|
|
for adc1, block until acquire the lock. */
|
2021-01-31 17:12:28 +00:00
|
|
|
SARADC1_ACQUIRE();
|
2020-02-25 14:19:48 +00:00
|
|
|
ESP_LOGD( ADC_TAG, "dma mode takes adc1 lock." );
|
|
|
|
|
2021-01-31 17:12:28 +00:00
|
|
|
adc_power_acquire();
|
|
|
|
|
|
|
|
SARADC1_ENTER();
|
2019-09-09 12:56:46 +00:00
|
|
|
/* switch SARADC into DIG channel */
|
2021-12-22 03:17:42 +00:00
|
|
|
adc_ll_set_controller(ADC_NUM_1, ADC_LL_CTRL_DIG);
|
2021-01-31 17:12:28 +00:00
|
|
|
SARADC1_EXIT();
|
2020-02-25 14:19:48 +00:00
|
|
|
|
2019-09-09 12:56:46 +00:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2020-02-25 14:19:48 +00:00
|
|
|
esp_err_t adc1_rtc_mode_acquire(void)
|
2019-09-09 12:56:46 +00:00
|
|
|
{
|
|
|
|
/* Use locks to avoid digtal and RTC controller conflicts.
|
|
|
|
for adc1, block until acquire the lock. */
|
2021-01-31 17:12:28 +00:00
|
|
|
SARADC1_ACQUIRE();
|
|
|
|
adc_power_acquire();
|
2020-02-25 14:19:48 +00:00
|
|
|
|
2021-01-31 17:12:28 +00:00
|
|
|
SARADC1_ENTER();
|
2019-09-09 12:56:46 +00:00
|
|
|
/* switch SARADC into RTC channel. */
|
2021-12-22 03:17:42 +00:00
|
|
|
adc_ll_set_controller(ADC_NUM_1, ADC_LL_CTRL_RTC);
|
2021-01-31 17:12:28 +00:00
|
|
|
SARADC1_EXIT();
|
2020-02-25 14:19:48 +00:00
|
|
|
|
2019-09-09 12:56:46 +00:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t adc1_lock_release(void)
|
|
|
|
{
|
2020-02-25 14:19:48 +00:00
|
|
|
ADC_CHECK((uint32_t *)adc1_dma_lock != NULL, "adc1 lock release called before acquire", ESP_ERR_INVALID_STATE );
|
|
|
|
/* Use locks to avoid digtal and RTC controller conflicts. for adc1, block until acquire the lock. */
|
2021-01-31 17:12:28 +00:00
|
|
|
|
|
|
|
adc_power_release();
|
|
|
|
SARADC1_RELEASE();
|
2019-09-09 12:56:46 +00:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
int adc1_get_raw(adc1_channel_t channel)
|
|
|
|
{
|
2020-02-25 14:19:48 +00:00
|
|
|
int adc_value;
|
2019-09-09 12:56:46 +00:00
|
|
|
ADC_CHANNEL_CHECK(ADC_NUM_1, channel);
|
2020-02-25 14:19:48 +00:00
|
|
|
adc1_rtc_mode_acquire();
|
|
|
|
|
2021-09-07 03:21:35 +00:00
|
|
|
#if SOC_ADC_CALIBRATION_V1_SUPPORTED
|
2020-12-08 07:51:27 +00:00
|
|
|
// Get calibration value before going into critical section
|
|
|
|
uint32_t cal_val = get_calibration_offset(ADC_NUM_1, channel);
|
2021-01-31 17:12:28 +00:00
|
|
|
adc_hal_set_calibration_param(ADC_NUM_1, cal_val);
|
2021-09-07 03:21:35 +00:00
|
|
|
#endif //SOC_ADC_CALIBRATION_V1_SUPPORTED
|
2020-12-08 07:51:27 +00:00
|
|
|
|
2021-01-31 17:12:28 +00:00
|
|
|
SARADC1_ENTER();
|
2020-07-29 05:13:51 +00:00
|
|
|
#ifdef CONFIG_IDF_TARGET_ESP32
|
2021-12-22 03:17:42 +00:00
|
|
|
adc_ll_hall_disable(); //Disable other peripherals.
|
|
|
|
adc_ll_amp_disable(); //Currently the LNA is not open, close it by default.
|
2021-06-08 09:38:46 +00:00
|
|
|
#endif
|
2021-12-22 03:17:42 +00:00
|
|
|
adc_ll_set_controller(ADC_NUM_1, ADC_LL_CTRL_RTC); //Set controller
|
2020-02-25 14:19:48 +00:00
|
|
|
adc_hal_convert(ADC_NUM_1, channel, &adc_value); //Start conversion, For ADC1, the data always valid.
|
2020-11-26 08:56:13 +00:00
|
|
|
#if !CONFIG_IDF_TARGET_ESP32
|
2021-06-08 09:38:46 +00:00
|
|
|
adc_ll_rtc_reset(); //Reset FSM of rtc controller
|
2020-02-25 14:19:48 +00:00
|
|
|
#endif
|
2021-01-31 17:12:28 +00:00
|
|
|
SARADC1_EXIT();
|
2019-09-09 12:56:46 +00:00
|
|
|
|
|
|
|
adc1_lock_release();
|
|
|
|
return adc_value;
|
|
|
|
}
|
|
|
|
|
|
|
|
int adc1_get_voltage(adc1_channel_t channel) //Deprecated. Use adc1_get_raw() instead
|
|
|
|
{
|
|
|
|
return adc1_get_raw(channel);
|
|
|
|
}
|
|
|
|
|
2020-11-26 08:56:13 +00:00
|
|
|
#if SOC_ULP_SUPPORTED
|
2019-09-09 12:56:46 +00:00
|
|
|
void adc1_ulp_enable(void)
|
|
|
|
{
|
2020-12-03 05:58:24 +00:00
|
|
|
adc_power_acquire();
|
2019-09-09 12:56:46 +00:00
|
|
|
|
2021-01-31 17:12:28 +00:00
|
|
|
SARADC1_ENTER();
|
2021-12-22 03:17:42 +00:00
|
|
|
adc_ll_set_controller(ADC_NUM_1, ADC_LL_CTRL_ULP);
|
2019-09-09 12:56:46 +00:00
|
|
|
/* since most users do not need LNA and HALL with uLP, we disable them here
|
|
|
|
open them in the uLP if needed. */
|
2020-02-25 14:19:48 +00:00
|
|
|
#ifdef CONFIG_IDF_TARGET_ESP32
|
2019-09-09 12:56:46 +00:00
|
|
|
/* disable other peripherals. */
|
2021-12-22 03:17:42 +00:00
|
|
|
adc_ll_hall_disable();
|
|
|
|
adc_ll_amp_disable();
|
2020-02-25 14:19:48 +00:00
|
|
|
#endif
|
2021-01-31 17:12:28 +00:00
|
|
|
SARADC1_EXIT();
|
2019-09-09 12:56:46 +00:00
|
|
|
}
|
2020-11-26 08:56:13 +00:00
|
|
|
#endif
|
2019-09-09 12:56:46 +00:00
|
|
|
|
|
|
|
/*---------------------------------------------------------------
|
|
|
|
ADC2
|
|
|
|
---------------------------------------------------------------*/
|
2020-02-25 14:19:48 +00:00
|
|
|
/** For ESP32S2 the ADC2 The right to use ADC2 is controlled by the arbiter, and there is no need to set a lock.*/
|
2019-09-09 12:56:46 +00:00
|
|
|
esp_err_t adc2_wifi_acquire(void)
|
|
|
|
{
|
|
|
|
/* Wi-Fi module will use adc2. Use locks to avoid conflicts. */
|
2021-01-31 17:12:28 +00:00
|
|
|
SARADC2_ACQUIRE();
|
2019-09-09 12:56:46 +00:00
|
|
|
ESP_LOGD( ADC_TAG, "Wi-Fi takes adc2 lock." );
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t adc2_wifi_release(void)
|
|
|
|
{
|
2021-01-31 17:12:28 +00:00
|
|
|
ADC_CHECK(SARADC2_LOCK_CHECK(), "wifi release called before acquire", ESP_ERR_INVALID_STATE );
|
|
|
|
SARADC2_RELEASE();
|
2019-09-09 12:56:46 +00:00
|
|
|
ESP_LOGD( ADC_TAG, "Wi-Fi returns adc2 lock." );
|
2020-02-25 14:19:48 +00:00
|
|
|
|
2019-09-09 12:56:46 +00:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten)
|
|
|
|
{
|
|
|
|
ADC_CHANNEL_CHECK(ADC_NUM_2, channel);
|
|
|
|
ADC_CHECK(atten <= ADC_ATTEN_11db, "ADC2 Atten Err", ESP_ERR_INVALID_ARG);
|
|
|
|
|
2021-12-22 03:17:42 +00:00
|
|
|
adc_common_gpio_init(ADC_UNIT_2, channel);
|
2021-01-31 17:12:28 +00:00
|
|
|
|
|
|
|
if ( SARADC2_TRY_ACQUIRE() == -1 ) {
|
2019-09-09 12:56:46 +00:00
|
|
|
//try the lock, return if failed (wifi using).
|
|
|
|
return ESP_ERR_TIMEOUT;
|
|
|
|
}
|
2021-01-31 17:12:28 +00:00
|
|
|
|
|
|
|
//avoid collision with other tasks
|
|
|
|
SARADC2_ENTER();
|
2020-04-15 12:51:27 +00:00
|
|
|
adc_rtc_chan_init(ADC_UNIT_2);
|
2019-09-09 12:56:46 +00:00
|
|
|
adc_hal_set_atten(ADC_NUM_2, channel, atten);
|
2021-01-31 17:12:28 +00:00
|
|
|
SARADC2_EXIT();
|
|
|
|
|
|
|
|
SARADC2_RELEASE();
|
2019-09-09 12:56:46 +00:00
|
|
|
|
2021-09-07 03:21:35 +00:00
|
|
|
#if SOC_ADC_CALIBRATION_V1_SUPPORTED
|
2021-01-19 12:00:01 +00:00
|
|
|
adc_hal_calibration_init(ADC_NUM_2);
|
|
|
|
#endif
|
|
|
|
|
2019-09-09 12:56:46 +00:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2021-01-31 17:12:28 +00:00
|
|
|
static inline void adc2_init(void)
|
2019-09-09 12:56:46 +00:00
|
|
|
{
|
2021-07-29 06:10:36 +00:00
|
|
|
#if CONFIG_IDF_TARGET_ESP32S2
|
2020-02-25 14:19:48 +00:00
|
|
|
#ifdef CONFIG_PM_ENABLE
|
|
|
|
/* Lock APB clock. */
|
|
|
|
if (s_adc2_arbiter_lock == NULL) {
|
|
|
|
esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "adc2", &s_adc2_arbiter_lock);
|
|
|
|
}
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|
|
|
#endif //CONFIG_PM_ENABLE
|
|
|
|
#endif //CONFIG_IDF_TARGET_ESP32S2
|
2019-09-09 12:56:46 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline void adc2_dac_disable( adc2_channel_t channel)
|
|
|
|
{
|
2021-04-06 13:56:27 +00:00
|
|
|
#if SOC_DAC_SUPPORTED
|
2020-02-25 14:19:48 +00:00
|
|
|
#ifdef CONFIG_IDF_TARGET_ESP32
|
2019-09-09 12:56:46 +00:00
|
|
|
if ( channel == ADC2_CHANNEL_8 ) { // the same as DAC channel 1
|
|
|
|
dac_output_disable(DAC_CHANNEL_1);
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|
|
|
} else if ( channel == ADC2_CHANNEL_9 ) {
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|
|
|
dac_output_disable(DAC_CHANNEL_2);
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|
|
|
}
|
2020-11-26 08:56:13 +00:00
|
|
|
#else
|
2020-02-25 14:19:48 +00:00
|
|
|
if ( channel == ADC2_CHANNEL_6 ) { // the same as DAC channel 1
|
|
|
|
dac_output_disable(DAC_CHANNEL_1);
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|
|
|
} else if ( channel == ADC2_CHANNEL_7 ) {
|
|
|
|
dac_output_disable(DAC_CHANNEL_2);
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|
|
|
}
|
|
|
|
#endif
|
2021-04-06 13:56:27 +00:00
|
|
|
#endif // SOC_DAC_SUPPORTED
|
2019-09-09 12:56:46 +00:00
|
|
|
}
|
|
|
|
|
2020-02-25 14:19:48 +00:00
|
|
|
/**
|
|
|
|
* @note For ESP32S2:
|
|
|
|
* The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
|
|
|
|
* Or, the RTC controller will fail when get raw data.
|
|
|
|
* This issue does not occur on digital controllers (DMA mode), and the hardware guarantees that there will be no errors.
|
|
|
|
*/
|
2019-09-09 12:56:46 +00:00
|
|
|
esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *raw_out)
|
|
|
|
{
|
2021-02-23 13:40:15 +00:00
|
|
|
esp_err_t ret = ESP_OK;
|
2020-02-25 14:19:48 +00:00
|
|
|
int adc_value = 0;
|
|
|
|
|
|
|
|
ADC_CHECK(raw_out != NULL, "ADC out value err", ESP_ERR_INVALID_ARG);
|
2019-09-09 12:56:46 +00:00
|
|
|
ADC_CHECK(channel < ADC2_CHANNEL_MAX, "ADC Channel Err", ESP_ERR_INVALID_ARG);
|
2021-06-08 09:38:46 +00:00
|
|
|
#if CONFIG_IDF_TARGET_ESP32
|
2020-02-25 14:19:48 +00:00
|
|
|
ADC_CHECK(width_bit < ADC_WIDTH_MAX, "WIDTH ERR: ESP32 support 9 ~ 12 bit width", ESP_ERR_INVALID_ARG);
|
2020-11-26 08:56:13 +00:00
|
|
|
#else
|
2021-06-08 09:38:46 +00:00
|
|
|
ADC_CHECK(width_bit == ADC_WIDTH_MAX - 1, "WIDTH ERR: see `adc_bits_width_t` for supported bit width", ESP_ERR_INVALID_ARG);
|
2020-02-25 14:19:48 +00:00
|
|
|
#endif
|
2019-09-09 12:56:46 +00:00
|
|
|
|
2021-09-07 03:21:35 +00:00
|
|
|
#if SOC_ADC_CALIBRATION_V1_SUPPORTED
|
2020-12-08 07:51:27 +00:00
|
|
|
// Get calibration value before going into critical section
|
|
|
|
uint32_t cal_val = get_calibration_offset(ADC_NUM_2, channel);
|
2021-01-31 17:12:28 +00:00
|
|
|
adc_hal_set_calibration_param(ADC_NUM_2, cal_val);
|
2021-09-07 03:21:35 +00:00
|
|
|
#endif //SOC_ADC_CALIBRATION_V1_SUPPORTED
|
2020-12-08 07:51:27 +00:00
|
|
|
|
2021-01-31 17:12:28 +00:00
|
|
|
if ( SARADC2_TRY_ACQUIRE() == -1 ) {
|
|
|
|
//try the lock, return if failed (wifi using).
|
2019-09-09 12:56:46 +00:00
|
|
|
return ESP_ERR_TIMEOUT;
|
|
|
|
}
|
2021-01-31 17:12:28 +00:00
|
|
|
adc_power_acquire(); //in critical section with whole rtc module
|
|
|
|
|
|
|
|
//avoid collision with other tasks
|
|
|
|
adc2_init(); // in critical section with whole rtc module. because the PWDET use the same registers, place it here.
|
|
|
|
SARADC2_ENTER();
|
2021-06-28 03:39:30 +00:00
|
|
|
|
|
|
|
#if SOC_ADC_ARBITER_SUPPORTED
|
|
|
|
adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
|
|
|
|
adc_hal_arbiter_config(&config);
|
|
|
|
#endif
|
|
|
|
|
2019-09-09 12:56:46 +00:00
|
|
|
#ifdef CONFIG_ADC_DISABLE_DAC
|
2020-02-25 14:19:48 +00:00
|
|
|
adc2_dac_disable(channel); //disable other peripherals
|
2019-09-09 12:56:46 +00:00
|
|
|
#endif
|
2021-01-31 17:12:28 +00:00
|
|
|
adc_hal_rtc_set_output_format(ADC_NUM_2, width_bit);
|
2021-12-22 03:17:42 +00:00
|
|
|
|
|
|
|
#if CONFIG_IDF_TARGET_ESP32
|
|
|
|
adc_ll_set_controller(ADC_NUM_2, ADC_LL_CTRL_RTC);// set controller
|
2021-06-08 09:38:46 +00:00
|
|
|
#else
|
2021-12-22 03:17:42 +00:00
|
|
|
adc_ll_set_controller(ADC_NUM_2, ADC_LL_CTRL_ARB);// set controller
|
2021-06-08 09:38:46 +00:00
|
|
|
#endif
|
2019-09-09 12:56:46 +00:00
|
|
|
|
2021-07-29 06:10:36 +00:00
|
|
|
#if CONFIG_IDF_TARGET_ESP32S2
|
2020-02-25 14:19:48 +00:00
|
|
|
#ifdef CONFIG_PM_ENABLE
|
|
|
|
if (s_adc2_arbiter_lock) {
|
|
|
|
esp_pm_lock_acquire(s_adc2_arbiter_lock);
|
2019-09-09 12:56:46 +00:00
|
|
|
}
|
2020-02-25 14:19:48 +00:00
|
|
|
#endif //CONFIG_PM_ENABLE
|
|
|
|
#endif //CONFIG_IDF_TARGET_ESP32
|
2019-09-09 12:56:46 +00:00
|
|
|
|
2021-02-23 13:40:15 +00:00
|
|
|
ret = adc_hal_convert(ADC_NUM_2, channel, &adc_value);
|
|
|
|
if (ret != ESP_OK) {
|
2020-02-25 14:19:48 +00:00
|
|
|
adc_value = -1;
|
|
|
|
}
|
2019-09-09 12:56:46 +00:00
|
|
|
|
2021-06-08 09:38:46 +00:00
|
|
|
#if CONFIG_IDF_TARGET_ESP32S2
|
2020-02-25 14:19:48 +00:00
|
|
|
#ifdef CONFIG_PM_ENABLE
|
|
|
|
/* Release APB clock. */
|
|
|
|
if (s_adc2_arbiter_lock) {
|
|
|
|
esp_pm_lock_release(s_adc2_arbiter_lock);
|
|
|
|
}
|
|
|
|
#endif //CONFIG_PM_ENABLE
|
|
|
|
#endif //CONFIG_IDF_TARGET_ESP32
|
2021-01-31 17:12:28 +00:00
|
|
|
SARADC2_EXIT();
|
2019-09-09 12:56:46 +00:00
|
|
|
|
2021-01-31 17:12:28 +00:00
|
|
|
adc_power_release();
|
|
|
|
SARADC2_RELEASE();
|
2019-09-09 12:56:46 +00:00
|
|
|
|
2020-02-25 14:19:48 +00:00
|
|
|
*raw_out = adc_value;
|
2021-02-23 13:40:15 +00:00
|
|
|
return ret;
|
2019-09-09 12:56:46 +00:00
|
|
|
}
|
|
|
|
|
2020-06-03 09:38:10 +00:00
|
|
|
esp_err_t adc2_vref_to_gpio(gpio_num_t gpio)
|
|
|
|
{
|
|
|
|
return adc_vref_to_gpio(ADC_UNIT_2, gpio);
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_IDF_TARGET_ESP32
|
2020-12-03 12:08:59 +00:00
|
|
|
if (adc_unit & ADC_UNIT_1) {
|
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
2020-06-03 09:38:10 +00:00
|
|
|
#endif
|
|
|
|
adc2_channel_t ch = ADC2_CHANNEL_MAX;
|
|
|
|
/* Check if the GPIO supported. */
|
|
|
|
for (int i = 0; i < ADC2_CHANNEL_MAX; i++) {
|
|
|
|
if (gpio == ADC_GET_IO_NUM(ADC_NUM_2, i)) {
|
|
|
|
ch = i;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2020-12-03 12:08:59 +00:00
|
|
|
if (ch == ADC2_CHANNEL_MAX) {
|
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
2020-06-03 09:38:10 +00:00
|
|
|
|
2021-01-31 17:12:28 +00:00
|
|
|
adc_power_acquire();
|
2020-06-03 09:38:10 +00:00
|
|
|
if (adc_unit & ADC_UNIT_1) {
|
2021-01-31 17:12:28 +00:00
|
|
|
VREF_ENTER(1);
|
2020-06-03 09:38:10 +00:00
|
|
|
adc_hal_vref_output(ADC_NUM_1, ch, true);
|
2021-01-31 17:12:28 +00:00
|
|
|
VREF_EXIT(1);
|
2020-06-03 09:38:10 +00:00
|
|
|
} else if (adc_unit & ADC_UNIT_2) {
|
2021-01-31 17:12:28 +00:00
|
|
|
VREF_ENTER(2);
|
2020-06-03 09:38:10 +00:00
|
|
|
adc_hal_vref_output(ADC_NUM_2, ch, true);
|
2021-01-31 17:12:28 +00:00
|
|
|
VREF_EXIT(2);
|
2020-06-03 09:38:10 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
//Configure RTC gpio, Only ADC2's channels IO are supported to output reference voltage.
|
2021-12-22 03:17:42 +00:00
|
|
|
adc_common_gpio_init(ADC_UNIT_2, ch);
|
2020-06-03 09:38:10 +00:00
|
|
|
return ESP_OK;
|
2020-07-29 12:46:37 +00:00
|
|
|
}
|
2021-01-31 17:12:28 +00:00
|
|
|
|
2021-09-07 03:21:35 +00:00
|
|
|
#endif //SOC_ADC_RTC_CTRL_SUPPORTED
|