kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
F61.440
Антон
rodzic
1007dd021c
commit
0588c10ab9
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# # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35
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#
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preplace inst DEBUG2.in_system_sources_probes_0 -pg 1 -lvl 1 -y 30
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preplace inst DEBUG2 -pg 1 -lvl 1 -y 40 -regy -20
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preplace netloc EXPORT<net_container>DEBUG2</net_container>(SLAVE)DEBUG2.probes,(SLAVE)in_system_sources_probes_0.probes) 1 0 1 N
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levelinfo -pg 1 0 50 280
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levelinfo -hier DEBUG2 60 130 260
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@ -0,0 +1,7 @@
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# # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35
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#
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preplace inst DEBUG -pg 1 -lvl 1 -y 40 -regy -20
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preplace inst DEBUG.in_system_sources_probes_0 -pg 1 -lvl 1 -y 30
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preplace netloc EXPORT<net_container>DEBUG</net_container>(SLAVE)DEBUG.probes,(SLAVE)in_system_sources_probes_0.probes) 1 0 1 N
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levelinfo -pg 1 0 50 280
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levelinfo -hier DEBUG 60 130 260
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# # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35
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#
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preplace inst NCO_TX -pg 1 -lvl 1 -y 40 -regy -20
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preplace inst NCO_TX.nco_ii_0 -pg 1 -lvl 1 -y 30
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preplace netloc EXPORT<net_container>NCO_TX</net_container>(SLAVE)nco_ii_0.out,(SLAVE)NCO_TX.out) 1 0 1 NJ
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preplace netloc EXPORT<net_container>NCO_TX</net_container>(SLAVE)nco_ii_0.clk,(SLAVE)NCO_TX.clk) 1 0 1 NJ
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preplace netloc EXPORT<net_container>NCO_TX</net_container>(SLAVE)nco_ii_0.in,(SLAVE)NCO_TX.in) 1 0 1 NJ
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preplace netloc EXPORT<net_container>NCO_TX</net_container>(SLAVE)nco_ii_0.rst,(SLAVE)NCO_TX.rst) 1 0 1 NJ
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levelinfo -pg 1 0 30 160
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levelinfo -hier NCO_TX 40 70 150
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# # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35
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#
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preplace inst unsaved.altclkctrl_0 -pg 1 -lvl 1 -y 30
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preplace inst unsaved -pg 1 -lvl 1 -y 40 -regy -20
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preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)unsaved.altclkctrl_output,(SLAVE)altclkctrl_0.altclkctrl_output) 1 0 1 NJ
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preplace netloc EXPORT<net_container>unsaved</net_container>(SLAVE)unsaved.altclkctrl_input,(SLAVE)altclkctrl_0.altclkctrl_input) 1 0 1 NJ
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levelinfo -pg 1 0 120 310
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levelinfo -hier unsaved 130 160 300
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@ -0,0 +1,2 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<filters version="18.1" />
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# # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35
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#
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preplace inst nco -pg 1 -lvl 1 -y 40 -regy -20
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preplace inst nco.nco_ii_0 -pg 1 -lvl 1 -y 30
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preplace netloc EXPORT<net_container>nco</net_container>(SLAVE)nco_ii_0.clk,(SLAVE)nco.clk) 1 0 1 NJ
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preplace netloc EXPORT<net_container>nco</net_container>(SLAVE)nco.in,(SLAVE)nco_ii_0.in) 1 0 1 NJ
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preplace netloc EXPORT<net_container>nco</net_container>(SLAVE)nco.out,(SLAVE)nco_ii_0.out) 1 0 1 NJ
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preplace netloc EXPORT<net_container>nco</net_container>(SLAVE)nco.rst,(SLAVE)nco_ii_0.rst) 1 0 1 NJ
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levelinfo -pg 1 0 30 160
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levelinfo -hier nco 40 70 150
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@ -0,0 +1,13 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<preferences>
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<debug showDebugMenu="0" />
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<systemtable filter="All Interfaces">
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<columns>
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<connections preferredWidth="31" />
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<irq preferredWidth="34" />
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</columns>
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</systemtable>
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<library expandedCategories="Project,Library" />
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<window width="1936" height="1056" x="-8" y="-8" />
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<generation path="_PROJECT_NAME_" />
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</preferences>
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# # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35
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#
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preplace inst rx_cic -pg 1 -lvl 1 -y 40 -regy -20
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preplace inst rx_cic.cic_ii_0 -pg 1 -lvl 1 -y 30
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preplace netloc EXPORT<net_container>rx_cic</net_container>(SLAVE)rx_cic.reset,(SLAVE)cic_ii_0.reset) 1 0 1 NJ
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preplace netloc EXPORT<net_container>rx_cic</net_container>(SLAVE)cic_ii_0.clken,(SLAVE)rx_cic.clken) 1 0 1 NJ
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preplace netloc EXPORT<net_container>rx_cic</net_container>(SLAVE)rx_cic.clock,(SLAVE)cic_ii_0.clock) 1 0 1 NJ
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preplace netloc EXPORT<net_container>rx_cic</net_container>(SLAVE)cic_ii_0.av_st_out,(SLAVE)rx_cic.av_st_out) 1 0 1 NJ
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preplace netloc EXPORT<net_container>rx_cic</net_container>(SLAVE)cic_ii_0.av_st_in,(SLAVE)rx_cic.av_st_in) 1 0 1 NJ
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levelinfo -pg 1 0 70 210
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levelinfo -hier rx_cic 80 110 200
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# # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35
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#
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preplace inst tx_cic -pg 1 -lvl 1 -y 40 -regy -20
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preplace inst tx_cic.cic_ii_0 -pg 1 -lvl 1 -y 30
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preplace netloc EXPORT<net_container>tx_cic</net_container>(SLAVE)cic_ii_0.av_st_out,(SLAVE)tx_cic.av_st_out) 1 0 1 NJ
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preplace netloc EXPORT<net_container>tx_cic</net_container>(SLAVE)cic_ii_0.av_st_in,(SLAVE)tx_cic.av_st_in) 1 0 1 NJ
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preplace netloc EXPORT<net_container>tx_cic</net_container>(SLAVE)cic_ii_0.reset,(SLAVE)tx_cic.reset) 1 0 1 NJ
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preplace netloc EXPORT<net_container>tx_cic</net_container>(SLAVE)cic_ii_0.clock,(SLAVE)tx_cic.clock) 1 0 1 NJ
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levelinfo -pg 1 0 70 210
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levelinfo -hier tx_cic 80 110 200
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# # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35
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#
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preplace inst tx_nco.nco_ii_0 -pg 1 -lvl 1 -y 30
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preplace inst tx_nco -pg 1 -lvl 1 -y 40 -regy -20
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preplace netloc EXPORT<net_container>tx_nco</net_container>(SLAVE)nco_ii_0.rst,(SLAVE)tx_nco.rst) 1 0 1 NJ
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preplace netloc EXPORT<net_container>tx_nco</net_container>(SLAVE)nco_ii_0.in,(SLAVE)tx_nco.in) 1 0 1 NJ
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preplace netloc EXPORT<net_container>tx_nco</net_container>(SLAVE)tx_nco.clk,(SLAVE)nco_ii_0.clk) 1 0 1 NJ
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preplace netloc EXPORT<net_container>tx_nco</net_container>(SLAVE)nco_ii_0.out,(SLAVE)tx_nco.out) 1 0 1 NJ
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levelinfo -pg 1 0 30 160
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levelinfo -hier tx_nco 40 70 150
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@ -0,0 +1,77 @@
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/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
*/
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||||
(header "symbol" (version "1.2"))
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||||
(symbol
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(rect 0 0 160 112)
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(text "ADC_Latch" (rect 48 0 125 16)(font "Arial" (font_size 10)))
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||||
(text "inst" (rect 8 96 25 108)(font "Arial" ))
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(port
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(pt 0 40)
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||||
(input)
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||||
(text "dataa[11..0]" (rect 0 0 66 14)(font "Arial" (font_size 8)))
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||||
(text "dataa[11..0]" (rect 4 26 58 39)(font "Arial" (font_size 8)))
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||||
(line (pt 0 40)(pt 64 40)(line_width 3))
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||||
)
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||||
(port
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||||
(pt 0 72)
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||||
(input)
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||||
(text "datab[11..0]" (rect 0 0 66 14)(font "Arial" (font_size 8)))
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||||
(text "datab[11..0]" (rect 4 58 58 71)(font "Arial" (font_size 8)))
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||||
(line (pt 0 72)(pt 64 72)(line_width 3))
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||||
)
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||||
(port
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||||
(pt 0 96)
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||||
(input)
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||||
(text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8)))
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||||
(text "clken" (rect 4 82 27 95)(font "Arial" (font_size 8)))
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||||
(line (pt 0 96)(pt 80 96))
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||||
)
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||||
(port
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||||
(pt 0 56)
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||||
(input)
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||||
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
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||||
(text "clock" (rect 4 42 27 55)(font "Arial" (font_size 8)))
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||||
(line (pt 0 56)(pt 64 56))
|
||||
)
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||||
(port
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||||
(pt 160 56)
|
||||
(output)
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||||
(text "result[11..0]" (rect 0 0 66 14)(font "Arial" (font_size 8)))
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||||
(text "result[11..0]" (rect 101 42 155 55)(font "Arial" (font_size 8)))
|
||||
(line (pt 160 56)(pt 96 56)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "A+B" (rect 75 51 169 115)(font "Arial" (font_size 8)))
|
||||
(text "A" (rect 64 35 134 83)(font "Arial" (font_size 8)))
|
||||
(text "B" (rect 65 67 135 147)(font "Arial" (font_size 8)))
|
||||
(line (pt 64 32)(pt 64 80))
|
||||
(line (pt 64 32)(pt 96 40))
|
||||
(line (pt 64 80)(pt 96 72))
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||||
(line (pt 96 40)(pt 96 72))
|
||||
(line (pt 80 76)(pt 80 96))
|
||||
(line (pt 0 0)(pt 162 0))
|
||||
(line (pt 162 0)(pt 162 114))
|
||||
(line (pt 0 114)(pt 162 114))
|
||||
(line (pt 0 0)(pt 0 114))
|
||||
(line (pt 64 50)(pt 70 56))
|
||||
(line (pt 70 56)(pt 64 62))
|
||||
)
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||||
)
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||||
|
|
@ -0,0 +1,5 @@
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|||
set_global_assignment -name IP_TOOL_NAME "LPM_ADD_SUB"
|
||||
set_global_assignment -name IP_TOOL_VERSION "18.1"
|
||||
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ADC_Latch.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ADC_Latch.bsf"]
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||||
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@ -0,0 +1,127 @@
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|||
// megafunction wizard: %LPM_ADD_SUB%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_ADD_SUB
|
||||
|
||||
// ============================================================
|
||||
// File Name: ADC_Latch.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_ADD_SUB
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 18.1.0 Build 625 09/12/2018 SJ Standard Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
//Your use of Intel Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Intel Program License
|
||||
//Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
//the Intel FPGA IP License Agreement, or other applicable license
|
||||
//agreement, including, without limitation, that your use is for
|
||||
//the sole purpose of programming logic devices manufactured by
|
||||
//Intel and sold by Intel or its authorized distributors. Please
|
||||
//refer to the applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module ADC_Latch (
|
||||
clken,
|
||||
clock,
|
||||
dataa,
|
||||
datab,
|
||||
result);
|
||||
|
||||
input clken;
|
||||
input clock;
|
||||
input [11:0] dataa;
|
||||
input [11:0] datab;
|
||||
output [11:0] result;
|
||||
|
||||
wire [11:0] sub_wire0;
|
||||
wire [11:0] result = sub_wire0[11:0];
|
||||
|
||||
lpm_add_sub LPM_ADD_SUB_component (
|
||||
.clken (clken),
|
||||
.clock (clock),
|
||||
.dataa (dataa),
|
||||
.datab (datab),
|
||||
.result (sub_wire0)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.aclr (),
|
||||
.add_sub (),
|
||||
.cin (),
|
||||
.cout (),
|
||||
.overflow ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
LPM_ADD_SUB_component.lpm_direction = "ADD",
|
||||
LPM_ADD_SUB_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
|
||||
LPM_ADD_SUB_component.lpm_pipeline = 1,
|
||||
LPM_ADD_SUB_component.lpm_representation = "SIGNED",
|
||||
LPM_ADD_SUB_component.lpm_type = "LPM_ADD_SUB",
|
||||
LPM_ADD_SUB_component.lpm_width = 12;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Function NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Latency NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: RadixA NUMERIC "10"
|
||||
// Retrieval info: PRIVATE: RadixB NUMERIC "10"
|
||||
// Retrieval info: PRIVATE: Representation NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: aclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: clken NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: nBit NUMERIC "12"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
|
||||
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
|
||||
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL "clken"
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||
// Retrieval info: USED_PORT: dataa 0 0 12 0 INPUT NODEFVAL "dataa[11..0]"
|
||||
// Retrieval info: USED_PORT: datab 0 0 12 0 INPUT NODEFVAL "datab[11..0]"
|
||||
// Retrieval info: USED_PORT: result 0 0 12 0 OUTPUT NODEFVAL "result[11..0]"
|
||||
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
|
||||
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @dataa 0 0 12 0 dataa 0 0 12 0
|
||||
// Retrieval info: CONNECT: @datab 0 0 12 0 datab 0 0 12 0
|
||||
// Retrieval info: CONNECT: result 0 0 12 0 @result 0 0 12 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Latch.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Latch.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Latch.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Latch.bsf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Latch_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL ADC_Latch_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 16 16 264 128)
|
||||
(text "DAC_corrector" (rect 5 0 69 12)(font "Arial" ))
|
||||
(text "inst" (rect 8 96 20 108)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "clk_in" (rect 0 0 22 12)(font "Arial" ))
|
||||
(text "clk_in" (rect 21 27 43 39)(font "Arial" ))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "DATA_IN[31..0]" (rect 0 0 68 12)(font "Arial" ))
|
||||
(text "DATA_IN[31..0]" (rect 21 43 89 55)(font "Arial" ))
|
||||
(line (pt 0 48)(pt 16 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "distance[7..0]" (rect 0 0 51 12)(font "Arial" ))
|
||||
(text "distance[7..0]" (rect 21 59 72 71)(font "Arial" ))
|
||||
(line (pt 0 64)(pt 16 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 248 32)
|
||||
(output)
|
||||
(text "DATA_OUT[13..0]" (rect 0 0 79 12)(font "Arial" ))
|
||||
(text "DATA_OUT[13..0]" (rect 148 27 227 39)(font "Arial" ))
|
||||
(line (pt 248 32)(pt 232 32)(line_width 3))
|
||||
)
|
||||
(parameter
|
||||
"in_width"
|
||||
"32"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(parameter
|
||||
"out_width"
|
||||
"14"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(drawing
|
||||
(rectangle (rect 16 16 232 96)(line_width 1))
|
||||
)
|
||||
(annotation_block (parameter)(rect 264 -64 364 16))
|
||||
)
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
module DAC_corrector(
|
||||
clk_in,
|
||||
DATA_IN,
|
||||
distance,
|
||||
|
||||
DATA_OUT
|
||||
);
|
||||
|
||||
parameter in_width = 32;
|
||||
parameter out_width = 14;
|
||||
|
||||
input clk_in;
|
||||
input signed [31:0] DATA_IN;
|
||||
input unsigned [7:0] distance;
|
||||
|
||||
output reg unsigned [13:0] DATA_OUT;
|
||||
|
||||
reg signed [13:0] tmp=0;
|
||||
|
||||
always @ (posedge clk_in)
|
||||
begin
|
||||
//получаем 14 бит
|
||||
if (distance<out_width)
|
||||
begin
|
||||
tmp[(out_width-1):0] = DATA_IN[(out_width-1):0];
|
||||
end
|
||||
if (distance>in_width)
|
||||
begin
|
||||
tmp[(out_width-1):0] = DATA_IN[(in_width-1) -: out_width];
|
||||
end
|
||||
else
|
||||
begin
|
||||
tmp[(out_width-1):0] = DATA_IN[(distance-1) -: out_width];
|
||||
end
|
||||
|
||||
DATA_OUT[(out_width-1):0]={~tmp[(out_width-1)],tmp[(out_width-2):0]}; //инвертируем первый бит, получая unsigned из two's complement
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<system name="$${FILENAME}">
|
||||
<component
|
||||
name="$${FILENAME}"
|
||||
displayName="$${FILENAME}"
|
||||
version="1.0"
|
||||
description=""
|
||||
tags="INTERNAL_COMPONENT=true"
|
||||
categories="System" />
|
||||
<parameter name="bonusData"><![CDATA[bonusData
|
||||
{
|
||||
element in_system_sources_probes_0
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "0";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
}
|
||||
]]></parameter>
|
||||
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
|
||||
<parameter name="device" value="EP4CE10E22C8" />
|
||||
<parameter name="deviceFamily" value="Cyclone IV E" />
|
||||
<parameter name="deviceSpeedGrade" value="8" />
|
||||
<parameter name="fabricMode" value="QSYS" />
|
||||
<parameter name="generateLegacySim" value="false" />
|
||||
<parameter name="generationId" value="0" />
|
||||
<parameter name="globalResetBus" value="false" />
|
||||
<parameter name="hdlLanguage" value="VERILOG" />
|
||||
<parameter name="hideFromIPCatalog" value="true" />
|
||||
<parameter name="lockedInterfaceDefinition" value="" />
|
||||
<parameter name="maxAdditionalLatency" value="1" />
|
||||
<parameter name="projectName" value="WOLF.qpf" />
|
||||
<parameter name="sopcBorderPoints" value="false" />
|
||||
<parameter name="systemHash" value="0" />
|
||||
<parameter name="testBenchDutName" value="" />
|
||||
<parameter name="timeStamp" value="0" />
|
||||
<parameter name="useTestBenchNamingPattern" value="false" />
|
||||
<instanceScript></instanceScript>
|
||||
<interface
|
||||
name="probes"
|
||||
internal="in_system_sources_probes_0.probes"
|
||||
type="conduit"
|
||||
dir="end">
|
||||
<port name="probe" internal="probe" />
|
||||
</interface>
|
||||
<interface name="sources" internal="in_system_sources_probes_0.sources" />
|
||||
<module
|
||||
name="in_system_sources_probes_0"
|
||||
kind="altera_in_system_sources_probes"
|
||||
version="18.1"
|
||||
enabled="1"
|
||||
autoexport="1">
|
||||
<parameter name="create_source_clock" value="false" />
|
||||
<parameter name="create_source_clock_enable" value="false" />
|
||||
<parameter name="device_family" value="Cyclone IV E" />
|
||||
<parameter name="gui_use_auto_index" value="true" />
|
||||
<parameter name="instance_id" value="ADC" />
|
||||
<parameter name="probe_width" value="12" />
|
||||
<parameter name="sld_instance_index" value="0" />
|
||||
<parameter name="source_initial_value" value="0" />
|
||||
<parameter name="source_width" value="0" />
|
||||
</module>
|
||||
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
|
||||
</system>
|
||||
|
|
@ -0,0 +1,256 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<EnsembleReport name="DEBUG" kind="DEBUG" version="1.0" fabric="QSYS">
|
||||
<!-- Format version 18.1 625 (Future versions may contain additional information.) -->
|
||||
<!-- 2021.03.31.22:16:32 -->
|
||||
<!-- A collection of modules and connections -->
|
||||
<parameter name="AUTO_GENERATION_ID">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>1617214592</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>GENERATION_ID</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_UNIQUE_ID">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>UNIQUE_ID</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE_FAMILY">
|
||||
<type>java.lang.String</type>
|
||||
<value>CYCLONEIVE</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE">
|
||||
<type>java.lang.String</type>
|
||||
<value>EP4CE10E22C8</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE">
|
||||
<type>java.lang.String</type>
|
||||
<value>8</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>Cyclone IV E</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<module
|
||||
name="in_system_sources_probes_0"
|
||||
kind="altera_in_system_sources_probes"
|
||||
version="18.1"
|
||||
path="in_system_sources_probes_0">
|
||||
<!-- Describes a single module. Module parameters are
|
||||
the requested settings for a module instance. -->
|
||||
<assignment>
|
||||
<name>embeddedsw.dts.group</name>
|
||||
<value>ignore</value>
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.dts.name</name>
|
||||
<value>debug</value>
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.dts.vendor</name>
|
||||
<value>altr</value>
|
||||
</assignment>
|
||||
<parameter name="device_family">
|
||||
<type>java.lang.String</type>
|
||||
<value>CYCLONEIVE</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="gui_use_auto_index">
|
||||
<type>boolean</type>
|
||||
<value>true</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="sld_auto_instance_index">
|
||||
<type>java.lang.String</type>
|
||||
<value>YES</value>
|
||||
<derived>true</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="sld_instance_index">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="instance_id">
|
||||
<type>java.lang.String</type>
|
||||
<value>ADC</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="probe_width">
|
||||
<type>int</type>
|
||||
<value>12</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="source_width">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="source_initial_value">
|
||||
<type>java.lang.String</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="create_source_clock">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="create_source_clock_enable">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="enable_metastability">
|
||||
<type>java.lang.String</type>
|
||||
<value>NO</value>
|
||||
<derived>true</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<interface name="probes" kind="conduit_end" version="18.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="associatedClock">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="associatedReset">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>conduit</type>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>probe</name>
|
||||
<direction>Input</direction>
|
||||
<width>12</width>
|
||||
<role>probe</role>
|
||||
</port>
|
||||
</interface>
|
||||
</module>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>altera_in_system_sources_probes</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IModule</subtype>
|
||||
<displayName><![CDATA[Altera In-System Sources & Probes]]></displayName>
|
||||
<version>18.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>conduit_end</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
<displayName>Conduit</displayName>
|
||||
<version>18.1</version>
|
||||
</plugin>
|
||||
<reportVersion>18.1 625</reportVersion>
|
||||
<uniqueIdentifier></uniqueIdentifier>
|
||||
</EnsembleReport>
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 176 104)
|
||||
(text "DEBUG" (rect 66 -1 100 11)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 88 20 100)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "probe[11..0]" (rect 0 0 44 12)(font "Arial" (font_size 8)))
|
||||
(text "probe[11..0]" (rect 4 61 76 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 64 72)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "probes" (rect 25 43 86 99)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "probe" (rect 69 67 168 144)(font "Arial" (color 0 0 0)))
|
||||
(text " DEBUG " (rect 139 88 320 186)(font "Arial" ))
|
||||
(line (pt 64 32)(pt 112 32)(line_width 1))
|
||||
(line (pt 112 32)(pt 112 88)(line_width 1))
|
||||
(line (pt 64 88)(pt 112 88)(line_width 1))
|
||||
(line (pt 64 32)(pt 64 88)(line_width 1))
|
||||
(line (pt 65 52)(pt 65 76)(line_width 1))
|
||||
(line (pt 66 52)(pt 66 76)(line_width 1))
|
||||
(line (pt 0 0)(pt 176 0)(line_width 1))
|
||||
(line (pt 176 0)(pt 176 104)(line_width 1))
|
||||
(line (pt 0 104)(pt 176 104)(line_width 1))
|
||||
(line (pt 0 0)(pt 0 104)(line_width 1))
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
component DEBUG is
|
||||
port (
|
||||
probe : in std_logic_vector(11 downto 0) := (others => 'X') -- probe
|
||||
);
|
||||
end component DEBUG;
|
||||
|
||||
|
|
@ -0,0 +1,177 @@
|
|||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml">
|
||||
<head>
|
||||
<title>datasheet for DEBUG</title>
|
||||
<style type="text/css">
|
||||
body { font-family:arial ;}
|
||||
a { text-decoration:underline ; color:#003000 ;}
|
||||
a:hover { text-decoration:underline ; color:0030f0 ;}
|
||||
td { padding : 5px ;}
|
||||
table.topTitle { width:100% ;}
|
||||
table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
|
||||
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
|
||||
table.blueBar { width : 100% ; border-spacing : 0px ;}
|
||||
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
|
||||
table.blueBar td.l { text-align : left ;}
|
||||
table.blueBar td.r { text-align : right ;}
|
||||
table.items { width:100% ; border-collapse:collapse ;}
|
||||
table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
|
||||
table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
|
||||
div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ; font-size:12px ;}
|
||||
body { font-family:arial ;}
|
||||
table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
|
||||
table.x td { border:1px solid #bbb ;}
|
||||
td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ;}
|
||||
table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
|
||||
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
|
||||
table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
|
||||
table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
|
||||
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
|
||||
table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
|
||||
table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
|
||||
table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
|
||||
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
|
||||
table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
|
||||
table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
|
||||
table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
|
||||
table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
|
||||
.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
|
||||
.flowbox { display:inline-block ;}
|
||||
.parametersbox table { font-size:10px ;}
|
||||
td.parametername { font-style:italic ;}
|
||||
td.parametervalue { font-weight:bold ;}
|
||||
div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
|
||||
</head>
|
||||
<body>
|
||||
<table class="topTitle">
|
||||
<tr>
|
||||
<td class="l">DEBUG</td>
|
||||
<td class="r">
|
||||
<br/>
|
||||
<br/>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">2020.10.21.00:22:12</td>
|
||||
<td class="r">Datasheet</td>
|
||||
</tr>
|
||||
</table>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Overview</div>
|
||||
<div class="greydiv">
|
||||
<div style="display:inline-block ; text-align:left">
|
||||
<table class="connectionboxes">
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><span style="display:inline-block ; width:28px"> </span>
|
||||
<div style="display:inline-block ; text-align:left"><span>
|
||||
<br/></span>
|
||||
</div>
|
||||
</div>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Memory Map</div>
|
||||
<table class="mmap">
|
||||
<tr>
|
||||
<td class="empty" rowspan="2"></td>
|
||||
</tr>
|
||||
</table>
|
||||
<a name="module_in_system_sources_probes_0"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>in_system_sources_probes_0</h2>altera_in_system_sources_probes v18.1
|
||||
<br/>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">device_family</td>
|
||||
<td class="parametervalue">CYCLONEIVE</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">gui_use_auto_index</td>
|
||||
<td class="parametervalue">true</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">sld_auto_instance_index</td>
|
||||
<td class="parametervalue">YES</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">sld_instance_index</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">instance_id</td>
|
||||
<td class="parametervalue">ADC</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">probe_width</td>
|
||||
<td class="parametervalue">12</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">source_width</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">source_initial_value</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">create_source_clock</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">create_source_clock_enable</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">enable_metastability</td>
|
||||
<td class="parametervalue">NO</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">deviceFamily</td>
|
||||
<td class="parametervalue">UNKNOWN</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>(none)</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">generation took 0,01 seconds</td>
|
||||
<td class="r">rendering took 0,02 seconds</td>
|
||||
</tr>
|
||||
</table>
|
||||
</body>
|
||||
</html>
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<pinplan
|
||||
variation_name="in_system_sources_probes_0"
|
||||
megafunction_name="ALTERA_IN_SYSTEM_SOURCES_PROBES"
|
||||
intended_family="Cyclone IV E"
|
||||
specifies="all_ports">
|
||||
<global>
|
||||
<pin name="probe[11..0]" direction="input" scope="external" />
|
||||
</global>
|
||||
</pinplan>
|
||||
|
|
@ -0,0 +1,127 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<deploy
|
||||
date="2020.10.21.00:22:13"
|
||||
outputDirectory="D:/Dropbox/Develop/Projects/WOLF-Lite/Scheme/FPGA/DEBUG/">
|
||||
<perimeter>
|
||||
<parameter
|
||||
name="AUTO_GENERATION_ID"
|
||||
type="Integer"
|
||||
defaultValue="0"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_UNIQUE_ID"
|
||||
type="String"
|
||||
defaultValue=""
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_FAMILY"
|
||||
type="String"
|
||||
defaultValue="Cyclone IV E"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE"
|
||||
type="String"
|
||||
defaultValue="EP4CE10E22C8"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_SPEEDGRADE"
|
||||
type="String"
|
||||
defaultValue="8"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<interface name="probes" kind="conduit" start="0">
|
||||
<property name="associatedClock" value="" />
|
||||
<property name="associatedReset" value="" />
|
||||
<port name="probe" direction="input" role="probe" width="12" />
|
||||
</interface>
|
||||
</perimeter>
|
||||
<entity
|
||||
path=""
|
||||
parameterizationKey="DEBUG:1.0:AUTO_DEVICE=EP4CE10E22C8,AUTO_DEVICE_FAMILY=Cyclone IV E,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1603225332,AUTO_UNIQUE_ID=(altera_in_system_sources_probes:18.1:create_source_clock=false,create_source_clock_enable=false,device_family=Cyclone IV E,enable_metastability=NO,gui_use_auto_index=true,instance_id=ADC,probe_width=12,sld_auto_instance_index=YES,sld_instance_index=0,source_initial_value=0,source_width=0)"
|
||||
instancePathKey="DEBUG"
|
||||
kind="DEBUG"
|
||||
version="1.0"
|
||||
name="DEBUG">
|
||||
<parameter name="AUTO_GENERATION_ID" value="1603225332" />
|
||||
<parameter name="AUTO_DEVICE" value="EP4CE10E22C8" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
|
||||
<parameter name="AUTO_UNIQUE_ID" value="" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
|
||||
<generatedFiles>
|
||||
<file
|
||||
path="D:/Dropbox/Develop/Projects/WOLF-Lite/Scheme/FPGA/DEBUG/synthesis/DEBUG.v"
|
||||
type="VERILOG" />
|
||||
</generatedFiles>
|
||||
<childGeneratedFiles>
|
||||
<file
|
||||
path="D:/Dropbox/Develop/Projects/WOLF-Lite/Scheme/FPGA/DEBUG/synthesis/submodules/altsource_probe_top.v"
|
||||
type="VERILOG"
|
||||
attributes="" />
|
||||
</childGeneratedFiles>
|
||||
<sourceFiles>
|
||||
<file path="D:/Dropbox/Develop/Projects/WOLF-Lite/Scheme/FPGA/DEBUG.qsys" />
|
||||
</sourceFiles>
|
||||
<childSourceFiles>
|
||||
<file
|
||||
path="C:/intelfpga/18.1/ip/altera/sld/jtag/altera_in_system_sources_probes/altera_in_system_sources_probes_hw.tcl" />
|
||||
</childSourceFiles>
|
||||
<messages>
|
||||
<message level="Debug" culprit="DEBUG">queue size: 0 starting:DEBUG "DEBUG"</message>
|
||||
<message level="Progress" culprit="min"></message>
|
||||
<message level="Progress" culprit="max"></message>
|
||||
<message level="Progress" culprit="current"></message>
|
||||
<message level="Debug">Transform: CustomInstructionTransform</message>
|
||||
<message level="Debug">No custom instruction connections, skipping transform </message>
|
||||
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
|
||||
<message level="Debug">Transform: MMTransform</message>
|
||||
<message level="Debug">Transform: InterruptMapperTransform</message>
|
||||
<message level="Debug">Transform: InterruptSyncTransform</message>
|
||||
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
||||
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
||||
<message level="Debug">Transform: ResetAdaptation</message>
|
||||
<message level="Debug" culprit="DEBUG"><![CDATA["<b>DEBUG</b>" reuses <b>altera_in_system_sources_probes</b> "<b>submodules/altsource_probe_top</b>"]]></message>
|
||||
<message level="Debug" culprit="DEBUG">queue size: 0 starting:altera_in_system_sources_probes "submodules/altsource_probe_top"</message>
|
||||
<message level="Info" culprit="in_system_sources_probes_0"><![CDATA["<b>DEBUG</b>" instantiated <b>altera_in_system_sources_probes</b> "<b>in_system_sources_probes_0</b>"]]></message>
|
||||
</messages>
|
||||
</entity>
|
||||
<entity
|
||||
path="submodules/"
|
||||
parameterizationKey="altera_in_system_sources_probes:18.1:create_source_clock=false,create_source_clock_enable=false,device_family=Cyclone IV E,enable_metastability=NO,gui_use_auto_index=true,instance_id=ADC,probe_width=12,sld_auto_instance_index=YES,sld_instance_index=0,source_initial_value=0,source_width=0"
|
||||
instancePathKey="DEBUG:.:in_system_sources_probes_0"
|
||||
kind="altera_in_system_sources_probes"
|
||||
version="18.1"
|
||||
name="altsource_probe_top">
|
||||
<parameter name="create_source_clock" value="false" />
|
||||
<parameter name="instance_id" value="ADC" />
|
||||
<parameter name="source_initial_value" value="0" />
|
||||
<parameter name="sld_auto_instance_index" value="YES" />
|
||||
<parameter name="sld_instance_index" value="0" />
|
||||
<parameter name="probe_width" value="12" />
|
||||
<parameter name="source_width" value="0" />
|
||||
<parameter name="create_source_clock_enable" value="false" />
|
||||
<parameter name="device_family" value="Cyclone IV E" />
|
||||
<parameter name="enable_metastability" value="NO" />
|
||||
<parameter name="gui_use_auto_index" value="true" />
|
||||
<generatedFiles>
|
||||
<file
|
||||
path="D:/Dropbox/Develop/Projects/WOLF-Lite/Scheme/FPGA/DEBUG/synthesis/submodules/altsource_probe_top.v"
|
||||
type="VERILOG"
|
||||
attributes="" />
|
||||
</generatedFiles>
|
||||
<childGeneratedFiles/>
|
||||
<sourceFiles>
|
||||
<file
|
||||
path="C:/intelfpga/18.1/ip/altera/sld/jtag/altera_in_system_sources_probes/altera_in_system_sources_probes_hw.tcl" />
|
||||
</sourceFiles>
|
||||
<childSourceFiles/>
|
||||
<instantiator instantiator="DEBUG" as="in_system_sources_probes_0" />
|
||||
<messages>
|
||||
<message level="Debug" culprit="DEBUG">queue size: 0 starting:altera_in_system_sources_probes "submodules/altsource_probe_top"</message>
|
||||
<message level="Info" culprit="in_system_sources_probes_0"><![CDATA["<b>DEBUG</b>" instantiated <b>altera_in_system_sources_probes</b> "<b>in_system_sources_probes_0</b>"]]></message>
|
||||
</messages>
|
||||
</entity>
|
||||
</deploy>
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
module DEBUG (
|
||||
probe);
|
||||
|
||||
input [11:0] probe;
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
DEBUG u0 (
|
||||
.probe (<connected-to-probe>) // probes.probe
|
||||
);
|
||||
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
component DEBUG is
|
||||
port (
|
||||
probe : in std_logic_vector(11 downto 0) := (others => 'X') -- probe
|
||||
);
|
||||
end component DEBUG;
|
||||
|
||||
u0 : component DEBUG
|
||||
port map (
|
||||
probe => CONNECTED_TO_probe -- probes.probe
|
||||
);
|
||||
|
||||
|
|
@ -0,0 +1,338 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<EnsembleReport name="DEBUG" kind="system" version="18.1" fabric="QSYS">
|
||||
<!-- Format version 18.1 625 (Future versions may contain additional information.) -->
|
||||
<!-- 2020.10.21.00:22:13 -->
|
||||
<!-- A collection of modules and connections -->
|
||||
<parameter name="clockCrossingAdapter">
|
||||
<type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
|
||||
<value>HANDSHAKE</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="device">
|
||||
<type>java.lang.String</type>
|
||||
<value>EP4CE10E22C8</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>CYCLONEIVE</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceSpeedGrade">
|
||||
<type>java.lang.String</type>
|
||||
<value>8</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="fabricMode">
|
||||
<type>com.altera.sopcmodel.ensemble.Ensemble$EFabricMode</type>
|
||||
<value>QSYS</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generationId">
|
||||
<type>int</type>
|
||||
<value>1603225332</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="globalResetBus">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="hdlLanguage">
|
||||
<type>com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage</type>
|
||||
<value>VERILOG</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="hideFromIPCatalog">
|
||||
<type>boolean</type>
|
||||
<value>true</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="lockedInterfaceDefinition">
|
||||
<type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="maxAdditionalLatency">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="projectName">
|
||||
<type>java.lang.String</type>
|
||||
<value>WOLF.qpf</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="sopcBorderPoints">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="systemHash">
|
||||
<type>long</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="testBenchDutName">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="timeStamp">
|
||||
<type>long</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="useTestBenchNamingPattern">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<module
|
||||
name="in_system_sources_probes_0"
|
||||
kind="altera_in_system_sources_probes"
|
||||
version="18.1"
|
||||
path="in_system_sources_probes_0">
|
||||
<!-- Describes a single module. Module parameters are
|
||||
the requested settings for a module instance. -->
|
||||
<assignment>
|
||||
<name>embeddedsw.dts.group</name>
|
||||
<value>ignore</value>
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.dts.name</name>
|
||||
<value>debug</value>
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.dts.vendor</name>
|
||||
<value>altr</value>
|
||||
</assignment>
|
||||
<parameter name="device_family">
|
||||
<type>java.lang.String</type>
|
||||
<value>CYCLONEIVE</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="gui_use_auto_index">
|
||||
<type>boolean</type>
|
||||
<value>true</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="sld_auto_instance_index">
|
||||
<type>java.lang.String</type>
|
||||
<value>YES</value>
|
||||
<derived>true</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="sld_instance_index">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="instance_id">
|
||||
<type>java.lang.String</type>
|
||||
<value>ADC</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="probe_width">
|
||||
<type>int</type>
|
||||
<value>12</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="source_width">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="source_initial_value">
|
||||
<type>java.lang.String</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="create_source_clock">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="create_source_clock_enable">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="enable_metastability">
|
||||
<type>java.lang.String</type>
|
||||
<value>NO</value>
|
||||
<derived>true</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<interface name="probes" kind="conduit_end" version="18.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="associatedClock">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="associatedReset">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>conduit</type>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>probe</name>
|
||||
<direction>Input</direction>
|
||||
<width>12</width>
|
||||
<role>probe</role>
|
||||
</port>
|
||||
</interface>
|
||||
</module>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>altera_in_system_sources_probes</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IModule</subtype>
|
||||
<displayName><![CDATA[Altera In-System Sources & Probes]]></displayName>
|
||||
<version>18.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>conduit_end</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
<displayName>Conduit</displayName>
|
||||
<version>18.1</version>
|
||||
</plugin>
|
||||
<reportVersion>18.1 625</reportVersion>
|
||||
<uniqueIdentifier>00FF00F878090000017547AD2CC5</uniqueIdentifier>
|
||||
</EnsembleReport>
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_TOOL_NAME "Qsys"
|
||||
set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_TOOL_VERSION "18.1"
|
||||
set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -library "DEBUG" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../DEBUG.sopcinfo"]
|
||||
set_global_assignment -entity "DEBUG" -library "DEBUG" -name SLD_INFO "QSYS_NAME DEBUG HAS_SOPCINFO 1 GENERATION_ID 1603225332"
|
||||
set_global_assignment -library "DEBUG" -name MISC_FILE [file join $::quartus(qip_path) "../DEBUG.cmp"]
|
||||
set_global_assignment -library "DEBUG" -name SLD_FILE [file join $::quartus(qip_path) "DEBUG.debuginfo"]
|
||||
set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_TARGETED_DEVICE_FAMILY "Cyclone IV E"
|
||||
set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
|
||||
set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_QSYS_MODE "STANDALONE"
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
set_global_assignment -library "DEBUG" -name MISC_FILE [file join $::quartus(qip_path) "../../DEBUG.qsys"]
|
||||
set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_COMPONENT_NAME "REVCVUc="
|
||||
set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_COMPONENT_DISPLAY_NAME "REVCVUc="
|
||||
set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
||||
set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_COMPONENT_VERSION "MS4w"
|
||||
set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTYwMzIyNTMzMg==::QXV0byBHRU5FUkFUSU9OX0lE"
|
||||
set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
|
||||
set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMEUyMkM4::QXV0byBERVZJQ0U="
|
||||
set_global_assignment -entity "DEBUG" -library "DEBUG" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_NAME "YWx0c291cmNlX3Byb2JlX3RvcA=="
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIEluLVN5c3RlbSBTb3VyY2VzICYgUHJvYmVz"
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_VERSION "MTguMQ=="
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_DESCRIPTION "SW4tc3lzdGVtIHNvdXJjZXMgJiBwcm9iZXMgZGVidWdnaW5nIG1lZ2FmdW5jdGlvbi4gIFRoZSBJbi1TeXN0ZW0gU291cmNlcyBhbmQgUHJvYmVzIG1lZ2FmdW5jdGlvbiBpcwphdmFpbGFibGUgZm9yIGFsbCBBbHRlcmEgZGV2aWNlIGZhbWlsaWVzIHN1cHBvcnRlZCBieSB0aGUgUXVhcnR1cyBQcmltZSBzb2Z0d2FyZS4="
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBJViBF::ZGV2aWNlX2ZhbWlseQ=="
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9hdXRvX2luZGV4::dHJ1ZQ==::QXV0b21hdGljIEluc3RhbmNlIEluZGV4IEFzc2lnbm1lbnQ="
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_PARAMETER "c2xkX2F1dG9faW5zdGFuY2VfaW5kZXg=::WUVT::c2xkX2F1dG9faW5zdGFuY2VfaW5kZXg="
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_PARAMETER "aW5zdGFuY2VfaWQ=::QURD::VGhlICdJbnN0YW5jZSBJRCcgb2YgdGhpcyBpbnN0YW5jZSAob3B0aW9uYWwp"
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_PARAMETER "cHJvYmVfd2lkdGg=::MTI=::UHJvYmUgUG9ydCBXaWR0aCBbMC4uNTEyXQ=="
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_PARAMETER "c291cmNlX3dpZHRo::MA==::U291cmNlIFBvcnQgV2lkdGggWzAuLjUxMl0="
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_COMPONENT_PARAMETER "ZW5hYmxlX21ldGFzdGFiaWxpdHk=::Tk8=::ZW5hYmxlX21ldGFzdGFiaWxpdHk="
|
||||
|
||||
set_global_assignment -library "DEBUG" -name VERILOG_FILE [file join $::quartus(qip_path) "DEBUG.v"]
|
||||
set_global_assignment -library "DEBUG" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altsource_probe_top.v"]
|
||||
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_TOOL_NAME "altera_in_system_sources_probes"
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_TOOL_VERSION "18.1"
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG" -name IP_TOOL_ENV "Qsys"
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
// DEBUG.v
|
||||
|
||||
// Generated using ACDS version 18.1 625
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module DEBUG (
|
||||
input wire [11:0] probe // probes.probe
|
||||
);
|
||||
|
||||
altsource_probe_top #(
|
||||
.sld_auto_instance_index ("YES"),
|
||||
.sld_instance_index (0),
|
||||
.instance_id ("ADC"),
|
||||
.probe_width (12),
|
||||
.source_width (0),
|
||||
.enable_metastability ("NO")
|
||||
) in_system_sources_probes_0 (
|
||||
.probe (probe) // probes.probe
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
// (C) 2001-2018 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
module altsource_probe_top
|
||||
#(
|
||||
parameter lpm_type = "altsource_probe", // required by the coding standard
|
||||
parameter lpm_hint = "UNUSED", // required by the coding standard
|
||||
|
||||
parameter sld_auto_instance_index = "YES", // Yes, if the instance index should be automatically assigned.
|
||||
parameter sld_instance_index = 0, // unique identifier for the altsource_probe instance.
|
||||
parameter sld_node_info_parameter = 4746752 + sld_instance_index, // The NODE ID to uniquely identify this node on the hub. Type ID: 9 Version: 0 Inst: 0 MFG ID 110 -- ***NOTE*** this parameter cannot be called SLD_NODE_INFO or Quartus Standard will think it's an ISSP impl.
|
||||
parameter sld_ir_width = 4,
|
||||
|
||||
parameter instance_id = "UNUSED", // optional name for the instance.
|
||||
parameter probe_width = 1, // probe port width
|
||||
parameter source_width= 1, // source port width
|
||||
parameter source_initial_value = "0", // initial source port value
|
||||
parameter enable_metastability = "NO" // yes to add two register
|
||||
)
|
||||
(
|
||||
input [probe_width - 1 : 0] probe, // probe inputs
|
||||
output [source_width - 1 : 0] source, // source outputs
|
||||
input source_clk, // clock of the registers used to metastabilize the source output
|
||||
input tri1 source_ena // enable of the registers used to metastabilize the source output
|
||||
);
|
||||
|
||||
altsource_probe #(
|
||||
.lpm_type(lpm_type),
|
||||
.lpm_hint(lpm_hint),
|
||||
.sld_auto_instance_index(sld_auto_instance_index),
|
||||
.sld_instance_index(sld_instance_index),
|
||||
.SLD_NODE_INFO(sld_node_info_parameter),
|
||||
.sld_ir_width(sld_ir_width),
|
||||
.instance_id(instance_id),
|
||||
.probe_width(probe_width),
|
||||
.source_width(source_width),
|
||||
.source_initial_value(source_initial_value),
|
||||
.enable_metastability(enable_metastability)
|
||||
)issp_impl
|
||||
(
|
||||
.probe(probe),
|
||||
.source(source),
|
||||
.source_clk(source_clk),
|
||||
.source_ena(source_ena)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<system name="$${FILENAME}">
|
||||
<component
|
||||
name="$${FILENAME}"
|
||||
displayName="$${FILENAME}"
|
||||
version="1.0"
|
||||
description=""
|
||||
tags="INTERNAL_COMPONENT=true"
|
||||
categories="System" />
|
||||
<parameter name="bonusData"><![CDATA[bonusData
|
||||
{
|
||||
element in_system_sources_probes_0
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "0";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
}
|
||||
]]></parameter>
|
||||
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
|
||||
<parameter name="device" value="EP4CE22E22C8" />
|
||||
<parameter name="deviceFamily" value="Cyclone IV E" />
|
||||
<parameter name="deviceSpeedGrade" value="8" />
|
||||
<parameter name="fabricMode" value="QSYS" />
|
||||
<parameter name="generateLegacySim" value="false" />
|
||||
<parameter name="generationId" value="0" />
|
||||
<parameter name="globalResetBus" value="false" />
|
||||
<parameter name="hdlLanguage" value="VERILOG" />
|
||||
<parameter name="hideFromIPCatalog" value="true" />
|
||||
<parameter name="lockedInterfaceDefinition" value="" />
|
||||
<parameter name="maxAdditionalLatency" value="1" />
|
||||
<parameter name="projectName" value="UA3REO.qpf" />
|
||||
<parameter name="sopcBorderPoints" value="false" />
|
||||
<parameter name="systemHash" value="0" />
|
||||
<parameter name="testBenchDutName" value="" />
|
||||
<parameter name="timeStamp" value="0" />
|
||||
<parameter name="useTestBenchNamingPattern" value="false" />
|
||||
<instanceScript></instanceScript>
|
||||
<interface
|
||||
name="probes"
|
||||
internal="in_system_sources_probes_0.probes"
|
||||
type="conduit"
|
||||
dir="end">
|
||||
<port name="probe" internal="probe" />
|
||||
</interface>
|
||||
<interface name="sources" internal="in_system_sources_probes_0.sources" />
|
||||
<module
|
||||
name="in_system_sources_probes_0"
|
||||
kind="altera_in_system_sources_probes"
|
||||
version="18.1"
|
||||
enabled="1"
|
||||
autoexport="1">
|
||||
<parameter name="create_source_clock" value="false" />
|
||||
<parameter name="create_source_clock_enable" value="false" />
|
||||
<parameter name="device_family" value="Cyclone IV E" />
|
||||
<parameter name="gui_use_auto_index" value="true" />
|
||||
<parameter name="instance_id" value="DBG2" />
|
||||
<parameter name="probe_width" value="24" />
|
||||
<parameter name="sld_instance_index" value="0" />
|
||||
<parameter name="source_initial_value" value="0" />
|
||||
<parameter name="source_width" value="0" />
|
||||
</module>
|
||||
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
|
||||
</system>
|
||||
|
|
@ -0,0 +1,256 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<EnsembleReport name="DEBUG2" kind="DEBUG2" version="1.0" fabric="QSYS">
|
||||
<!-- Format version 18.1 625 (Future versions may contain additional information.) -->
|
||||
<!-- 2021.03.31.22:16:46 -->
|
||||
<!-- A collection of modules and connections -->
|
||||
<parameter name="AUTO_GENERATION_ID">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>1617214606</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>GENERATION_ID</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_UNIQUE_ID">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>UNIQUE_ID</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE_FAMILY">
|
||||
<type>java.lang.String</type>
|
||||
<value>CYCLONEIVE</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE">
|
||||
<type>java.lang.String</type>
|
||||
<value>EP4CE10E22C8</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE">
|
||||
<type>java.lang.String</type>
|
||||
<value>8</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>Cyclone IV E</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<module
|
||||
name="in_system_sources_probes_0"
|
||||
kind="altera_in_system_sources_probes"
|
||||
version="18.1"
|
||||
path="in_system_sources_probes_0">
|
||||
<!-- Describes a single module. Module parameters are
|
||||
the requested settings for a module instance. -->
|
||||
<assignment>
|
||||
<name>embeddedsw.dts.group</name>
|
||||
<value>ignore</value>
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.dts.name</name>
|
||||
<value>debug</value>
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.dts.vendor</name>
|
||||
<value>altr</value>
|
||||
</assignment>
|
||||
<parameter name="device_family">
|
||||
<type>java.lang.String</type>
|
||||
<value>CYCLONEIVE</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="gui_use_auto_index">
|
||||
<type>boolean</type>
|
||||
<value>true</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="sld_auto_instance_index">
|
||||
<type>java.lang.String</type>
|
||||
<value>YES</value>
|
||||
<derived>true</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="sld_instance_index">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="instance_id">
|
||||
<type>java.lang.String</type>
|
||||
<value>DBG2</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="probe_width">
|
||||
<type>int</type>
|
||||
<value>24</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="source_width">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="source_initial_value">
|
||||
<type>java.lang.String</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="create_source_clock">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="create_source_clock_enable">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="enable_metastability">
|
||||
<type>java.lang.String</type>
|
||||
<value>NO</value>
|
||||
<derived>true</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<interface name="probes" kind="conduit_end" version="18.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="associatedClock">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="associatedReset">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>conduit</type>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>probe</name>
|
||||
<direction>Input</direction>
|
||||
<width>24</width>
|
||||
<role>probe</role>
|
||||
</port>
|
||||
</interface>
|
||||
</module>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>altera_in_system_sources_probes</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IModule</subtype>
|
||||
<displayName><![CDATA[Altera In-System Sources & Probes]]></displayName>
|
||||
<version>18.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>conduit_end</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
<displayName>Conduit</displayName>
|
||||
<version>18.1</version>
|
||||
</plugin>
|
||||
<reportVersion>18.1 625</reportVersion>
|
||||
<uniqueIdentifier></uniqueIdentifier>
|
||||
</EnsembleReport>
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 208 104)
|
||||
(text "DEBUG2" (rect 78 -1 116 11)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 88 20 100)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "probe[23..0]" (rect 0 0 47 12)(font "Arial" (font_size 8)))
|
||||
(text "probe[23..0]" (rect 4 61 76 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 80 72)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "probes" (rect 41 43 118 99)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "probe" (rect 85 67 200 144)(font "Arial" (color 0 0 0)))
|
||||
(text " DEBUG2 " (rect 166 88 380 186)(font "Arial" ))
|
||||
(line (pt 80 32)(pt 128 32)(line_width 1))
|
||||
(line (pt 128 32)(pt 128 88)(line_width 1))
|
||||
(line (pt 80 88)(pt 128 88)(line_width 1))
|
||||
(line (pt 80 32)(pt 80 88)(line_width 1))
|
||||
(line (pt 81 52)(pt 81 76)(line_width 1))
|
||||
(line (pt 82 52)(pt 82 76)(line_width 1))
|
||||
(line (pt 0 0)(pt 208 0)(line_width 1))
|
||||
(line (pt 208 0)(pt 208 104)(line_width 1))
|
||||
(line (pt 0 104)(pt 208 104)(line_width 1))
|
||||
(line (pt 0 0)(pt 0 104)(line_width 1))
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
component DEBUG2 is
|
||||
port (
|
||||
probe : in std_logic_vector(23 downto 0) := (others => 'X') -- probe
|
||||
);
|
||||
end component DEBUG2;
|
||||
|
||||
|
|
@ -0,0 +1,177 @@
|
|||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml">
|
||||
<head>
|
||||
<title>datasheet for DEBUG2</title>
|
||||
<style type="text/css">
|
||||
body { font-family:arial ;}
|
||||
a { text-decoration:underline ; color:#003000 ;}
|
||||
a:hover { text-decoration:underline ; color:0030f0 ;}
|
||||
td { padding : 5px ;}
|
||||
table.topTitle { width:100% ;}
|
||||
table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
|
||||
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
|
||||
table.blueBar { width : 100% ; border-spacing : 0px ;}
|
||||
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
|
||||
table.blueBar td.l { text-align : left ;}
|
||||
table.blueBar td.r { text-align : right ;}
|
||||
table.items { width:100% ; border-collapse:collapse ;}
|
||||
table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
|
||||
table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
|
||||
div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ; font-size:12px ;}
|
||||
body { font-family:arial ;}
|
||||
table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
|
||||
table.x td { border:1px solid #bbb ;}
|
||||
td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ;}
|
||||
table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
|
||||
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
|
||||
table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
|
||||
table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
|
||||
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
|
||||
table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
|
||||
table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
|
||||
table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
|
||||
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
|
||||
table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
|
||||
table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
|
||||
table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
|
||||
table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
|
||||
.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
|
||||
.flowbox { display:inline-block ;}
|
||||
.parametersbox table { font-size:10px ;}
|
||||
td.parametername { font-style:italic ;}
|
||||
td.parametervalue { font-weight:bold ;}
|
||||
div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
|
||||
</head>
|
||||
<body>
|
||||
<table class="topTitle">
|
||||
<tr>
|
||||
<td class="l">DEBUG2</td>
|
||||
<td class="r">
|
||||
<br/>
|
||||
<br/>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">2020.08.26.21:28:33</td>
|
||||
<td class="r">Datasheet</td>
|
||||
</tr>
|
||||
</table>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Overview</div>
|
||||
<div class="greydiv">
|
||||
<div style="display:inline-block ; text-align:left">
|
||||
<table class="connectionboxes">
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><span style="display:inline-block ; width:28px"> </span>
|
||||
<div style="display:inline-block ; text-align:left"><span>
|
||||
<br/></span>
|
||||
</div>
|
||||
</div>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Memory Map</div>
|
||||
<table class="mmap">
|
||||
<tr>
|
||||
<td class="empty" rowspan="2"></td>
|
||||
</tr>
|
||||
</table>
|
||||
<a name="module_in_system_sources_probes_0"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>in_system_sources_probes_0</h2>altera_in_system_sources_probes v18.1
|
||||
<br/>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">device_family</td>
|
||||
<td class="parametervalue">CYCLONEIVE</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">gui_use_auto_index</td>
|
||||
<td class="parametervalue">true</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">sld_auto_instance_index</td>
|
||||
<td class="parametervalue">YES</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">sld_instance_index</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">instance_id</td>
|
||||
<td class="parametervalue">DBG2</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">probe_width</td>
|
||||
<td class="parametervalue">24</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">source_width</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">source_initial_value</td>
|
||||
<td class="parametervalue">0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">create_source_clock</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">create_source_clock_enable</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">enable_metastability</td>
|
||||
<td class="parametervalue">NO</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">deviceFamily</td>
|
||||
<td class="parametervalue">UNKNOWN</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>(none)</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">generation took 0,01 seconds</td>
|
||||
<td class="r">rendering took 0,03 seconds</td>
|
||||
</tr>
|
||||
</table>
|
||||
</body>
|
||||
</html>
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<pinplan
|
||||
variation_name="in_system_sources_probes_0"
|
||||
megafunction_name="ALTERA_IN_SYSTEM_SOURCES_PROBES"
|
||||
intended_family="Cyclone IV E"
|
||||
specifies="all_ports">
|
||||
<global>
|
||||
<pin name="probe[23..0]" direction="input" scope="external" />
|
||||
</global>
|
||||
</pinplan>
|
||||
|
|
@ -0,0 +1,127 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<deploy
|
||||
date="2020.08.26.21:28:34"
|
||||
outputDirectory="D:/Dropbox/Develop/Projects/UA3REO/FPGA/DEBUG2/">
|
||||
<perimeter>
|
||||
<parameter
|
||||
name="AUTO_GENERATION_ID"
|
||||
type="Integer"
|
||||
defaultValue="0"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_UNIQUE_ID"
|
||||
type="String"
|
||||
defaultValue=""
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_FAMILY"
|
||||
type="String"
|
||||
defaultValue="Cyclone IV E"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE"
|
||||
type="String"
|
||||
defaultValue="EP4CE22E22C8"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_SPEEDGRADE"
|
||||
type="String"
|
||||
defaultValue="8"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<interface name="probes" kind="conduit" start="0">
|
||||
<property name="associatedClock" value="" />
|
||||
<property name="associatedReset" value="" />
|
||||
<port name="probe" direction="input" role="probe" width="24" />
|
||||
</interface>
|
||||
</perimeter>
|
||||
<entity
|
||||
path=""
|
||||
parameterizationKey="DEBUG2:1.0:AUTO_DEVICE=EP4CE22E22C8,AUTO_DEVICE_FAMILY=Cyclone IV E,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1598462913,AUTO_UNIQUE_ID=(altera_in_system_sources_probes:18.1:create_source_clock=false,create_source_clock_enable=false,device_family=Cyclone IV E,enable_metastability=NO,gui_use_auto_index=true,instance_id=DBG2,probe_width=24,sld_auto_instance_index=YES,sld_instance_index=0,source_initial_value=0,source_width=0)"
|
||||
instancePathKey="DEBUG2"
|
||||
kind="DEBUG2"
|
||||
version="1.0"
|
||||
name="DEBUG2">
|
||||
<parameter name="AUTO_GENERATION_ID" value="1598462913" />
|
||||
<parameter name="AUTO_DEVICE" value="EP4CE22E22C8" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
|
||||
<parameter name="AUTO_UNIQUE_ID" value="" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
|
||||
<generatedFiles>
|
||||
<file
|
||||
path="D:/Dropbox/Develop/Projects/UA3REO/FPGA/DEBUG2/synthesis/DEBUG2.v"
|
||||
type="VERILOG" />
|
||||
</generatedFiles>
|
||||
<childGeneratedFiles>
|
||||
<file
|
||||
path="D:/Dropbox/Develop/Projects/UA3REO/FPGA/DEBUG2/synthesis/submodules/altsource_probe_top.v"
|
||||
type="VERILOG"
|
||||
attributes="" />
|
||||
</childGeneratedFiles>
|
||||
<sourceFiles>
|
||||
<file path="D:/Dropbox/Develop/Projects/UA3REO/FPGA/DEBUG2.qsys" />
|
||||
</sourceFiles>
|
||||
<childSourceFiles>
|
||||
<file
|
||||
path="C:/intelfpga/18.1/ip/altera/sld/jtag/altera_in_system_sources_probes/altera_in_system_sources_probes_hw.tcl" />
|
||||
</childSourceFiles>
|
||||
<messages>
|
||||
<message level="Debug" culprit="DEBUG2">queue size: 0 starting:DEBUG2 "DEBUG2"</message>
|
||||
<message level="Progress" culprit="min"></message>
|
||||
<message level="Progress" culprit="max"></message>
|
||||
<message level="Progress" culprit="current"></message>
|
||||
<message level="Debug">Transform: CustomInstructionTransform</message>
|
||||
<message level="Debug">No custom instruction connections, skipping transform </message>
|
||||
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
|
||||
<message level="Debug">Transform: MMTransform</message>
|
||||
<message level="Debug">Transform: InterruptMapperTransform</message>
|
||||
<message level="Debug">Transform: InterruptSyncTransform</message>
|
||||
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
||||
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
||||
<message level="Debug">Transform: ResetAdaptation</message>
|
||||
<message level="Debug" culprit="DEBUG2"><![CDATA["<b>DEBUG2</b>" reuses <b>altera_in_system_sources_probes</b> "<b>submodules/altsource_probe_top</b>"]]></message>
|
||||
<message level="Debug" culprit="DEBUG2">queue size: 0 starting:altera_in_system_sources_probes "submodules/altsource_probe_top"</message>
|
||||
<message level="Info" culprit="in_system_sources_probes_0"><![CDATA["<b>DEBUG2</b>" instantiated <b>altera_in_system_sources_probes</b> "<b>in_system_sources_probes_0</b>"]]></message>
|
||||
</messages>
|
||||
</entity>
|
||||
<entity
|
||||
path="submodules/"
|
||||
parameterizationKey="altera_in_system_sources_probes:18.1:create_source_clock=false,create_source_clock_enable=false,device_family=Cyclone IV E,enable_metastability=NO,gui_use_auto_index=true,instance_id=DBG2,probe_width=24,sld_auto_instance_index=YES,sld_instance_index=0,source_initial_value=0,source_width=0"
|
||||
instancePathKey="DEBUG2:.:in_system_sources_probes_0"
|
||||
kind="altera_in_system_sources_probes"
|
||||
version="18.1"
|
||||
name="altsource_probe_top">
|
||||
<parameter name="create_source_clock" value="false" />
|
||||
<parameter name="instance_id" value="DBG2" />
|
||||
<parameter name="source_initial_value" value="0" />
|
||||
<parameter name="sld_auto_instance_index" value="YES" />
|
||||
<parameter name="sld_instance_index" value="0" />
|
||||
<parameter name="probe_width" value="24" />
|
||||
<parameter name="source_width" value="0" />
|
||||
<parameter name="create_source_clock_enable" value="false" />
|
||||
<parameter name="device_family" value="Cyclone IV E" />
|
||||
<parameter name="enable_metastability" value="NO" />
|
||||
<parameter name="gui_use_auto_index" value="true" />
|
||||
<generatedFiles>
|
||||
<file
|
||||
path="D:/Dropbox/Develop/Projects/UA3REO/FPGA/DEBUG2/synthesis/submodules/altsource_probe_top.v"
|
||||
type="VERILOG"
|
||||
attributes="" />
|
||||
</generatedFiles>
|
||||
<childGeneratedFiles/>
|
||||
<sourceFiles>
|
||||
<file
|
||||
path="C:/intelfpga/18.1/ip/altera/sld/jtag/altera_in_system_sources_probes/altera_in_system_sources_probes_hw.tcl" />
|
||||
</sourceFiles>
|
||||
<childSourceFiles/>
|
||||
<instantiator instantiator="DEBUG2" as="in_system_sources_probes_0" />
|
||||
<messages>
|
||||
<message level="Debug" culprit="DEBUG2">queue size: 0 starting:altera_in_system_sources_probes "submodules/altsource_probe_top"</message>
|
||||
<message level="Info" culprit="in_system_sources_probes_0"><![CDATA["<b>DEBUG2</b>" instantiated <b>altera_in_system_sources_probes</b> "<b>in_system_sources_probes_0</b>"]]></message>
|
||||
</messages>
|
||||
</entity>
|
||||
</deploy>
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
module DEBUG2 (
|
||||
probe);
|
||||
|
||||
input [23:0] probe;
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
Info: Starting: Create block symbol file (.bsf)
|
||||
Info: qsys-generate D:\Dropbox\Develop\Projects\UA3REO\FPGA\DEBUG2.qsys --block-symbol-file --output-directory=D:\Dropbox\Develop\Projects\UA3REO\FPGA\DEBUG2 --family="Cyclone IV E" --part=EP4CE22E22C8
|
||||
Progress: Loading FPGA/DEBUG2.qsys
|
||||
Progress: Reading input file
|
||||
Progress: Adding in_system_sources_probes_0 [altera_in_system_sources_probes 18.1]
|
||||
Progress: Parameterizing module in_system_sources_probes_0
|
||||
Progress: Building connections
|
||||
Progress: Parameterizing connections
|
||||
Progress: Validating
|
||||
Progress: Done reading input file
|
||||
Info: qsys-generate succeeded.
|
||||
Info: Finished: Create block symbol file (.bsf)
|
||||
Info:
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate D:\Dropbox\Develop\Projects\UA3REO\FPGA\DEBUG2.qsys --synthesis=VERILOG --output-directory=D:\Dropbox\Develop\Projects\UA3REO\FPGA\DEBUG2\synthesis --family="Cyclone IV E" --part=EP4CE22E22C8
|
||||
Progress: Loading FPGA/DEBUG2.qsys
|
||||
Progress: Reading input file
|
||||
Progress: Adding in_system_sources_probes_0 [altera_in_system_sources_probes 18.1]
|
||||
Progress: Parameterizing module in_system_sources_probes_0
|
||||
Progress: Building connections
|
||||
Progress: Parameterizing connections
|
||||
Progress: Validating
|
||||
Progress: Done reading input file
|
||||
Info: DEBUG2: Generating DEBUG2 "DEBUG2" for QUARTUS_SYNTH
|
||||
Info: in_system_sources_probes_0: "DEBUG2" instantiated altera_in_system_sources_probes "in_system_sources_probes_0"
|
||||
Info: DEBUG2: Done "DEBUG2" with 2 modules, 2 files
|
||||
Info: qsys-generate succeeded.
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
Info: Starting: Create block symbol file (.bsf)
|
||||
Info: qsys-generate D:\Dropbox\Develop\Projects\UA3REO\FPGA\DEBUG2.qsys --block-symbol-file --output-directory=D:\Dropbox\Develop\Projects\UA3REO\FPGA\DEBUG2 --family="Cyclone IV E" --part=EP4CE22E22C8
|
||||
Progress: Loading FPGA/DEBUG2.qsys
|
||||
Progress: Reading input file
|
||||
Progress: Adding in_system_sources_probes_0 [altera_in_system_sources_probes 18.1]
|
||||
Progress: Parameterizing module in_system_sources_probes_0
|
||||
Progress: Building connections
|
||||
Progress: Parameterizing connections
|
||||
Progress: Validating
|
||||
Progress: Done reading input file
|
||||
Info: qsys-generate succeeded.
|
||||
Info: Finished: Create block symbol file (.bsf)
|
||||
Info:
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate D:\Dropbox\Develop\Projects\UA3REO\FPGA\DEBUG2.qsys --synthesis=VERILOG --output-directory=D:\Dropbox\Develop\Projects\UA3REO\FPGA\DEBUG2\synthesis --family="Cyclone IV E" --part=EP4CE22E22C8
|
||||
Progress: Loading FPGA/DEBUG2.qsys
|
||||
Progress: Reading input file
|
||||
Progress: Adding in_system_sources_probes_0 [altera_in_system_sources_probes 18.1]
|
||||
Progress: Parameterizing module in_system_sources_probes_0
|
||||
Progress: Building connections
|
||||
Progress: Parameterizing connections
|
||||
Progress: Validating
|
||||
Progress: Done reading input file
|
||||
Info: DEBUG2: Generating DEBUG2 "DEBUG2" for QUARTUS_SYNTH
|
||||
Info: in_system_sources_probes_0: "DEBUG2" instantiated altera_in_system_sources_probes "in_system_sources_probes_0"
|
||||
Info: DEBUG2: Done "DEBUG2" with 2 modules, 2 files
|
||||
Info: qsys-generate succeeded.
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
DEBUG2 u0 (
|
||||
.probe (<connected-to-probe>) // probes.probe
|
||||
);
|
||||
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
component DEBUG2 is
|
||||
port (
|
||||
probe : in std_logic_vector(23 downto 0) := (others => 'X') -- probe
|
||||
);
|
||||
end component DEBUG2;
|
||||
|
||||
u0 : component DEBUG2
|
||||
port map (
|
||||
probe => CONNECTED_TO_probe -- probes.probe
|
||||
);
|
||||
|
||||
|
|
@ -0,0 +1,338 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<EnsembleReport name="DEBUG2" kind="system" version="18.1" fabric="QSYS">
|
||||
<!-- Format version 18.1 625 (Future versions may contain additional information.) -->
|
||||
<!-- 2020.08.26.21:28:34 -->
|
||||
<!-- A collection of modules and connections -->
|
||||
<parameter name="clockCrossingAdapter">
|
||||
<type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
|
||||
<value>HANDSHAKE</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="device">
|
||||
<type>java.lang.String</type>
|
||||
<value>EP4CE22E22C8</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>CYCLONEIVE</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceSpeedGrade">
|
||||
<type>java.lang.String</type>
|
||||
<value>8</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="fabricMode">
|
||||
<type>com.altera.sopcmodel.ensemble.Ensemble$EFabricMode</type>
|
||||
<value>QSYS</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generationId">
|
||||
<type>int</type>
|
||||
<value>1598462913</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="globalResetBus">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="hdlLanguage">
|
||||
<type>com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage</type>
|
||||
<value>VERILOG</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="hideFromIPCatalog">
|
||||
<type>boolean</type>
|
||||
<value>true</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="lockedInterfaceDefinition">
|
||||
<type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="maxAdditionalLatency">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="projectName">
|
||||
<type>java.lang.String</type>
|
||||
<value>UA3REO.qpf</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="sopcBorderPoints">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="systemHash">
|
||||
<type>long</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="testBenchDutName">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="timeStamp">
|
||||
<type>long</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="useTestBenchNamingPattern">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<module
|
||||
name="in_system_sources_probes_0"
|
||||
kind="altera_in_system_sources_probes"
|
||||
version="18.1"
|
||||
path="in_system_sources_probes_0">
|
||||
<!-- Describes a single module. Module parameters are
|
||||
the requested settings for a module instance. -->
|
||||
<assignment>
|
||||
<name>embeddedsw.dts.group</name>
|
||||
<value>ignore</value>
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.dts.name</name>
|
||||
<value>debug</value>
|
||||
</assignment>
|
||||
<assignment>
|
||||
<name>embeddedsw.dts.vendor</name>
|
||||
<value>altr</value>
|
||||
</assignment>
|
||||
<parameter name="device_family">
|
||||
<type>java.lang.String</type>
|
||||
<value>CYCLONEIVE</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="gui_use_auto_index">
|
||||
<type>boolean</type>
|
||||
<value>true</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="sld_auto_instance_index">
|
||||
<type>java.lang.String</type>
|
||||
<value>YES</value>
|
||||
<derived>true</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="sld_instance_index">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="instance_id">
|
||||
<type>java.lang.String</type>
|
||||
<value>DBG2</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="probe_width">
|
||||
<type>int</type>
|
||||
<value>24</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="source_width">
|
||||
<type>int</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="source_initial_value">
|
||||
<type>java.lang.String</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="create_source_clock">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="create_source_clock_enable">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="enable_metastability">
|
||||
<type>java.lang.String</type>
|
||||
<value>NO</value>
|
||||
<derived>true</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<interface name="probes" kind="conduit_end" version="18.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<parameter name="associatedClock">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="associatedReset">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>conduit</type>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>probe</name>
|
||||
<direction>Input</direction>
|
||||
<width>24</width>
|
||||
<role>probe</role>
|
||||
</port>
|
||||
</interface>
|
||||
</module>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>altera_in_system_sources_probes</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IModule</subtype>
|
||||
<displayName><![CDATA[Altera In-System Sources & Probes]]></displayName>
|
||||
<version>18.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>conduit_end</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
<displayName>Conduit</displayName>
|
||||
<version>18.1</version>
|
||||
</plugin>
|
||||
<reportVersion>18.1 625</reportVersion>
|
||||
<uniqueIdentifier>00FF00F87809000001742BD06E96</uniqueIdentifier>
|
||||
</EnsembleReport>
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_TOOL_NAME "Qsys"
|
||||
set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_TOOL_VERSION "18.1"
|
||||
set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -library "DEBUG2" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../DEBUG2.sopcinfo"]
|
||||
set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name SLD_INFO "QSYS_NAME DEBUG2 HAS_SOPCINFO 1 GENERATION_ID 1598462913"
|
||||
set_global_assignment -library "DEBUG2" -name MISC_FILE [file join $::quartus(qip_path) "../DEBUG2.cmp"]
|
||||
set_global_assignment -library "DEBUG2" -name SLD_FILE [file join $::quartus(qip_path) "DEBUG2.debuginfo"]
|
||||
set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_TARGETED_DEVICE_FAMILY "Cyclone IV E"
|
||||
set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
|
||||
set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_QSYS_MODE "STANDALONE"
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
set_global_assignment -library "DEBUG2" -name MISC_FILE [file join $::quartus(qip_path) "../../DEBUG2.qsys"]
|
||||
set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_COMPONENT_NAME "REVCVUcy"
|
||||
set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_COMPONENT_DISPLAY_NAME "REVCVUcy"
|
||||
set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
||||
set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_COMPONENT_VERSION "MS4w"
|
||||
set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTU5ODQ2MjkxMw==::QXV0byBHRU5FUkFUSU9OX0lE"
|
||||
set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
|
||||
set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UyMkUyMkM4::QXV0byBERVZJQ0U="
|
||||
set_global_assignment -entity "DEBUG2" -library "DEBUG2" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_NAME "YWx0c291cmNlX3Byb2JlX3RvcA=="
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIEluLVN5c3RlbSBTb3VyY2VzICYgUHJvYmVz"
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_VERSION "MTguMQ=="
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_DESCRIPTION "SW4tc3lzdGVtIHNvdXJjZXMgJiBwcm9iZXMgZGVidWdnaW5nIG1lZ2FmdW5jdGlvbi4gIFRoZSBJbi1TeXN0ZW0gU291cmNlcyBhbmQgUHJvYmVzIG1lZ2FmdW5jdGlvbiBpcwphdmFpbGFibGUgZm9yIGFsbCBBbHRlcmEgZGV2aWNlIGZhbWlsaWVzIHN1cHBvcnRlZCBieSB0aGUgUXVhcnR1cyBQcmltZSBzb2Z0d2FyZS4="
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBJViBF::ZGV2aWNlX2ZhbWlseQ=="
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9hdXRvX2luZGV4::dHJ1ZQ==::QXV0b21hdGljIEluc3RhbmNlIEluZGV4IEFzc2lnbm1lbnQ="
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_PARAMETER "c2xkX2F1dG9faW5zdGFuY2VfaW5kZXg=::WUVT::c2xkX2F1dG9faW5zdGFuY2VfaW5kZXg="
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_PARAMETER "aW5zdGFuY2VfaWQ=::REJHMg==::VGhlICdJbnN0YW5jZSBJRCcgb2YgdGhpcyBpbnN0YW5jZSAob3B0aW9uYWwp"
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_PARAMETER "cHJvYmVfd2lkdGg=::MjQ=::UHJvYmUgUG9ydCBXaWR0aCBbMC4uNTEyXQ=="
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_PARAMETER "c291cmNlX3dpZHRo::MA==::U291cmNlIFBvcnQgV2lkdGggWzAuLjUxMl0="
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_COMPONENT_PARAMETER "ZW5hYmxlX21ldGFzdGFiaWxpdHk=::Tk8=::ZW5hYmxlX21ldGFzdGFiaWxpdHk="
|
||||
|
||||
set_global_assignment -library "DEBUG2" -name VERILOG_FILE [file join $::quartus(qip_path) "DEBUG2.v"]
|
||||
set_global_assignment -library "DEBUG2" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altsource_probe_top.v"]
|
||||
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_TOOL_NAME "altera_in_system_sources_probes"
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_TOOL_VERSION "18.1"
|
||||
set_global_assignment -entity "altsource_probe_top" -library "DEBUG2" -name IP_TOOL_ENV "Qsys"
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
// DEBUG2.v
|
||||
|
||||
// Generated using ACDS version 18.1 625
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module DEBUG2 (
|
||||
input wire [23:0] probe // probes.probe
|
||||
);
|
||||
|
||||
altsource_probe_top #(
|
||||
.sld_auto_instance_index ("YES"),
|
||||
.sld_instance_index (0),
|
||||
.instance_id ("DBG2"),
|
||||
.probe_width (24),
|
||||
.source_width (0),
|
||||
.enable_metastability ("NO")
|
||||
) in_system_sources_probes_0 (
|
||||
.probe (probe) // probes.probe
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
// (C) 2001-2018 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
module altsource_probe_top
|
||||
#(
|
||||
parameter lpm_type = "altsource_probe", // required by the coding standard
|
||||
parameter lpm_hint = "UNUSED", // required by the coding standard
|
||||
|
||||
parameter sld_auto_instance_index = "YES", // Yes, if the instance index should be automatically assigned.
|
||||
parameter sld_instance_index = 0, // unique identifier for the altsource_probe instance.
|
||||
parameter sld_node_info_parameter = 4746752 + sld_instance_index, // The NODE ID to uniquely identify this node on the hub. Type ID: 9 Version: 0 Inst: 0 MFG ID 110 -- ***NOTE*** this parameter cannot be called SLD_NODE_INFO or Quartus Standard will think it's an ISSP impl.
|
||||
parameter sld_ir_width = 4,
|
||||
|
||||
parameter instance_id = "UNUSED", // optional name for the instance.
|
||||
parameter probe_width = 1, // probe port width
|
||||
parameter source_width= 1, // source port width
|
||||
parameter source_initial_value = "0", // initial source port value
|
||||
parameter enable_metastability = "NO" // yes to add two register
|
||||
)
|
||||
(
|
||||
input [probe_width - 1 : 0] probe, // probe inputs
|
||||
output [source_width - 1 : 0] source, // source outputs
|
||||
input source_clk, // clock of the registers used to metastabilize the source output
|
||||
input tri1 source_ena // enable of the registers used to metastabilize the source output
|
||||
);
|
||||
|
||||
altsource_probe #(
|
||||
.lpm_type(lpm_type),
|
||||
.lpm_hint(lpm_hint),
|
||||
.sld_auto_instance_index(sld_auto_instance_index),
|
||||
.sld_instance_index(sld_instance_index),
|
||||
.SLD_NODE_INFO(sld_node_info_parameter),
|
||||
.sld_ir_width(sld_ir_width),
|
||||
.instance_id(instance_id),
|
||||
.probe_width(probe_width),
|
||||
.source_width(source_width),
|
||||
.source_initial_value(source_initial_value),
|
||||
.enable_metastability(enable_metastability)
|
||||
)issp_impl
|
||||
(
|
||||
.probe(probe),
|
||||
.source(source),
|
||||
.source_clk(source_clk),
|
||||
.source_ena(source_ena)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
<session jtag_chain="USB-Blaster [USB-1]" jtag_device="@1: 10CL006(Y|Z)/10CL010(Y|Z)/.. (0x020F10DD)" sof_file="">
|
||||
<display_attributes is_max_probe_read_interval="1" is_write_immediate="1" probe_read_interval="1" probe_read_interval_units="s"/>
|
||||
<instance enable_logging="true" entity_name="ADC" is_auto_node="true" name="ADC">
|
||||
<node_ip_info instance_id="0" mfg_id="110" node_id="9" version="0"/>
|
||||
<sources/>
|
||||
<probes>
|
||||
<probe name="probe[0]"/>
|
||||
<probe name="probe[1]"/>
|
||||
<probe name="probe[2]"/>
|
||||
<probe name="probe[3]"/>
|
||||
<probe name="probe[4]"/>
|
||||
<probe name="probe[5]"/>
|
||||
<probe name="probe[6]"/>
|
||||
<probe name="probe[7]"/>
|
||||
<probe name="probe[8]"/>
|
||||
<probe name="probe[9]"/>
|
||||
<probe name="probe[10]"/>
|
||||
<probe name="probe[11]"/>
|
||||
</probes>
|
||||
<view>
|
||||
<view_node expanded="false" group_name="probe[11..0]" index="0" lsb_to_msb="false" node_type="probe" view_type="group_header"/>
|
||||
<view_node expanded="true" index="11" node_type="probe" view_type="group_member"/>
|
||||
<view_node expanded="true" index="10" node_type="probe" view_type="group_member"/>
|
||||
<view_node expanded="true" index="9" node_type="probe" view_type="group_member"/>
|
||||
<view_node expanded="true" index="8" node_type="probe" view_type="group_member"/>
|
||||
<view_node expanded="true" index="7" node_type="probe" view_type="group_member"/>
|
||||
<view_node expanded="true" index="6" node_type="probe" view_type="group_member"/>
|
||||
<view_node expanded="true" index="5" node_type="probe" view_type="group_member"/>
|
||||
<view_node expanded="true" index="4" node_type="probe" view_type="group_member"/>
|
||||
<view_node expanded="true" index="3" node_type="probe" view_type="group_member"/>
|
||||
<view_node expanded="true" index="2" node_type="probe" view_type="group_member"/>
|
||||
<view_node expanded="true" index="1" node_type="probe" view_type="group_member"/>
|
||||
<view_node expanded="true" index="0" node_type="probe" view_type="group_member"/>
|
||||
</view>
|
||||
<log data="220120020120220120220120" max_size="8" size="8" time="8DEA2CF5000000008DEA2CF5000000008DEA2CF5000000009DEA2CF5000000009DEA2CF5000000009DEA2CF5000000009DEA2CF5000000009DEA2CF500000000" width="12"/>
|
||||
</instance>
|
||||
</session>
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 0 0 240 168)
|
||||
(text "MAIN_PLL" (rect 89 0 162 16)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 152 25 164)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
|
||||
(text "inclk0" (rect 4 50 29 63)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 64)(pt 40 64))
|
||||
)
|
||||
(port
|
||||
(pt 240 64)
|
||||
(output)
|
||||
(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
|
||||
(text "c0" (rect 224 50 234 63)(font "Arial" (font_size 8)))
|
||||
)
|
||||
(port
|
||||
(pt 240 80)
|
||||
(output)
|
||||
(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
|
||||
(text "c1" (rect 224 66 232 79)(font "Arial" (font_size 8)))
|
||||
)
|
||||
(drawing
|
||||
(text "Cyclone IV E" (rect 164 152 383 315)(font "Arial" ))
|
||||
(text "inclk0 frequency: 61.440 MHz" (rect 50 59 223 129)(font "Arial" ))
|
||||
(text "Operation Mode: Normal" (rect 50 72 199 155)(font "Arial" ))
|
||||
(text "Clk " (rect 51 93 116 197)(font "Arial" ))
|
||||
(text "Ratio" (rect 75 93 170 197)(font "Arial" ))
|
||||
(text "Ph (dg)" (rect 104 93 237 197)(font "Arial" ))
|
||||
(text "DC (%)" (rect 138 93 306 197)(font "Arial" ))
|
||||
(text "c0" (rect 54 107 116 225)(font "Arial" ))
|
||||
(text "1/5" (rect 80 107 171 225)(font "Arial" ))
|
||||
(text "0.00" (rect 110 107 236 225)(font "Arial" ))
|
||||
(text "50.00" (rect 142 107 305 225)(font "Arial" ))
|
||||
(text "c1" (rect 54 121 115 253)(font "Arial" ))
|
||||
(text "1/1280" (rect 72 121 170 253)(font "Arial" ))
|
||||
(text "0.00" (rect 110 121 236 253)(font "Arial" ))
|
||||
(text "50.00" (rect 142 121 305 253)(font "Arial" ))
|
||||
(line (pt 0 0)(pt 241 0))
|
||||
(line (pt 241 0)(pt 241 169))
|
||||
(line (pt 0 169)(pt 241 169))
|
||||
(line (pt 0 0)(pt 0 169))
|
||||
(line (pt 48 91)(pt 170 91))
|
||||
(line (pt 48 104)(pt 170 104))
|
||||
(line (pt 48 118)(pt 170 118))
|
||||
(line (pt 48 132)(pt 170 132))
|
||||
(line (pt 48 91)(pt 48 132))
|
||||
(line (pt 69 91)(pt 69 132)(line_width 3))
|
||||
(line (pt 101 91)(pt 101 132)(line_width 3))
|
||||
(line (pt 135 91)(pt 135 132)(line_width 3))
|
||||
(line (pt 169 91)(pt 169 132))
|
||||
(line (pt 40 48)(pt 207 48))
|
||||
(line (pt 207 48)(pt 207 151))
|
||||
(line (pt 40 151)(pt 207 151))
|
||||
(line (pt 40 48)(pt 40 151))
|
||||
(line (pt 239 64)(pt 207 64))
|
||||
(line (pt 239 80)(pt 207 80))
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone IV E" variation_name="MAIN_PLL" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="c1" direction="output" scope="external" source="clock" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "18.1"
|
||||
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "MAIN_PLL.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "MAIN_PLL.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "MAIN_PLL.ppf"]
|
||||
|
|
@ -0,0 +1,329 @@
|
|||
// megafunction wizard: %ALTPLL%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: MAIN_PLL.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 18.1.0 Build 625 09/12/2018 SJ Standard Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
//Your use of Intel Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Intel Program License
|
||||
//Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
//the Intel FPGA IP License Agreement, or other applicable license
|
||||
//agreement, including, without limitation, that your use is for
|
||||
//the sole purpose of programming logic devices manufactured by
|
||||
//Intel and sold by Intel or its authorized distributors. Please
|
||||
//refer to the applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module MAIN_PLL (
|
||||
inclk0,
|
||||
c0,
|
||||
c1);
|
||||
|
||||
input inclk0;
|
||||
output c0;
|
||||
output c1;
|
||||
|
||||
wire [0:0] sub_wire2 = 1'h0;
|
||||
wire [4:0] sub_wire3;
|
||||
wire sub_wire0 = inclk0;
|
||||
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
|
||||
wire [1:1] sub_wire5 = sub_wire3[1:1];
|
||||
wire [0:0] sub_wire4 = sub_wire3[0:0];
|
||||
wire c0 = sub_wire4;
|
||||
wire c1 = sub_wire5;
|
||||
|
||||
altpll altpll_component (
|
||||
.inclk (sub_wire1),
|
||||
.clk (sub_wire3),
|
||||
.activeclock (),
|
||||
.areset (1'b0),
|
||||
.clkbad (),
|
||||
.clkena ({6{1'b1}}),
|
||||
.clkloss (),
|
||||
.clkswitch (1'b0),
|
||||
.configupdate (1'b0),
|
||||
.enable0 (),
|
||||
.enable1 (),
|
||||
.extclk (),
|
||||
.extclkena ({4{1'b1}}),
|
||||
.fbin (1'b1),
|
||||
.fbmimicbidir (),
|
||||
.fbout (),
|
||||
.fref (),
|
||||
.icdrclk (),
|
||||
.locked (),
|
||||
.pfdena (1'b1),
|
||||
.phasecounterselect ({4{1'b1}}),
|
||||
.phasedone (),
|
||||
.phasestep (1'b1),
|
||||
.phaseupdown (1'b1),
|
||||
.pllena (1'b1),
|
||||
.scanaclr (1'b0),
|
||||
.scanclk (1'b0),
|
||||
.scanclkena (1'b1),
|
||||
.scandata (1'b0),
|
||||
.scandataout (),
|
||||
.scandone (),
|
||||
.scanread (1'b0),
|
||||
.scanwrite (1'b0),
|
||||
.sclkout0 (),
|
||||
.sclkout1 (),
|
||||
.vcooverrange (),
|
||||
.vcounderrange ());
|
||||
defparam
|
||||
altpll_component.bandwidth_type = "AUTO",
|
||||
altpll_component.clk0_divide_by = 5,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 1,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.clk1_divide_by = 1280,
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.clk1_multiply_by = 1,
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 16276,
|
||||
altpll_component.intended_device_family = "Cyclone IV E",
|
||||
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=MAIN_PLL",
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.operation_mode = "NORMAL",
|
||||
altpll_component.pll_type = "AUTO",
|
||||
altpll_component.port_activeclock = "PORT_UNUSED",
|
||||
altpll_component.port_areset = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkloss = "PORT_UNUSED",
|
||||
altpll_component.port_clkswitch = "PORT_UNUSED",
|
||||
altpll_component.port_configupdate = "PORT_UNUSED",
|
||||
altpll_component.port_fbin = "PORT_UNUSED",
|
||||
altpll_component.port_inclk0 = "PORT_USED",
|
||||
altpll_component.port_inclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_locked = "PORT_UNUSED",
|
||||
altpll_component.port_pfdena = "PORT_UNUSED",
|
||||
altpll_component.port_phasecounterselect = "PORT_UNUSED",
|
||||
altpll_component.port_phasedone = "PORT_UNUSED",
|
||||
altpll_component.port_phasestep = "PORT_UNUSED",
|
||||
altpll_component.port_phaseupdown = "PORT_UNUSED",
|
||||
altpll_component.port_pllena = "PORT_UNUSED",
|
||||
altpll_component.port_scanaclr = "PORT_UNUSED",
|
||||
altpll_component.port_scanclk = "PORT_UNUSED",
|
||||
altpll_component.port_scanclkena = "PORT_UNUSED",
|
||||
altpll_component.port_scandata = "PORT_UNUSED",
|
||||
altpll_component.port_scandataout = "PORT_UNUSED",
|
||||
altpll_component.port_scandone = "PORT_UNUSED",
|
||||
altpll_component.port_scanread = "PORT_UNUSED",
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_USED",
|
||||
altpll_component.port_clk2 = "PORT_UNUSED",
|
||||
altpll_component.port_clk3 = "PORT_UNUSED",
|
||||
altpll_component.port_clk4 = "PORT_UNUSED",
|
||||
altpll_component.port_clk5 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena2 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena3 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena4 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena5 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk0 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk2 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk3 = "PORT_UNUSED",
|
||||
altpll_component.width_clock = 5;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1340"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1340"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "12.288000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.048000"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "61.440"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "256"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "12.28800000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.04800000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "MAIN_PLL.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1280"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "16276"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL MAIN_PLL.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL MAIN_PLL.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL MAIN_PLL.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL MAIN_PLL.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL MAIN_PLL.bsf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL MAIN_PLL_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL MAIN_PLL_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
// Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
set_time_format -unit ns -decimal_places 3
|
||||
|
||||
create_clock -name "clk_sys" -period 61.44MHz [get_ports {clk_sys}]
|
||||
create_clock -name "clock_stm32" -period 25MHz [get_ports {STM32_CLK}]
|
||||
create_clock -name "iq_valid" -period 48KHz {rx_ciccomp:RX1_CICOMP_Q|rx_ciccomp_0002:rx_ciccomp_inst|rx_ciccomp_0002_ast:rx_ciccomp_0002_ast_inst|auk_dspip_avalon_streaming_source_hpfir:source|data_valid}
|
||||
|
||||
set_clock_groups -asynchronous -group { clock_sys clock_stm32 iq_valid }
|
||||
|
||||
derive_clock_uncertainty
|
||||
|
||||
derive_pll_clocks -create_base_clocks
|
||||
|
||||
set_output_delay -clock clock_crystal -max 36ps [get_ports {DAC_OUTPUT[*]}]
|
||||
set_output_delay -clock clock_crystal -min 0ps [get_ports {DAC_OUTPUT[*]}]
|
||||
set_output_delay -clock clock_stm32 -max 36ps [get_ports {STM32_DATA_BUS[*]}]
|
||||
set_output_delay -clock clock_stm32 -min 0ps [get_ports {STM32_DATA_BUS[*]}]
|
||||
|
||||
set_input_delay -clock clock_adc -max 36ps [get_ports ADC_INPUT[*]]
|
||||
set_input_delay -clock clock_adc -min 0ps [get_ports ADC_INPUT[*]]
|
||||
set_input_delay -clock clock_adc -max 36ps [get_ports ADC_OTR]
|
||||
set_input_delay -clock clock_adc -min 0ps [get_ports ADC_OTR]
|
||||
set_input_delay -clock clock_stm32 -max 36ps [get_ports STM32_DATA_BUS[*]]
|
||||
set_input_delay -clock clock_stm32 -min 0ps [get_ports STM32_DATA_BUS[*]]
|
||||
set_input_delay -clock clock_stm32 -max 36ps [get_ports STM32_SYNC]
|
||||
set_input_delay -clock clock_stm32 -min 0ps [get_ports STM32_SYNC]
|
||||
|
||||
set_multicycle_path -from [get_clocks {clock_stm32}] -to [get_clocks {iq_valid}] -setup -end 2
|
||||
set_multicycle_path -from [get_clocks {clock_stm32}] -to [get_clocks {iq_valid}] -hold -end 2
|
||||
set_multicycle_path -from [get_clocks {iq_valid}] -to [get_clocks {clock_stm32}] -setup -end 2
|
||||
set_multicycle_path -from [get_clocks {iq_valid}] -to [get_clocks {clock_stm32}] -hold -end 2
|
||||
set_multicycle_path -from [get_clocks {clock_stm32}] -to [get_clocks {clock_sys}] -setup -end 2
|
||||
set_multicycle_path -from [get_clocks {clock_stm32}] -to [get_clocks {clock_sys}] -hold -end 2
|
||||
Plik diff jest za duży
Load Diff
|
|
@ -0,0 +1,32 @@
|
|||
<?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
|
||||
<cof>
|
||||
<eprom_name>EPCS16</eprom_name>
|
||||
<flash_loader_device>EP4CE10E22</flash_loader_device>
|
||||
<output_filename>output_files/WOLF-LITE.jic</output_filename>
|
||||
<n_pages>1</n_pages>
|
||||
<width>1</width>
|
||||
<mode>7</mode>
|
||||
<sof_data>
|
||||
<user_name>Page_0</user_name>
|
||||
<page_flags>1</page_flags>
|
||||
<bit0>
|
||||
<sof_filename>output_files/WOLF-LITE.sof</sof_filename>
|
||||
</bit0>
|
||||
</sof_data>
|
||||
<version>10</version>
|
||||
<create_cvp_file>0</create_cvp_file>
|
||||
<create_hps_iocsr>0</create_hps_iocsr>
|
||||
<auto_create_rpd>0</auto_create_rpd>
|
||||
<rpd_little_endian>1</rpd_little_endian>
|
||||
<options>
|
||||
<map_file>1</map_file>
|
||||
</options>
|
||||
<advanced_options>
|
||||
<ignore_epcs_id_check>1</ignore_epcs_id_check>
|
||||
<ignore_condone_check>1</ignore_condone_check>
|
||||
<plc_adjustment>0</plc_adjustment>
|
||||
<post_chain_bitstream_pad_bytes>-1</post_chain_bitstream_pad_bytes>
|
||||
<post_device_bitstream_pad_bytes>-1</post_device_bitstream_pad_bytes>
|
||||
<bitslice_pre_padding>1</bitslice_pre_padding>
|
||||
</advanced_options>
|
||||
</cof>
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition
|
||||
# Date created = 10:13:04 December 04, 2020
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "18.1"
|
||||
DATE = "10:13:04 December 04, 2020"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "WOLF-LITE"
|
||||
PROJECT_REVISION = "WOLF-LITE"
|
||||
|
|
@ -0,0 +1,324 @@
|
|||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
|
||||
# Date created = 17:58:56 March 31, 2018
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# UA3REO_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus Prime software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone IV E"
|
||||
set_global_assignment -name DEVICE EP4CE10E22C8
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY "WOLF-LITE"
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:58:56 MARCH 31, 2018"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||
|
||||
|
||||
|
||||
set_global_assignment -name ENABLE_LOGIC_ANALYZER_INTERFACE OFF
|
||||
set_global_assignment -name USE_LOGIC_ANALYZER_INTERFACE_FILE debugger1.lai
|
||||
set_global_assignment -name ENABLE_SIGNALTAP OFF
|
||||
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS16
|
||||
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
|
||||
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
|
||||
set_global_assignment -name ENABLE_OCT_DONE OFF
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name PROJECT_IP_REGENERATION_POLICY ALWAYS_REGENERATE_IP
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
|
||||
set_global_assignment -name SMART_RECOMPILE ON
|
||||
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
|
||||
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER OFF
|
||||
set_location_assignment PIN_52 -to ADC_INPUT[11]
|
||||
set_location_assignment PIN_53 -to ADC_INPUT[10]
|
||||
set_location_assignment PIN_54 -to ADC_INPUT[9]
|
||||
set_location_assignment PIN_55 -to ADC_INPUT[8]
|
||||
set_location_assignment PIN_58 -to ADC_INPUT[7]
|
||||
set_location_assignment PIN_59 -to ADC_INPUT[6]
|
||||
set_location_assignment PIN_60 -to ADC_INPUT[5]
|
||||
set_location_assignment PIN_64 -to ADC_INPUT[4]
|
||||
set_location_assignment PIN_65 -to ADC_INPUT[3]
|
||||
set_location_assignment PIN_66 -to ADC_INPUT[2]
|
||||
set_location_assignment PIN_67 -to ADC_INPUT[1]
|
||||
set_location_assignment PIN_68 -to ADC_INPUT[0]
|
||||
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 2.5V
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS OUTPUT DRIVING GROUND"
|
||||
set_global_assignment -name ENABLE_DRC_SETTINGS OFF
|
||||
set_global_assignment -name AUTO_MERGE_PLLS ON
|
||||
set_location_assignment PIN_69 -to PREAMP
|
||||
set_location_assignment PIN_44 -to ADC_OTR
|
||||
set_global_assignment -name SAVE_DISK_SPACE OFF
|
||||
set_global_assignment -name OCP_HW_EVAL DISABLE
|
||||
set_location_assignment PIN_33 -to STM32_CLK
|
||||
set_location_assignment PIN_32 -to STM32_SYNC
|
||||
set_location_assignment PIN_101 -to DAC_OUTPUT[0]
|
||||
set_location_assignment PIN_103 -to DAC_OUTPUT[1]
|
||||
set_location_assignment PIN_104 -to DAC_OUTPUT[2]
|
||||
set_location_assignment PIN_105 -to DAC_OUTPUT[3]
|
||||
set_location_assignment PIN_106 -to DAC_OUTPUT[4]
|
||||
set_location_assignment PIN_110 -to DAC_OUTPUT[5]
|
||||
set_location_assignment PIN_111 -to DAC_OUTPUT[6]
|
||||
set_location_assignment PIN_112 -to DAC_OUTPUT[7]
|
||||
set_location_assignment PIN_113 -to DAC_OUTPUT[8]
|
||||
set_location_assignment PIN_114 -to DAC_OUTPUT[9]
|
||||
set_location_assignment PIN_115 -to DAC_OUTPUT[10]
|
||||
set_location_assignment PIN_119 -to DAC_OUTPUT[11]
|
||||
set_location_assignment PIN_120 -to DAC_OUTPUT[12]
|
||||
set_location_assignment PIN_121 -to DAC_OUTPUT[13]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS OFF
|
||||
set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
|
||||
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION ON
|
||||
|
||||
set_location_assignment PIN_136 -to AUDIO_I2S_CLOCK
|
||||
set_location_assignment PIN_135 -to AUDIO_48K_CLOCK
|
||||
|
||||
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
|
||||
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "80 %"
|
||||
set_location_assignment PIN_49 -to STM32_DATA_BUS[0]
|
||||
set_location_assignment PIN_50 -to STM32_DATA_BUS[1]
|
||||
set_location_assignment PIN_51 -to STM32_DATA_BUS[2]
|
||||
set_location_assignment PIN_38 -to STM32_DATA_BUS[3]
|
||||
set_location_assignment PIN_39 -to STM32_DATA_BUS[4]
|
||||
set_location_assignment PIN_42 -to STM32_DATA_BUS[5]
|
||||
set_location_assignment PIN_43 -to STM32_DATA_BUS[6]
|
||||
set_location_assignment PIN_46 -to STM32_DATA_BUS[7]
|
||||
set_location_assignment PIN_8 -to FLASH_S
|
||||
set_location_assignment PIN_12 -to FLASH_C
|
||||
set_location_assignment PIN_13 -to FLASH_MISO
|
||||
set_location_assignment PIN_6 -to FLASH_MOSI
|
||||
set_global_assignment -name ALLOW_REGISTER_RETIMING OFF
|
||||
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS MAXIMUM
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
|
||||
set_location_assignment PIN_124 -to DAC_PD
|
||||
|
||||
set_global_assignment -name POST_FLOW_SCRIPT_FILE "quartus_sh:auto_convert.tcl"
|
||||
|
||||
set_global_assignment -name POWER_USE_PVA ON
|
||||
set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
|
||||
set_global_assignment -name POWER_OUTPUT_SAF_NAME output_files/signal_activity.saf
|
||||
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY ON
|
||||
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION ON
|
||||
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
|
||||
set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
|
||||
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
|
||||
set_global_assignment -name OPTIMIZE_SSN "NORMAL COMPILATION"
|
||||
set_global_assignment -name WEAK_PULL_UP_RESISTOR OFF
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
|
||||
|
||||
|
||||
set_location_assignment PIN_125 -to DAC_CLK
|
||||
set_location_assignment PIN_89 -to clk_sys
|
||||
set_location_assignment PIN_87 -to ATT_1
|
||||
set_location_assignment PIN_98 -to ATT_2
|
||||
set_location_assignment PIN_86 -to ATT_05
|
||||
set_location_assignment PIN_99 -to ATT_4
|
||||
set_location_assignment PIN_100 -to ATT_8
|
||||
set_location_assignment PIN_85 -to ATT_16
|
||||
set_location_assignment PIN_80 -to BPF_A
|
||||
set_location_assignment PIN_83 -to BPF_B
|
||||
set_location_assignment PIN_77 -to BPF_OE1
|
||||
set_location_assignment PIN_84 -to BPF_OE2
|
||||
set_location_assignment PIN_76 -to LPF_1
|
||||
set_location_assignment PIN_75 -to LPF_2
|
||||
set_location_assignment PIN_74 -to LPF_3
|
||||
set_location_assignment PIN_72 -to TXRX_OUT
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE POST_FIT -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_INPUT[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_INPUT[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_INPUT[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_INPUT[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_INPUT[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_INPUT[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_INPUT[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_INPUT[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_INPUT[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_INPUT[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_INPUT[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_INPUT[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PREAMP
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_OUTPUT[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_OUTPUT[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_OUTPUT[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_OUTPUT[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to STM32_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to STM32_SYNC
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_OTR
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_I2S_CLOCK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_48K_CLOCK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to STM32_DATA_BUS[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to STM32_DATA_BUS[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to STM32_DATA_BUS[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to STM32_DATA_BUS[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to STM32_DATA_BUS[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to STM32_DATA_BUS[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to STM32_DATA_BUS[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to STM32_DATA_BUS[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_OUTPUT[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_PD
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to FLASH_C
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to FLASH_MISO
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to FLASH_MOSI
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to FLASH_S
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ADC_INPUT[7]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ADC_INPUT[6]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ADC_INPUT[5]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ADC_INPUT[4]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ADC_INPUT[3]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ADC_INPUT[2]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ADC_INPUT[1]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ADC_INPUT[0]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ADC_OTR
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to AUDIO_48K_CLOCK
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to AUDIO_I2S_CLOCK
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to DAC_OUTPUT[13]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to DAC_OUTPUT[12]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to DAC_OUTPUT[11]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to DAC_OUTPUT[10]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to DAC_OUTPUT[9]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to DAC_OUTPUT[8]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to DAC_OUTPUT[7]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to DAC_OUTPUT[6]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to DAC_OUTPUT[5]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to DAC_OUTPUT[4]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to DAC_OUTPUT[3]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to DAC_OUTPUT[2]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to DAC_OUTPUT[1]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to DAC_OUTPUT[0]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to DAC_PD
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PREAMP
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to STM32_CLK
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to STM32_DATA_BUS[7]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to STM32_DATA_BUS[6]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to STM32_DATA_BUS[5]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to STM32_DATA_BUS[4]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to STM32_DATA_BUS[3]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to STM32_DATA_BUS[2]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to STM32_DATA_BUS[1]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to STM32_DATA_BUS[0]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to STM32_SYNC
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_OUTPUT[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_OUTPUT[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_OUTPUT[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_OUTPUT[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_OUTPUT[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_OUTPUT[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_OUTPUT[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_OUTPUT[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_OUTPUT[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_OUTPUT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DAC_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_sys
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ATT_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ATT_2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ATT_4
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ATT_05
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ATT_8
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ATT_16
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BPF_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BPF_B
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BPF_OE1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BPF_OE2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LPF_2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LPF_3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LPF_1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TXRX_OUT
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
|
||||
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
|
||||
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
|
||||
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
|
||||
set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
|
||||
set_global_assignment -name MUX_RESTRUCTURE OFF
|
||||
set_global_assignment -name BDF_FILE "WOLF-LITE.bdf"
|
||||
set_global_assignment -name VERILOG_FILE DAC_corrector.v
|
||||
set_global_assignment -name VERILOG_FILE spi_interface.v
|
||||
set_global_assignment -name VERILOG_FILE stm32_interface.v
|
||||
set_global_assignment -name VERILOG_FILE data_shifter.v
|
||||
set_global_assignment -name VERILOG_FILE vcxo_controller.v -hdl_version Verilog_2001
|
||||
set_global_assignment -name SOURCE_FILE Debug_Probes.spf
|
||||
set_global_assignment -name QIP_FILE mixer.qip
|
||||
set_global_assignment -name SDC_FILE SDC.sdc
|
||||
set_global_assignment -name QSYS_FILE clock_buffer.qsys
|
||||
set_global_assignment -name QSYS_FILE rx_cic.qsys
|
||||
set_global_assignment -name QSYS_FILE tx_cic.qsys
|
||||
set_global_assignment -name QSYS_FILE tx_nco.qsys
|
||||
set_global_assignment -name QSYS_FILE nco.qsys
|
||||
set_global_assignment -name QSYS_FILE DEBUG.qsys
|
||||
set_global_assignment -name QSYS_FILE DEBUG2.qsys
|
||||
set_global_assignment -name SOURCE_FILE rx_ciccomp.cmp
|
||||
set_global_assignment -name SOURCE_FILE tx_ciccomp.cmp
|
||||
set_global_assignment -name QIP_FILE mux16.qip
|
||||
set_global_assignment -name QIP_FILE MAIN_PLL.qip
|
||||
set_global_assignment -name QIP_FILE mux14.qip
|
||||
set_global_assignment -name QIP_FILE mux1.qip
|
||||
set_global_assignment -name QIP_FILE tx_mixer.qip
|
||||
set_global_assignment -name QIP_FILE tx_summator.qip
|
||||
set_global_assignment -name QIP_FILE ADC_Latch.qip
|
||||
set_global_assignment -name QIP_FILE dac_null.qip
|
||||
set_global_assignment -name QIP_FILE rx_ciccomp.qip
|
||||
set_global_assignment -name SIP_FILE rx_ciccomp.sip
|
||||
set_global_assignment -name QIP_FILE tx_ciccomp.qip
|
||||
set_global_assignment -name SIP_FILE tx_ciccomp.sip
|
||||
set_global_assignment -name QIP_FILE diffclock_buff.qip
|
||||
set_global_assignment -name QIP_FILE dcdc_pll.qip
|
||||
set_global_assignment -name QIP_FILE tx_pll.qip
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
Plik binarny nie jest wyświetlany.
|
|
@ -0,0 +1,39 @@
|
|||
{ "" "" "" "Verilog HDL assignment warning at tx_ciccomp.v(381): truncated value with size 33 to match size of target (32)" { } { } 0 10230 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Verilog HDL assignment warning at ciccomp.v(529): truncated value with size 30 to match size of target (16)" { } { } 0 10230 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Timing requirements not met" { } { } 0 332148 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Port \"counter_max\" on the entity instantiation of \"latency_cnt_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 4. The extra bits will be ignored." { } { } 0 12020 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Port \"counter_max\" on the entity instantiation of \"counter_fs_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 10. The extra bits will be ignored." { } { } 0 12020 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Port \"counter_max\" on the entity instantiation of \"counter_ch_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 1. The extra bits will be ignored." { } { } 0 12020 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Port \"counter_max\" on the entity instantiation of \"counter_fs_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 9. The extra bits will be ignored." { } { } 0 12020 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Port \"counter_max\" on the entity instantiation of \"rate_cnt_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 9. The extra bits will be ignored." { } { } 0 12020 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Port \"counter_max\" on the entity instantiation of \"channel_out_int_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 2. The extra bits will be ignored." { } { } 0 12020 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Verilog HDL assignment warning at tx_ciccomp.v(417): truncated value with size 30 to match size of target (16)" { } { } 0 10230 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Synthesized away the following node(s):" { } { } 0 14284 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Previously generated Fitter netlist for partition \"Top\" is older than current Synthesis netlist -- using the current Synthesis netlist instead to ensure that the latest source changes are included" { } { } 0 35010 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example." { } { } 0 18550 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "15 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "19 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { } { } 0 169177 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "PLL \"MAIN_PLL:main_pll\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1\" input clock inclk\[0\] is not fully compensated because it is fed by a remote clock pin \"Pin_23\"" { } { } 0 176598 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "PLL \"MAIN_PLL:main_pll\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1\" output port clk\[0\] feeds output pin \"ADC_DAC_CLK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" { } { } 0 15064 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "PLL \"SECOND_PLL:second_pll\|altpll:altpll_component\|SECOND_PLL_altpll:auto_generated\|pll1\" input clock inclk\[0\] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input" { } { } 0 15055 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Verilog HDL assignment warning at ciccomp.v(905): truncated value with size 30 to match size of target (16)" { } { } 0 10230 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Verilog HDL assignment warning at rx_ciccomp.v(1136): truncated value with size 30 to match size of target (16)" { } { } 0 10230 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Verilog HDL assignment warning at tx_ciccomp.v(741): truncated value with size 29 to match size of target (16)" { } { } 0 10230 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Port \"counter_max\" on the entity instantiation of \"rate_cnt_inst\" is connected to a signal of width 32. The formal width of the signal in the module is 10. The extra bits will be ignored." { } { } 0 12020 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Verilog HDL assignment warning at rx_ciccomp.v(905): truncated value with size 30 to match size of target (16)" { } { } 0 10230 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Verilog HDL assignment warning at tx_ciccomp.v(657): truncated value with size 29 to match size of target (16)" { } { } 0 10230 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "PLL \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1\" output port clk\[1\] feeds output pin \"AUDIO_CLOCK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" { } { } 0 15064 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Verilog HDL assignment warning at rx_ciccomp.v(585): truncated value with size 31 to match size of target (16)" { } { } 0 10230 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Verilog HDL assignment warning at shifter_iq_single.v(14): truncated value with size 32 to match size of target (14)" { } { } 0 10230 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "Verilog HDL assignment warning at tx_ciccomp.v(387): truncated value with size 30 to match size of target (16)" { } { } 0 10230 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "PLL \"MAIN_PLL:MAIN_PLL\|altpll:altpll_component\|MAIN_PLL_altpll:auto_generated\|pll1\" output port clk\[2\] feeds output pin \"AUDIO_48K_CLOCK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" { } { } 0 15064 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 169177 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 332060 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 171167 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 222013 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 10273 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 169180 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 12020 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 10541 "" 0 0 "Design Software" 0 -1 0 ""}
|
||||
|
|
@ -0,0 +1 @@
|
|||
open
|
||||
|
|
@ -0,0 +1,807 @@
|
|||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition
|
||||
# Date created = 12:36:37 March 04, 2019
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Note:
|
||||
#
|
||||
# 1) Do not modify this file. This file was generated
|
||||
# automatically by the Quartus Prime software and is used
|
||||
# to preserve global assignments across Quartus Prime versions.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
|
||||
set_global_assignment -name IP_COMPONENT_INTERNAL Off
|
||||
set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
|
||||
set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
|
||||
set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
|
||||
set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
|
||||
set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
|
||||
set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
|
||||
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
|
||||
set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
|
||||
set_global_assignment -name HC_OUTPUT_DIR hc_output
|
||||
set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
|
||||
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
|
||||
set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
|
||||
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
|
||||
set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
|
||||
set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
|
||||
set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
|
||||
set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
|
||||
set_global_assignment -name REVISION_TYPE Base -family "Arria V"
|
||||
set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
|
||||
set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
|
||||
set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
|
||||
set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
|
||||
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
|
||||
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
|
||||
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
|
||||
set_global_assignment -name DO_COMBINED_ANALYSIS Off
|
||||
set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
|
||||
set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
|
||||
set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
|
||||
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
|
||||
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V"
|
||||
set_global_assignment -name OPTIMIZATION_MODE Balanced
|
||||
set_global_assignment -name ALLOW_REGISTER_MERGING On
|
||||
set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V"
|
||||
set_global_assignment -name MUX_RESTRUCTURE Auto
|
||||
set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
|
||||
set_global_assignment -name ENABLE_IP_DEBUG Off
|
||||
set_global_assignment -name SAVE_DISK_SPACE On
|
||||
set_global_assignment -name OCP_HW_EVAL Enable
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE Any
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
|
||||
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
|
||||
set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
|
||||
set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
|
||||
set_global_assignment -name FAMILY "Cyclone V"
|
||||
set_global_assignment -name TRUE_WYSIWYG_FLOW Off
|
||||
set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
|
||||
set_global_assignment -name STATE_MACHINE_PROCESSING Auto
|
||||
set_global_assignment -name SAFE_STATE_MACHINE Off
|
||||
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
|
||||
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
|
||||
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
|
||||
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
|
||||
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
|
||||
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
|
||||
set_global_assignment -name PARALLEL_SYNTHESIS On
|
||||
set_global_assignment -name DSP_BLOCK_BALANCING Auto
|
||||
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
|
||||
set_global_assignment -name NOT_GATE_PUSH_BACK On
|
||||
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
|
||||
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
|
||||
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
|
||||
set_global_assignment -name IGNORE_CARRY_BUFFERS Off
|
||||
set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
|
||||
set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
|
||||
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
|
||||
set_global_assignment -name IGNORE_LCELL_BUFFERS Off
|
||||
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
|
||||
set_global_assignment -name IGNORE_SOFT_BUFFERS On
|
||||
set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
|
||||
set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
|
||||
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
|
||||
set_global_assignment -name AUTO_GLOBAL_OE_MAX On
|
||||
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
|
||||
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
|
||||
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
|
||||
set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
|
||||
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
|
||||
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
|
||||
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
|
||||
set_global_assignment -name ALLOW_XOR_GATE_USAGE On
|
||||
set_global_assignment -name AUTO_LCELL_INSERTION On
|
||||
set_global_assignment -name CARRY_CHAIN_LENGTH 48
|
||||
set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
|
||||
set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
|
||||
set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
|
||||
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
|
||||
set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
|
||||
set_global_assignment -name CASCADE_CHAIN_LENGTH 2
|
||||
set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
|
||||
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
|
||||
set_global_assignment -name AUTO_CARRY_CHAINS On
|
||||
set_global_assignment -name AUTO_CASCADE_CHAINS On
|
||||
set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
|
||||
set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
|
||||
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
|
||||
set_global_assignment -name AUTO_ROM_RECOGNITION On
|
||||
set_global_assignment -name AUTO_RAM_RECOGNITION On
|
||||
set_global_assignment -name AUTO_DSP_RECOGNITION On
|
||||
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
|
||||
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
|
||||
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
|
||||
set_global_assignment -name STRICT_RAM_RECOGNITION Off
|
||||
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
|
||||
set_global_assignment -name FORCE_SYNCH_CLEAR Off
|
||||
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
|
||||
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
|
||||
set_global_assignment -name AUTO_RESOURCE_SHARING Off
|
||||
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
|
||||
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
|
||||
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
|
||||
set_global_assignment -name MAX7000_FANIN_PER_CELL 100
|
||||
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
|
||||
set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
|
||||
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
|
||||
set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
|
||||
set_global_assignment -name REPORT_PARAMETER_SETTINGS On
|
||||
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
|
||||
set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
|
||||
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
|
||||
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
|
||||
set_global_assignment -name HDL_MESSAGE_LEVEL Level2
|
||||
set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
|
||||
set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
|
||||
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
|
||||
set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
|
||||
set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
|
||||
set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
|
||||
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
|
||||
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
|
||||
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
|
||||
set_global_assignment -name BLOCK_DESIGN_NAMING Auto
|
||||
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
|
||||
set_global_assignment -name SYNTHESIS_EFFORT Auto
|
||||
set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
|
||||
set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
|
||||
set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
|
||||
set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
|
||||
set_global_assignment -name MAX_LABS "-1 (Unlimited)"
|
||||
set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
|
||||
set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
|
||||
set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
|
||||
set_global_assignment -name PRPOF_ID Off
|
||||
set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
|
||||
set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
|
||||
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
|
||||
set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
|
||||
set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
|
||||
set_global_assignment -name AUTO_MERGE_PLLS On
|
||||
set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
|
||||
set_global_assignment -name TXPMA_SLEW_RATE Low
|
||||
set_global_assignment -name ADCE_ENABLED Auto
|
||||
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
|
||||
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
|
||||
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
|
||||
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
|
||||
set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS Off
|
||||
set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
|
||||
set_global_assignment -name DEVICE AUTO
|
||||
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
|
||||
set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
|
||||
set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
|
||||
set_global_assignment -name ENABLE_NCEO_OUTPUT Off
|
||||
set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
|
||||
set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
|
||||
set_global_assignment -name STRATIX_UPDATE_MODE Standard
|
||||
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
|
||||
set_global_assignment -name CVP_MODE Off
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
|
||||
set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
|
||||
set_global_assignment -name USE_CONF_DONE AUTO
|
||||
set_global_assignment -name USE_PWRMGT_SCL AUTO
|
||||
set_global_assignment -name USE_PWRMGT_SDA AUTO
|
||||
set_global_assignment -name USE_PWRMGT_ALERT AUTO
|
||||
set_global_assignment -name USE_INIT_DONE AUTO
|
||||
set_global_assignment -name USE_CVP_CONFDONE AUTO
|
||||
set_global_assignment -name USE_SEU_ERROR AUTO
|
||||
set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
|
||||
set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
|
||||
set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
|
||||
set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name USER_START_UP_CLOCK Off
|
||||
set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
|
||||
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
|
||||
set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
|
||||
set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
|
||||
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
|
||||
set_global_assignment -name ENABLE_VREFA_PIN Off
|
||||
set_global_assignment -name ENABLE_VREFB_PIN Off
|
||||
set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
|
||||
set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
|
||||
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
|
||||
set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
|
||||
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
|
||||
set_global_assignment -name INIT_DONE_OPEN_DRAIN On
|
||||
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
|
||||
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
|
||||
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
|
||||
set_global_assignment -name ENABLE_CONFIGURATION_PINS On
|
||||
set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
|
||||
set_global_assignment -name ENABLE_NCE_PIN Off
|
||||
set_global_assignment -name ENABLE_BOOT_SEL_PIN On
|
||||
set_global_assignment -name CRC_ERROR_CHECKING Off
|
||||
set_global_assignment -name INTERNAL_SCRUBBING Off
|
||||
set_global_assignment -name PR_ERROR_OPEN_DRAIN On
|
||||
set_global_assignment -name PR_READY_OPEN_DRAIN On
|
||||
set_global_assignment -name ENABLE_CVP_CONFDONE Off
|
||||
set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
|
||||
set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
|
||||
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
|
||||
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
|
||||
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
|
||||
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
|
||||
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
|
||||
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
|
||||
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
|
||||
set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
|
||||
set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
|
||||
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
|
||||
set_global_assignment -name OPTIMIZE_SSN Off
|
||||
set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
|
||||
set_global_assignment -name ECO_OPTIMIZE_TIMING Off
|
||||
set_global_assignment -name ECO_REGENERATE_REPORT Off
|
||||
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
|
||||
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
|
||||
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
|
||||
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
|
||||
set_global_assignment -name SEED 1
|
||||
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
|
||||
set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
|
||||
set_global_assignment -name SLOW_SLEW_RATE Off
|
||||
set_global_assignment -name PCI_IO Off
|
||||
set_global_assignment -name TURBO_BIT On
|
||||
set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
|
||||
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
|
||||
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
|
||||
set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
|
||||
set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
|
||||
set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
|
||||
set_global_assignment -name NORMAL_LCELL_INSERT On
|
||||
set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
|
||||
set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
|
||||
set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
|
||||
set_global_assignment -name AUTO_TURBO_BIT ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
|
||||
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
|
||||
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
|
||||
set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
|
||||
set_global_assignment -name FITTER_EFFORT "Auto Fit"
|
||||
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
|
||||
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
|
||||
set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
|
||||
set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
|
||||
set_global_assignment -name AUTO_GLOBAL_CLOCK On
|
||||
set_global_assignment -name AUTO_GLOBAL_OE On
|
||||
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
|
||||
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
|
||||
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
|
||||
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
|
||||
set_global_assignment -name ENABLE_HOLD_BACK_OFF On
|
||||
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
|
||||
set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
|
||||
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
|
||||
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
|
||||
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
|
||||
set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
|
||||
set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
|
||||
set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
|
||||
set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
|
||||
set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
|
||||
set_global_assignment -name PR_DONE_OPEN_DRAIN On
|
||||
set_global_assignment -name NCEO_OPEN_DRAIN On
|
||||
set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
|
||||
set_global_assignment -name ENABLE_PR_PINS Off
|
||||
set_global_assignment -name RESERVE_PR_PINS Off
|
||||
set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
|
||||
set_global_assignment -name PR_PINS_OPEN_DRAIN Off
|
||||
set_global_assignment -name CLAMPING_DIODE Off
|
||||
set_global_assignment -name TRI_STATE_SPI_PINS Off
|
||||
set_global_assignment -name UNUSED_TSD_PINS_GND Off
|
||||
set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
|
||||
set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
|
||||
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
|
||||
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
|
||||
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
|
||||
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
|
||||
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
|
||||
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
|
||||
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
|
||||
set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
|
||||
set_global_assignment -name SEU_FIT_REPORT Off
|
||||
set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
|
||||
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
|
||||
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
|
||||
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
|
||||
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
|
||||
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
|
||||
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
|
||||
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
|
||||
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
|
||||
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
|
||||
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
|
||||
set_global_assignment -name COMPRESSION_MODE Off
|
||||
set_global_assignment -name CLOCK_SOURCE Internal
|
||||
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
|
||||
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
|
||||
set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
|
||||
set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
|
||||
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
|
||||
set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
|
||||
set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
|
||||
set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
|
||||
set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
|
||||
set_global_assignment -name SECURITY_BIT Off
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
|
||||
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
|
||||
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
|
||||
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
|
||||
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
|
||||
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
|
||||
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
|
||||
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
|
||||
set_global_assignment -name GENERATE_TTF_FILE Off
|
||||
set_global_assignment -name GENERATE_RBF_FILE Off
|
||||
set_global_assignment -name GENERATE_HEX_FILE Off
|
||||
set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
|
||||
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
|
||||
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
|
||||
set_global_assignment -name AUTO_RESTART_CONFIGURATION On
|
||||
set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
|
||||
set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
|
||||
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP"
|
||||
set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
|
||||
set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
|
||||
set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
|
||||
set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
|
||||
set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
|
||||
set_global_assignment -name POR_SCHEME "Instant ON"
|
||||
set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
|
||||
set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
|
||||
set_global_assignment -name POF_VERIFY_PROTECT Off
|
||||
set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
|
||||
set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
|
||||
set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
|
||||
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
|
||||
set_global_assignment -name GENERATE_PMSF_FILES On
|
||||
set_global_assignment -name START_TIME 0ns
|
||||
set_global_assignment -name SIMULATION_MODE TIMING
|
||||
set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
|
||||
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
|
||||
set_global_assignment -name SETUP_HOLD_DETECTION Off
|
||||
set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
|
||||
set_global_assignment -name CHECK_OUTPUTS Off
|
||||
set_global_assignment -name SIMULATION_COVERAGE On
|
||||
set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
|
||||
set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
|
||||
set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
|
||||
set_global_assignment -name GLITCH_DETECTION Off
|
||||
set_global_assignment -name GLITCH_INTERVAL 1ns
|
||||
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
|
||||
set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
|
||||
set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
|
||||
set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
|
||||
set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
|
||||
set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
|
||||
set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
|
||||
set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
|
||||
set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
|
||||
set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
|
||||
set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
|
||||
set_global_assignment -name DRC_TOP_FANOUT 50
|
||||
set_global_assignment -name DRC_FANOUT_EXCEEDING 30
|
||||
set_global_assignment -name DRC_GATED_CLOCK_FEED 30
|
||||
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
|
||||
set_global_assignment -name ENABLE_DRC_SETTINGS Off
|
||||
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
|
||||
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
|
||||
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
|
||||
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
|
||||
set_global_assignment -name MERGE_HEX_FILE Off
|
||||
set_global_assignment -name GENERATE_SVF_FILE Off
|
||||
set_global_assignment -name GENERATE_ISC_FILE Off
|
||||
set_global_assignment -name GENERATE_JAM_FILE Off
|
||||
set_global_assignment -name GENERATE_JBC_FILE Off
|
||||
set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
|
||||
set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
|
||||
set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
|
||||
set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
|
||||
set_global_assignment -name HPS_EARLY_IO_RELEASE Off
|
||||
set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
|
||||
set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
|
||||
set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
|
||||
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
|
||||
set_global_assignment -name POWER_USE_PVA On
|
||||
set_global_assignment -name POWER_USE_INPUT_FILE "No File"
|
||||
set_global_assignment -name POWER_USE_INPUT_FILES Off
|
||||
set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
|
||||
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
|
||||
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
|
||||
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
|
||||
set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
|
||||
set_global_assignment -name POWER_TJ_VALUE 25
|
||||
set_global_assignment -name POWER_USE_TA_VALUE 25
|
||||
set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
|
||||
set_global_assignment -name POWER_BOARD_TEMPERATURE 25
|
||||
set_global_assignment -name POWER_HPS_ENABLE Off
|
||||
set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
|
||||
set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
|
||||
set_global_assignment -name IGNORE_PARTITIONS Off
|
||||
set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
|
||||
set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
|
||||
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
|
||||
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
|
||||
set_global_assignment -name RTLV_GROUP_RELATED_NODES On
|
||||
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
|
||||
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
|
||||
set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
|
||||
set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
|
||||
set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
|
||||
set_global_assignment -name EQC_BBOX_MERGE On
|
||||
set_global_assignment -name EQC_LVDS_MERGE On
|
||||
set_global_assignment -name EQC_RAM_UNMERGING On
|
||||
set_global_assignment -name EQC_DFF_SS_EMULATION On
|
||||
set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
|
||||
set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
|
||||
set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
|
||||
set_global_assignment -name EQC_STRUCTURE_MATCHING On
|
||||
set_global_assignment -name EQC_AUTO_BREAK_CONE On
|
||||
set_global_assignment -name EQC_POWER_UP_COMPARE Off
|
||||
set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
|
||||
set_global_assignment -name EQC_AUTO_INVERSION On
|
||||
set_global_assignment -name EQC_AUTO_TERMINATE On
|
||||
set_global_assignment -name EQC_SUB_CONE_REPORT Off
|
||||
set_global_assignment -name EQC_RENAMING_RULES On
|
||||
set_global_assignment -name EQC_PARAMETER_CHECK On
|
||||
set_global_assignment -name EQC_AUTO_PORTSWAP On
|
||||
set_global_assignment -name EQC_DETECT_DONT_CARES On
|
||||
set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
|
||||
set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
|
||||
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
|
||||
set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
|
||||
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
|
||||
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
|
||||
set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
|
||||
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
|
||||
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
|
||||
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
|
||||
set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
|
||||
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
|
||||
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
|
||||
set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
|
||||
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
|
||||
set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
|
||||
set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
|
||||
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
|
||||
set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
|
||||
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
|
||||
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
|
||||
set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
|
||||
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
|
||||
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
|
||||
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
|
||||
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
|
||||
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
|
||||
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
|
||||
set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
|
||||
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
|
||||
set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
|
||||
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
|
||||
set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
|
||||
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
|
||||
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
|
||||
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
|
||||
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
|
||||
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
|
||||
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
|
||||
set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
|
||||
set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
|
||||
set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
|
||||
set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
|
||||
set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
|
||||
|
|
@ -0,0 +1 @@
|
|||
qexec "quartus_cpf -c WOLF-LITE.cof"
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<system name="$${FILENAME}">
|
||||
<component
|
||||
name="$${FILENAME}"
|
||||
displayName="$${FILENAME}"
|
||||
version="1.0"
|
||||
description=""
|
||||
tags="INTERNAL_COMPONENT=true"
|
||||
categories="" />
|
||||
<parameter name="bonusData"><![CDATA[bonusData
|
||||
{
|
||||
element altclkctrl_0
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "0";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
}
|
||||
]]></parameter>
|
||||
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
|
||||
<parameter name="device" value="EP4CE22E22C8" />
|
||||
<parameter name="deviceFamily" value="Cyclone IV E" />
|
||||
<parameter name="deviceSpeedGrade" value="8" />
|
||||
<parameter name="fabricMode" value="QSYS" />
|
||||
<parameter name="generateLegacySim" value="false" />
|
||||
<parameter name="generationId" value="0" />
|
||||
<parameter name="globalResetBus" value="false" />
|
||||
<parameter name="hdlLanguage" value="VERILOG" />
|
||||
<parameter name="hideFromIPCatalog" value="true" />
|
||||
<parameter name="lockedInterfaceDefinition" value="" />
|
||||
<parameter name="maxAdditionalLatency" value="1" />
|
||||
<parameter name="projectName" value="" />
|
||||
<parameter name="sopcBorderPoints" value="false" />
|
||||
<parameter name="systemHash" value="0" />
|
||||
<parameter name="testBenchDutName" value="" />
|
||||
<parameter name="timeStamp" value="0" />
|
||||
<parameter name="useTestBenchNamingPattern" value="false" />
|
||||
<instanceScript></instanceScript>
|
||||
<interface
|
||||
name="altclkctrl_input"
|
||||
internal="altclkctrl_0.altclkctrl_input"
|
||||
type="conduit"
|
||||
dir="end">
|
||||
<port name="inclk" internal="inclk" />
|
||||
</interface>
|
||||
<interface
|
||||
name="altclkctrl_output"
|
||||
internal="altclkctrl_0.altclkctrl_output"
|
||||
type="conduit"
|
||||
dir="end">
|
||||
<port name="outclk" internal="outclk" />
|
||||
</interface>
|
||||
<module
|
||||
name="altclkctrl_0"
|
||||
kind="altclkctrl"
|
||||
version="18.1"
|
||||
enabled="1"
|
||||
autoexport="1">
|
||||
<parameter name="CLOCK_TYPE" value="1" />
|
||||
<parameter name="DEVICE_FAMILY" value="Cyclone IV E" />
|
||||
<parameter name="ENA_REGISTER_MODE" value="1" />
|
||||
<parameter name="GUI_USE_ENA" value="false" />
|
||||
<parameter name="NUMBER_OF_CLOCKS" value="1" />
|
||||
<parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" value="false" />
|
||||
</module>
|
||||
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
|
||||
</system>
|
||||
|
|
@ -0,0 +1,257 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<EnsembleReport name="clock_buffer" kind="clock_buffer" version="1.0" fabric="QSYS">
|
||||
<!-- Format version 18.1 625 (Future versions may contain additional information.) -->
|
||||
<!-- 2021.03.31.22:15:10 -->
|
||||
<!-- A collection of modules and connections -->
|
||||
<parameter name="AUTO_GENERATION_ID">
|
||||
<type>java.lang.Integer</type>
|
||||
<value>1617214510</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>GENERATION_ID</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_UNIQUE_ID">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>UNIQUE_ID</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE_FAMILY">
|
||||
<type>java.lang.String</type>
|
||||
<value>CYCLONEIVE</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE">
|
||||
<type>java.lang.String</type>
|
||||
<value>EP4CE10E22C8</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE">
|
||||
<type>java.lang.String</type>
|
||||
<value>8</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>Cyclone IV E</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<module
|
||||
name="altclkctrl_0"
|
||||
kind="altclkctrl"
|
||||
version="18.1"
|
||||
path="altclkctrl_0">
|
||||
<!-- Describes a single module. Module parameters are
|
||||
the requested settings for a module instance. -->
|
||||
<parameter name="DEVICE_FAMILY">
|
||||
<type>java.lang.String</type>
|
||||
<value>CYCLONEIVE</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="CLOCK_TYPE">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="NUMBER_OF_CLOCKS">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="ENA_REGISTER_MODE">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="GUI_USE_ENA">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<interface name="altclkctrl_input" kind="conduit_end" version="18.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<assignment>
|
||||
<name>ui.blockdiagram.direction</name>
|
||||
<value>input</value>
|
||||
</assignment>
|
||||
<parameter name="associatedClock">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="associatedReset">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>conduit</type>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>inclk</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>inclk</role>
|
||||
</port>
|
||||
</interface>
|
||||
<interface name="altclkctrl_output" kind="conduit_end" version="18.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<assignment>
|
||||
<name>ui.blockdiagram.direction</name>
|
||||
<value>output</value>
|
||||
</assignment>
|
||||
<parameter name="associatedClock">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="associatedReset">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>conduit</type>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>outclk</name>
|
||||
<direction>Output</direction>
|
||||
<width>1</width>
|
||||
<role>outclk</role>
|
||||
</port>
|
||||
</interface>
|
||||
</module>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>altclkctrl</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IModule</subtype>
|
||||
<displayName>ALTCLKCTRL Intel FPGA IP</displayName>
|
||||
<version>18.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>2</instanceCount>
|
||||
<name>conduit_end</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
<displayName>Conduit</displayName>
|
||||
<version>18.1</version>
|
||||
</plugin>
|
||||
<reportVersion>18.1 625</reportVersion>
|
||||
<uniqueIdentifier></uniqueIdentifier>
|
||||
</EnsembleReport>
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 272 104)
|
||||
(text "clock_buffer" (rect 99 -1 149 11)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 88 20 100)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 72)
|
||||
(input)
|
||||
(text "inclk" (rect 0 0 16 12)(font "Arial" (font_size 8)))
|
||||
(text "inclk" (rect 4 61 34 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 96 72)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 272 72)
|
||||
(output)
|
||||
(text "outclk" (rect 0 0 22 12)(font "Arial" (font_size 8)))
|
||||
(text "outclk" (rect 242 61 278 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 272 72)(pt 160 72)(line_width 1))
|
||||
)
|
||||
(drawing
|
||||
(text "altclkctrl_input" (rect 13 43 122 99)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "inclk" (rect 101 67 232 144)(font "Arial" (color 0 0 0)))
|
||||
(text "altclkctrl_output" (rect 161 43 424 99)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "outclk" (rect 132 67 300 144)(font "Arial" (color 0 0 0)))
|
||||
(text " clock_buffer " (rect 214 88 512 186)(font "Arial" ))
|
||||
(line (pt 96 32)(pt 160 32)(line_width 1))
|
||||
(line (pt 160 32)(pt 160 88)(line_width 1))
|
||||
(line (pt 96 88)(pt 160 88)(line_width 1))
|
||||
(line (pt 96 32)(pt 96 88)(line_width 1))
|
||||
(line (pt 97 52)(pt 97 76)(line_width 1))
|
||||
(line (pt 98 52)(pt 98 76)(line_width 1))
|
||||
(line (pt 159 52)(pt 159 76)(line_width 1))
|
||||
(line (pt 158 52)(pt 158 76)(line_width 1))
|
||||
(line (pt 0 0)(pt 272 0)(line_width 1))
|
||||
(line (pt 272 0)(pt 272 104)(line_width 1))
|
||||
(line (pt 0 104)(pt 272 104)(line_width 1))
|
||||
(line (pt 0 0)(pt 0 104)(line_width 1))
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
component clock_buffer is
|
||||
port (
|
||||
inclk : in std_logic := 'X'; -- inclk
|
||||
outclk : out std_logic -- outclk
|
||||
);
|
||||
end component clock_buffer;
|
||||
|
||||
|
|
@ -0,0 +1,157 @@
|
|||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
|
||||
|
||||
<html xmlns="http://www.w3.org/1999/xhtml">
|
||||
<head>
|
||||
<title>datasheet for clock_buffer</title>
|
||||
<style type="text/css">
|
||||
body { font-family:arial ;}
|
||||
a { text-decoration:underline ; color:#003000 ;}
|
||||
a:hover { text-decoration:underline ; color:0030f0 ;}
|
||||
td { padding : 5px ;}
|
||||
table.topTitle { width:100% ;}
|
||||
table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
|
||||
table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
|
||||
table.blueBar { width : 100% ; border-spacing : 0px ;}
|
||||
table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
|
||||
table.blueBar td.l { text-align : left ;}
|
||||
table.blueBar td.r { text-align : right ;}
|
||||
table.items { width:100% ; border-collapse:collapse ;}
|
||||
table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
|
||||
table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
|
||||
div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ; font-size:12px ;}
|
||||
body { font-family:arial ;}
|
||||
table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
|
||||
table.x td { border:1px solid #bbb ;}
|
||||
td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.grid { border-collapse:collapse ;}
|
||||
table.grid td { border:1px solid #bbb ;}
|
||||
table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
|
||||
table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
|
||||
table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
|
||||
table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
|
||||
table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
|
||||
table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
|
||||
table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
|
||||
table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
|
||||
table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
|
||||
table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
|
||||
table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
|
||||
table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
|
||||
table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
|
||||
table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
|
||||
table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
|
||||
table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
|
||||
table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
|
||||
.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
|
||||
.flowbox { display:inline-block ;}
|
||||
.parametersbox table { font-size:10px ;}
|
||||
td.parametername { font-style:italic ;}
|
||||
td.parametervalue { font-weight:bold ;}
|
||||
div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
|
||||
</head>
|
||||
<body>
|
||||
<table class="topTitle">
|
||||
<tr>
|
||||
<td class="l">clock_buffer</td>
|
||||
<td class="r">
|
||||
<br/>
|
||||
<br/>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">2019.11.10.03:26:29</td>
|
||||
<td class="r">Datasheet</td>
|
||||
</tr>
|
||||
</table>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Overview</div>
|
||||
<div class="greydiv">
|
||||
<div style="display:inline-block ; text-align:left">
|
||||
<table class="connectionboxes">
|
||||
<tr style="height:6px">
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><span style="display:inline-block ; width:28px"> </span>
|
||||
<div style="display:inline-block ; text-align:left"><span>
|
||||
<br/></span>
|
||||
</div>
|
||||
</div>
|
||||
<div style="width:100% ; height:10px"> </div>
|
||||
<div class="label">Memory Map</div>
|
||||
<table class="mmap">
|
||||
<tr>
|
||||
<td class="empty" rowspan="2"></td>
|
||||
</tr>
|
||||
</table>
|
||||
<a name="module_altclkctrl_0"> </a>
|
||||
<div>
|
||||
<hr/>
|
||||
<h2>altclkctrl_0</h2>altclkctrl v18.1
|
||||
<br/>
|
||||
<br/>
|
||||
<br/>
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Parameters</h2>
|
||||
<table>
|
||||
<tr>
|
||||
<td class="parametername">DEVICE_FAMILY</td>
|
||||
<td class="parametervalue">CYCLONEIVE</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">CLOCK_TYPE</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">NUMBER_OF_CLOCKS</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">ENA_REGISTER_MODE</td>
|
||||
<td class="parametervalue">1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">GUI_USE_ENA</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">deviceFamily</td>
|
||||
<td class="parametervalue">UNKNOWN</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="parametername">generateLegacySim</td>
|
||||
<td class="parametervalue">false</td>
|
||||
</tr>
|
||||
</table>
|
||||
</td>
|
||||
</tr>
|
||||
</table>  
|
||||
<table class="flowbox">
|
||||
<tr>
|
||||
<td class="parametersbox">
|
||||
<h2>Software Assignments</h2>(none)</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
<table class="blueBar">
|
||||
<tr>
|
||||
<td class="l">generation took 0,01 seconds</td>
|
||||
<td class="r">rendering took 0,03 seconds</td>
|
||||
</tr>
|
||||
</table>
|
||||
</body>
|
||||
</html>
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<pinplan
|
||||
variation_name="altclkctrl_0"
|
||||
megafunction_name="ALTCLKCTRL"
|
||||
intended_family="Cyclone IV E"
|
||||
specifies="all_ports">
|
||||
<global>
|
||||
<pin name="inclk" direction="input" scope="external" />
|
||||
<pin name="outclk" direction="output" scope="external" />
|
||||
</global>
|
||||
</pinplan>
|
||||
|
|
@ -0,0 +1,131 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<deploy
|
||||
date="2019.11.10.03:26:30"
|
||||
outputDirectory="D:/Dropbox/Develop/Projects/UA3REO/FPGA/clock_buffer/">
|
||||
<perimeter>
|
||||
<parameter
|
||||
name="AUTO_GENERATION_ID"
|
||||
type="Integer"
|
||||
defaultValue="0"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_UNIQUE_ID"
|
||||
type="String"
|
||||
defaultValue=""
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_FAMILY"
|
||||
type="String"
|
||||
defaultValue="Cyclone IV E"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE"
|
||||
type="String"
|
||||
defaultValue="EP4CE22E22C8"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<parameter
|
||||
name="AUTO_DEVICE_SPEEDGRADE"
|
||||
type="String"
|
||||
defaultValue="8"
|
||||
onHdl="0"
|
||||
affectsHdl="1" />
|
||||
<interface name="altclkctrl_input" kind="conduit" start="0">
|
||||
<property name="associatedClock" value="" />
|
||||
<property name="associatedReset" value="" />
|
||||
<port name="inclk" direction="input" role="inclk" width="1" />
|
||||
</interface>
|
||||
<interface name="altclkctrl_output" kind="conduit" start="0">
|
||||
<property name="associatedClock" value="" />
|
||||
<property name="associatedReset" value="" />
|
||||
<port name="outclk" direction="output" role="outclk" width="1" />
|
||||
</interface>
|
||||
</perimeter>
|
||||
<entity
|
||||
path=""
|
||||
parameterizationKey="clock_buffer:1.0:AUTO_DEVICE=EP4CE22E22C8,AUTO_DEVICE_FAMILY=Cyclone IV E,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1573341989,AUTO_UNIQUE_ID=(altclkctrl:18.1:CLOCK_TYPE=1,DEVICE_FAMILY=Cyclone IV E,ENA_REGISTER_MODE=1,GUI_USE_ENA=false,NUMBER_OF_CLOCKS=1,USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION=false)"
|
||||
instancePathKey="clock_buffer"
|
||||
kind="clock_buffer"
|
||||
version="1.0"
|
||||
name="clock_buffer">
|
||||
<parameter name="AUTO_GENERATION_ID" value="1573341989" />
|
||||
<parameter name="AUTO_DEVICE" value="EP4CE22E22C8" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
|
||||
<parameter name="AUTO_UNIQUE_ID" value="" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
|
||||
<generatedFiles>
|
||||
<file
|
||||
path="D:/Dropbox/Develop/Projects/UA3REO/FPGA/clock_buffer/synthesis/clock_buffer.v"
|
||||
type="VERILOG" />
|
||||
</generatedFiles>
|
||||
<childGeneratedFiles>
|
||||
<file
|
||||
path="D:/Dropbox/Develop/Projects/UA3REO/FPGA/clock_buffer/synthesis/submodules/clock_buffer_altclkctrl_0.v"
|
||||
type="VERILOG"
|
||||
attributes="" />
|
||||
</childGeneratedFiles>
|
||||
<sourceFiles>
|
||||
<file path="D:/Dropbox/Develop/Projects/UA3REO/FPGA/clock_buffer.qsys" />
|
||||
</sourceFiles>
|
||||
<childSourceFiles>
|
||||
<file
|
||||
path="C:/intelfpga/18.1/ip/altera/megafunctions/altclkctrl/altclkctrl_hw.tcl" />
|
||||
</childSourceFiles>
|
||||
<messages>
|
||||
<message level="Debug" culprit="clock_buffer">queue size: 0 starting:clock_buffer "clock_buffer"</message>
|
||||
<message level="Progress" culprit="min"></message>
|
||||
<message level="Progress" culprit="max"></message>
|
||||
<message level="Progress" culprit="current"></message>
|
||||
<message level="Debug">Transform: CustomInstructionTransform</message>
|
||||
<message level="Debug">No custom instruction connections, skipping transform </message>
|
||||
<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
|
||||
<message level="Debug">Transform: MMTransform</message>
|
||||
<message level="Debug">Transform: InterruptMapperTransform</message>
|
||||
<message level="Debug">Transform: InterruptSyncTransform</message>
|
||||
<message level="Debug">Transform: InterruptFanoutTransform</message>
|
||||
<message level="Debug">Transform: AvalonStreamingTransform</message>
|
||||
<message level="Debug">Transform: ResetAdaptation</message>
|
||||
<message level="Debug" culprit="clock_buffer"><![CDATA["<b>clock_buffer</b>" reuses <b>altclkctrl</b> "<b>submodules/clock_buffer_altclkctrl_0</b>"]]></message>
|
||||
<message level="Debug" culprit="clock_buffer">queue size: 0 starting:altclkctrl "submodules/clock_buffer_altclkctrl_0"</message>
|
||||
<message level="Info" culprit="altclkctrl_0">Generating top-level entity clock_buffer_altclkctrl_0.</message>
|
||||
<message level="Debug" culprit="altclkctrl_0">Current quartus bindir: C:/intelfpga/18.1/quartus/bin64/.</message>
|
||||
<message level="Info" culprit="altclkctrl_0"><![CDATA["<b>clock_buffer</b>" instantiated <b>altclkctrl</b> "<b>altclkctrl_0</b>"]]></message>
|
||||
</messages>
|
||||
</entity>
|
||||
<entity
|
||||
path="submodules/"
|
||||
parameterizationKey="altclkctrl:18.1:CLOCK_TYPE=1,DEVICE_FAMILY=Cyclone IV E,ENA_REGISTER_MODE=1,GUI_USE_ENA=false,NUMBER_OF_CLOCKS=1,USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION=false"
|
||||
instancePathKey="clock_buffer:.:altclkctrl_0"
|
||||
kind="altclkctrl"
|
||||
version="18.1"
|
||||
name="clock_buffer_altclkctrl_0">
|
||||
<parameter name="NUMBER_OF_CLOCKS" value="1" />
|
||||
<parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" value="false" />
|
||||
<parameter name="GUI_USE_ENA" value="false" />
|
||||
<parameter name="DEVICE_FAMILY" value="Cyclone IV E" />
|
||||
<parameter name="ENA_REGISTER_MODE" value="1" />
|
||||
<parameter name="CLOCK_TYPE" value="1" />
|
||||
<generatedFiles>
|
||||
<file
|
||||
path="D:/Dropbox/Develop/Projects/UA3REO/FPGA/clock_buffer/synthesis/submodules/clock_buffer_altclkctrl_0.v"
|
||||
type="VERILOG"
|
||||
attributes="" />
|
||||
</generatedFiles>
|
||||
<childGeneratedFiles/>
|
||||
<sourceFiles>
|
||||
<file
|
||||
path="C:/intelfpga/18.1/ip/altera/megafunctions/altclkctrl/altclkctrl_hw.tcl" />
|
||||
</sourceFiles>
|
||||
<childSourceFiles/>
|
||||
<instantiator instantiator="clock_buffer" as="altclkctrl_0" />
|
||||
<messages>
|
||||
<message level="Debug" culprit="clock_buffer">queue size: 0 starting:altclkctrl "submodules/clock_buffer_altclkctrl_0"</message>
|
||||
<message level="Info" culprit="altclkctrl_0">Generating top-level entity clock_buffer_altclkctrl_0.</message>
|
||||
<message level="Debug" culprit="altclkctrl_0">Current quartus bindir: C:/intelfpga/18.1/quartus/bin64/.</message>
|
||||
<message level="Info" culprit="altclkctrl_0"><![CDATA["<b>clock_buffer</b>" instantiated <b>altclkctrl</b> "<b>altclkctrl_0</b>"]]></message>
|
||||
</messages>
|
||||
</entity>
|
||||
</deploy>
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
|
||||
module clock_buffer (
|
||||
inclk,
|
||||
outclk);
|
||||
|
||||
input inclk;
|
||||
output outclk;
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
clock_buffer u0 (
|
||||
.inclk (<connected-to-inclk>), // altclkctrl_input.inclk
|
||||
.outclk (<connected-to-outclk>) // altclkctrl_output.outclk
|
||||
);
|
||||
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
component clock_buffer is
|
||||
port (
|
||||
inclk : in std_logic := 'X'; -- inclk
|
||||
outclk : out std_logic -- outclk
|
||||
);
|
||||
end component clock_buffer;
|
||||
|
||||
u0 : component clock_buffer
|
||||
port map (
|
||||
inclk => CONNECTED_TO_inclk, -- altclkctrl_input.inclk
|
||||
outclk => CONNECTED_TO_outclk -- altclkctrl_output.outclk
|
||||
);
|
||||
|
||||
|
|
@ -0,0 +1,339 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<EnsembleReport name="clock_buffer" kind="system" version="18.1" fabric="QSYS">
|
||||
<!-- Format version 18.1 625 (Future versions may contain additional information.) -->
|
||||
<!-- 2019.11.10.03:26:30 -->
|
||||
<!-- A collection of modules and connections -->
|
||||
<parameter name="clockCrossingAdapter">
|
||||
<type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
|
||||
<value>HANDSHAKE</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="device">
|
||||
<type>java.lang.String</type>
|
||||
<value>EP4CE22E22C8</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>CYCLONEIVE</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceSpeedGrade">
|
||||
<type>java.lang.String</type>
|
||||
<value>8</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="fabricMode">
|
||||
<type>com.altera.sopcmodel.ensemble.Ensemble$EFabricMode</type>
|
||||
<value>QSYS</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generationId">
|
||||
<type>int</type>
|
||||
<value>1573341989</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="globalResetBus">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="hdlLanguage">
|
||||
<type>com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage</type>
|
||||
<value>VERILOG</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="hideFromIPCatalog">
|
||||
<type>boolean</type>
|
||||
<value>true</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="lockedInterfaceDefinition">
|
||||
<type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="maxAdditionalLatency">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="projectName">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="sopcBorderPoints">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="systemHash">
|
||||
<type>long</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="testBenchDutName">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="timeStamp">
|
||||
<type>long</type>
|
||||
<value>0</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="useTestBenchNamingPattern">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<module
|
||||
name="altclkctrl_0"
|
||||
kind="altclkctrl"
|
||||
version="18.1"
|
||||
path="altclkctrl_0">
|
||||
<!-- Describes a single module. Module parameters are
|
||||
the requested settings for a module instance. -->
|
||||
<parameter name="DEVICE_FAMILY">
|
||||
<type>java.lang.String</type>
|
||||
<value>CYCLONEIVE</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
<sysinfo_type>DEVICE_FAMILY</sysinfo_type>
|
||||
</parameter>
|
||||
<parameter name="CLOCK_TYPE">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="NUMBER_OF_CLOCKS">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="ENA_REGISTER_MODE">
|
||||
<type>int</type>
|
||||
<value>1</value>
|
||||
<derived>false</derived>
|
||||
<enabled>false</enabled>
|
||||
<visible>false</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="GUI_USE_ENA">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<interface name="altclkctrl_input" kind="conduit_end" version="18.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<assignment>
|
||||
<name>ui.blockdiagram.direction</name>
|
||||
<value>input</value>
|
||||
</assignment>
|
||||
<parameter name="associatedClock">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="associatedReset">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>conduit</type>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>inclk</name>
|
||||
<direction>Input</direction>
|
||||
<width>1</width>
|
||||
<role>inclk</role>
|
||||
</port>
|
||||
</interface>
|
||||
<interface name="altclkctrl_output" kind="conduit_end" version="18.1">
|
||||
<!-- The connection points exposed by a module instance for the
|
||||
particular module parameters. Connection points and their
|
||||
parameters are a RESULT of the module parameters. -->
|
||||
<assignment>
|
||||
<name>ui.blockdiagram.direction</name>
|
||||
<value>output</value>
|
||||
</assignment>
|
||||
<parameter name="associatedClock">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="associatedReset">
|
||||
<type>java.lang.String</type>
|
||||
<value></value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="deviceFamily">
|
||||
<type>java.lang.String</type>
|
||||
<value>UNKNOWN</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<parameter name="generateLegacySim">
|
||||
<type>boolean</type>
|
||||
<value>false</value>
|
||||
<derived>false</derived>
|
||||
<enabled>true</enabled>
|
||||
<visible>true</visible>
|
||||
<valid>true</valid>
|
||||
</parameter>
|
||||
<type>conduit</type>
|
||||
<isStart>false</isStart>
|
||||
<port>
|
||||
<name>outclk</name>
|
||||
<direction>Output</direction>
|
||||
<width>1</width>
|
||||
<role>outclk</role>
|
||||
</port>
|
||||
</interface>
|
||||
</module>
|
||||
<plugin>
|
||||
<instanceCount>1</instanceCount>
|
||||
<name>altclkctrl</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IModule</subtype>
|
||||
<displayName>ALTCLKCTRL Intel FPGA IP</displayName>
|
||||
<version>18.1</version>
|
||||
</plugin>
|
||||
<plugin>
|
||||
<instanceCount>2</instanceCount>
|
||||
<name>conduit_end</name>
|
||||
<type>com.altera.entityinterfaces.IElementClass</type>
|
||||
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
|
||||
<displayName>Conduit</displayName>
|
||||
<version>18.1</version>
|
||||
</plugin>
|
||||
<reportVersion>18.1 625</reportVersion>
|
||||
<uniqueIdentifier>00FF3199AA160000016E527D8CDB</uniqueIdentifier>
|
||||
</EnsembleReport>
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_TOOL_NAME "Qsys"
|
||||
set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_TOOL_VERSION "18.1"
|
||||
set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_TOOL_ENV "Qsys"
|
||||
set_global_assignment -library "clock_buffer" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../clock_buffer.sopcinfo"]
|
||||
set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name SLD_INFO "QSYS_NAME clock_buffer HAS_SOPCINFO 1 GENERATION_ID 1573341989"
|
||||
set_global_assignment -library "clock_buffer" -name MISC_FILE [file join $::quartus(qip_path) "../clock_buffer.cmp"]
|
||||
set_global_assignment -library "clock_buffer" -name SLD_FILE [file join $::quartus(qip_path) "clock_buffer.debuginfo"]
|
||||
set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_TARGETED_DEVICE_FAMILY "Cyclone IV E"
|
||||
set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
|
||||
set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_QSYS_MODE "STANDALONE"
|
||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||
set_global_assignment -library "clock_buffer" -name MISC_FILE [file join $::quartus(qip_path) "../../clock_buffer.qsys"]
|
||||
set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_COMPONENT_NAME "Y2xvY2tfYnVmZmVy"
|
||||
set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_COMPONENT_DISPLAY_NAME "Y2xvY2tfYnVmZmVy"
|
||||
set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_COMPONENT_REPORT_HIERARCHY "On"
|
||||
set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_COMPONENT_VERSION "MS4w"
|
||||
set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTU3MzM0MTk4OQ==::QXV0byBHRU5FUkFUSU9OX0lE"
|
||||
set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
|
||||
set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UyMkUyMkM4::QXV0byBERVZJQ0U="
|
||||
set_global_assignment -entity "clock_buffer" -library "clock_buffer" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
|
||||
set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_COMPONENT_NAME "Y2xvY2tfYnVmZmVyX2FsdGNsa2N0cmxfMA=="
|
||||
set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_COMPONENT_DISPLAY_NAME "QUxUQ0xLQ1RSTCBJbnRlbCBGUEdBIElQ"
|
||||
set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
|
||||
set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_COMPONENT_INTERNAL "Off"
|
||||
set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
|
||||
set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_COMPONENT_VERSION "MTguMQ=="
|
||||
set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::Q3ljbG9uZSBJViBF::RGV2aWNlIEZhbWlseQ=="
|
||||
set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_COMPONENT_PARAMETER "Q0xPQ0tfVFlQRQ==::MQ==::SG93IGRvIHlvdSB3YW50IHRvIHVzZSB0aGUgQUxUQ0xLQ1RSTD8="
|
||||
set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_COMPONENT_PARAMETER "TlVNQkVSX09GX0NMT0NLUw==::MQ==::SG93IG1hbnkgY2xvY2sgaW5wdXRzIHdvdWxkIHlvdSBsaWtlPw=="
|
||||
set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_COMPONENT_PARAMETER "R1VJX1VTRV9FTkE=::ZmFsc2U=::Q3JlYXRlICdlbmEnIHBvcnQgdG8gZW5hYmxlIG9yIGRpc2FibGUgdGhlIGNsb2NrIG5ldHdvcmsgZHJpdmVuIGJ5IHRoaXMgYnVmZmVyPw=="
|
||||
set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_COMPONENT_PARAMETER "VVNFX0dMSVRDSF9GUkVFX1NXSVRDSF9PVkVSX0lNUExFTUVOVEFUSU9O::ZmFsc2U=::RW5zdXJlIGdsaXRjaC1mcmVlIHN3aXRjaG92ZXIgaW1wbGVtZW50YXRpb24="
|
||||
|
||||
set_global_assignment -library "clock_buffer" -name VERILOG_FILE [file join $::quartus(qip_path) "clock_buffer.v"]
|
||||
set_global_assignment -library "clock_buffer" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/clock_buffer_altclkctrl_0.v"]
|
||||
|
||||
set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_TOOL_NAME "altclkctrl"
|
||||
set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_TOOL_VERSION "18.1"
|
||||
set_global_assignment -entity "clock_buffer_altclkctrl_0" -library "clock_buffer" -name IP_TOOL_ENV "Qsys"
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
// clock_buffer.v
|
||||
|
||||
// Generated using ACDS version 18.1 625
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module clock_buffer (
|
||||
input wire inclk, // altclkctrl_input.inclk
|
||||
output wire outclk // altclkctrl_output.outclk
|
||||
);
|
||||
|
||||
clock_buffer_altclkctrl_0 altclkctrl_0 (
|
||||
.inclk (inclk), // altclkctrl_input.inclk
|
||||
.outclk (outclk) // altclkctrl_output.outclk
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,114 @@
|
|||
//altclkctrl CBX_SINGLE_OUTPUT_FILE="ON" CLOCK_TYPE="Global Clock" DEVICE_FAMILY="Cyclone IV E" ENA_REGISTER_MODE="falling edge" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" ena inclk outclk
|
||||
//VERSION_BEGIN 18.1 cbx_altclkbuf 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ VERSION_END
|
||||
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
|
||||
// altera message_off 10463
|
||||
|
||||
|
||||
|
||||
// Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License
|
||||
// Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
// the Intel FPGA IP License Agreement, or other applicable license
|
||||
// agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by
|
||||
// Intel and sold by Intel or its authorized distributors. Please
|
||||
// refer to the applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
//synthesis_resources = clkctrl 1
|
||||
//synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
//synopsys translate_on
|
||||
module clock_buffer_altclkctrl_0_sub
|
||||
(
|
||||
ena,
|
||||
inclk,
|
||||
outclk) /* synthesis synthesis_clearbox=1 */;
|
||||
input ena;
|
||||
input [3:0] inclk;
|
||||
output outclk;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri1 ena;
|
||||
tri0 [3:0] inclk;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire wire_clkctrl1_outclk;
|
||||
wire [1:0] clkselect;
|
||||
wire [1:0] clkselect_wire;
|
||||
wire [3:0] inclk_wire;
|
||||
|
||||
cycloneive_clkctrl clkctrl1
|
||||
(
|
||||
.clkselect(clkselect_wire),
|
||||
.ena(ena),
|
||||
.inclk(inclk_wire),
|
||||
.outclk(wire_clkctrl1_outclk)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.devclrn(1'b1),
|
||||
.devpor(1'b1)
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
clkctrl1.clock_type = "Global Clock",
|
||||
clkctrl1.ena_register_mode = "falling edge",
|
||||
clkctrl1.lpm_type = "cycloneive_clkctrl";
|
||||
assign
|
||||
clkselect = {2{1'b0}},
|
||||
clkselect_wire = {clkselect},
|
||||
inclk_wire = {inclk},
|
||||
outclk = wire_clkctrl1_outclk;
|
||||
endmodule //clock_buffer_altclkctrl_0_sub
|
||||
//VALID FILE // (C) 2001-2018 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions and other
|
||||
// software and tools, and its AMPP partner logic functions, and any output
|
||||
// files from any of the foregoing (including device programming or simulation
|
||||
// files), and any associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License Subscription
|
||||
// Agreement, Intel FPGA IP License Agreement, or other applicable
|
||||
// license agreement, including, without limitation, that your use is for the
|
||||
// sole purpose of programming logic devices manufactured by Intel and sold by
|
||||
// Intel or its authorized distributors. Please refer to the applicable
|
||||
// agreement for further details.
|
||||
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module clock_buffer_altclkctrl_0 (
|
||||
inclk,
|
||||
outclk);
|
||||
|
||||
input inclk;
|
||||
output outclk;
|
||||
|
||||
wire sub_wire0;
|
||||
wire outclk;
|
||||
wire sub_wire1;
|
||||
wire sub_wire2;
|
||||
wire [3:0] sub_wire3;
|
||||
wire [2:0] sub_wire4;
|
||||
|
||||
assign outclk = sub_wire0;
|
||||
assign sub_wire1 = 1'h1;
|
||||
assign sub_wire2 = inclk;
|
||||
assign sub_wire3[3:0] = {sub_wire4, sub_wire2};
|
||||
assign sub_wire4[2:0] = 3'h0;
|
||||
|
||||
clock_buffer_altclkctrl_0_sub clock_buffer_altclkctrl_0_sub_component (
|
||||
.ena (sub_wire1),
|
||||
.inclk (sub_wire3),
|
||||
.outclk (sub_wire0));
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 0 0 112 48)
|
||||
(text "dac_null" (rect 33 0 89 16)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 32 25 44)(font "Arial" ))
|
||||
(port
|
||||
(pt 112 24)
|
||||
(output)
|
||||
(text "result[13..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
|
||||
(text "8192" (rect 69 17 91 30)(font "Arial" (font_size 8)))
|
||||
(line (pt 112 24)(pt 96 24)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "14" (rect 94 26 197 63)(font "Arial" ))
|
||||
(line (pt 106 20)(pt 98 28))
|
||||
(line (pt 16 16)(pt 16 32))
|
||||
(line (pt 16 16)(pt 96 16))
|
||||
(line (pt 16 32)(pt 96 32))
|
||||
(line (pt 96 16)(pt 96 32))
|
||||
(line (pt 0 0)(pt 114 0))
|
||||
(line (pt 114 0)(pt 114 50))
|
||||
(line (pt 0 50)(pt 114 50))
|
||||
(line (pt 0 0)(pt 0 50))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
(line (pt 0 0)(pt 0 0))
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "18.1"
|
||||
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "dac_null.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dac_null.bsf"]
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
// megafunction wizard: %LPM_CONSTANT%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: LPM_CONSTANT
|
||||
|
||||
// ============================================================
|
||||
// File Name: dac_null.v
|
||||
// Megafunction Name(s):
|
||||
// LPM_CONSTANT
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// lpm
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 18.1.0 Build 625 09/12/2018 SJ Standard Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
//Your use of Intel Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Intel Program License
|
||||
//Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
//the Intel FPGA IP License Agreement, or other applicable license
|
||||
//agreement, including, without limitation, that your use is for
|
||||
//the sole purpose of programming logic devices manufactured by
|
||||
//Intel and sold by Intel or its authorized distributors. Please
|
||||
//refer to the applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module dac_null (
|
||||
result);
|
||||
|
||||
output [13:0] result;
|
||||
|
||||
wire [13:0] sub_wire0;
|
||||
wire [13:0] result = sub_wire0[13:0];
|
||||
|
||||
lpm_constant LPM_CONSTANT_component (
|
||||
.result (sub_wire0));
|
||||
defparam
|
||||
LPM_CONSTANT_component.lpm_cvalue = 8192,
|
||||
LPM_CONSTANT_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
|
||||
LPM_CONSTANT_component.lpm_type = "LPM_CONSTANT",
|
||||
LPM_CONSTANT_component.lpm_width = 14;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
// Retrieval info: PRIVATE: Radix NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: Value NUMERIC "8192"
|
||||
// Retrieval info: PRIVATE: nBit NUMERIC "14"
|
||||
// Retrieval info: PRIVATE: new_diagram STRING "1"
|
||||
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
// Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "8192"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "14"
|
||||
// Retrieval info: USED_PORT: result 0 0 14 0 OUTPUT NODEFVAL "result[13..0]"
|
||||
// Retrieval info: CONNECT: result 0 0 14 0 @result 0 0 14 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL dac_null.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL dac_null.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL dac_null.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL dac_null.bsf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL dac_null_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL dac_null_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: lpm
|
||||
|
|
@ -0,0 +1,110 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 16 16 320 160)
|
||||
(text "data_shifter" (rect 5 0 52 12)(font "Arial" ))
|
||||
(text "inst" (rect 8 128 20 140)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "data_in_I[in_width-1..0]" (rect 0 0 88 12)(font "Arial" ))
|
||||
(text "data_in_I[in_width-1..0]" (rect 21 27 109 39)(font "Arial" ))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "data_valid_I" (rect 0 0 48 12)(font "Arial" ))
|
||||
(text "data_valid_I" (rect 21 43 69 55)(font "Arial" ))
|
||||
(line (pt 0 48)(pt 16 48)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "data_in_Q[in_width-1..0]" (rect 0 0 93 12)(font "Arial" ))
|
||||
(text "data_in_Q[in_width-1..0]" (rect 21 59 114 71)(font "Arial" ))
|
||||
(line (pt 0 64)(pt 16 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 80)
|
||||
(input)
|
||||
(text "data_valid_Q" (rect 0 0 53 12)(font "Arial" ))
|
||||
(text "data_valid_Q" (rect 21 75 74 87)(font "Arial" ))
|
||||
(line (pt 0 80)(pt 16 80)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "distance[7..0]" (rect 0 0 51 12)(font "Arial" ))
|
||||
(text "distance[7..0]" (rect 21 91 72 103)(font "Arial" ))
|
||||
(line (pt 0 96)(pt 16 96)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "enabled" (rect 0 0 29 12)(font "Arial" ))
|
||||
(text "enabled" (rect 21 107 50 119)(font "Arial" ))
|
||||
(line (pt 0 112)(pt 16 112)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 304 32)
|
||||
(output)
|
||||
(text "data_out_I[out_width-1..0]" (rect 0 0 100 12)(font "Arial" ))
|
||||
(text "data_out_I[out_width-1..0]" (rect 183 27 283 39)(font "Arial" ))
|
||||
(line (pt 304 32)(pt 288 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 304 48)
|
||||
(output)
|
||||
(text "data_valid_out_I" (rect 0 0 66 12)(font "Arial" ))
|
||||
(text "data_valid_out_I" (rect 217 43 283 55)(font "Arial" ))
|
||||
(line (pt 304 48)(pt 288 48)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 304 64)
|
||||
(output)
|
||||
(text "data_out_Q[out_width-1..0]" (rect 0 0 105 12)(font "Arial" ))
|
||||
(text "data_out_Q[out_width-1..0]" (rect 178 59 283 71)(font "Arial" ))
|
||||
(line (pt 304 64)(pt 288 64)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 304 80)
|
||||
(output)
|
||||
(text "data_valid_out_Q" (rect 0 0 70 12)(font "Arial" ))
|
||||
(text "data_valid_out_Q" (rect 213 75 283 87)(font "Arial" ))
|
||||
(line (pt 304 80)(pt 288 80)(line_width 1))
|
||||
)
|
||||
(parameter
|
||||
"in_width"
|
||||
"88"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(parameter
|
||||
"out_width"
|
||||
"32"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(drawing
|
||||
(rectangle (rect 16 16 288 128)(line_width 1))
|
||||
)
|
||||
(annotation_block (parameter)(rect 320 -64 420 16))
|
||||
)
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
module data_shifter(
|
||||
input wire [(in_width-1):0] data_in_I,
|
||||
input wire data_valid_I,
|
||||
input wire [(in_width-1):0] data_in_Q,
|
||||
input wire data_valid_Q,
|
||||
input unsigned [7:0] distance,
|
||||
input wire enabled,
|
||||
|
||||
output wire [(out_width-1):0] data_out_I,
|
||||
output wire data_valid_out_I,
|
||||
output wire [(out_width-1):0] data_out_Q,
|
||||
output wire data_valid_out_Q
|
||||
);
|
||||
|
||||
parameter in_width = 88;
|
||||
parameter out_width = 32;
|
||||
|
||||
assign data_valid_out_I = enabled ? data_valid_I : 0;
|
||||
assign data_valid_out_Q = enabled ? data_valid_Q : 0;
|
||||
assign data_out_I[(out_width-1):0] = enabled ? data_in_I[(distance-1) -: out_width] : 0;
|
||||
assign data_out_Q[(out_width-1):0] = enabled ? data_in_Q[(distance-1) -: out_width] : 0;
|
||||
|
||||
endmodule
|
||||
Plik binarny nie jest wyświetlany.
|
|
@ -0,0 +1,96 @@
|
|||
//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=5 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="0" clk1_divide_by=1280 clk1_duty_cycle=50 clk1_multiply_by=1 clk1_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=16276 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=MAIN_PLL" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
|
||||
//VERSION_BEGIN 18.1 cbx_altclkbuf 2018:09:12:13:04:24:SJ cbx_altiobuf_bidir 2018:09:12:13:04:24:SJ cbx_altiobuf_in 2018:09:12:13:04:24:SJ cbx_altiobuf_out 2018:09:12:13:04:24:SJ cbx_altpll 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END
|
||||
//CBXI_INSTANCE_NAME="WOLF_LITE_MAIN_PLL_MAIN_PLL_altpll_altpll_component"
|
||||
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
|
||||
// altera message_off 10463
|
||||
|
||||
|
||||
|
||||
// Copyright (C) 2018 Intel Corporation. All rights reserved.
|
||||
// Your use of Intel Corporation's design tools, logic functions
|
||||
// and other software and tools, and its AMPP partner logic
|
||||
// functions, and any output files from any of the foregoing
|
||||
// (including device programming or simulation files), and any
|
||||
// associated documentation or information are expressly subject
|
||||
// to the terms and conditions of the Intel Program License
|
||||
// Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
// the Intel FPGA IP License Agreement, or other applicable license
|
||||
// agreement, including, without limitation, that your use is for
|
||||
// the sole purpose of programming logic devices manufactured by
|
||||
// Intel and sold by Intel or its authorized distributors. Please
|
||||
// refer to the applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
//synthesis_resources = cycloneive_pll 1
|
||||
//synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
//synopsys translate_on
|
||||
module MAIN_PLL_altpll
|
||||
(
|
||||
clk,
|
||||
inclk) /* synthesis synthesis_clearbox=1 */;
|
||||
output [4:0] clk;
|
||||
input [1:0] inclk;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri0 [1:0] inclk;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [4:0] wire_pll1_clk;
|
||||
wire wire_pll1_fbout;
|
||||
|
||||
cycloneive_pll pll1
|
||||
(
|
||||
.activeclock(),
|
||||
.clk(wire_pll1_clk),
|
||||
.clkbad(),
|
||||
.fbin(wire_pll1_fbout),
|
||||
.fbout(wire_pll1_fbout),
|
||||
.inclk(inclk),
|
||||
.locked(),
|
||||
.phasedone(),
|
||||
.scandataout(),
|
||||
.scandone(),
|
||||
.vcooverrange(),
|
||||
.vcounderrange()
|
||||
`ifndef FORMAL_VERIFICATION
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
,
|
||||
.areset(1'b0),
|
||||
.clkswitch(1'b0),
|
||||
.configupdate(1'b0),
|
||||
.pfdena(1'b1),
|
||||
.phasecounterselect({3{1'b0}}),
|
||||
.phasestep(1'b0),
|
||||
.phaseupdown(1'b0),
|
||||
.scanclk(1'b0),
|
||||
.scanclkena(1'b1),
|
||||
.scandata(1'b0)
|
||||
`ifndef FORMAL_VERIFICATION
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
);
|
||||
defparam
|
||||
pll1.bandwidth_type = "auto",
|
||||
pll1.clk0_divide_by = 5,
|
||||
pll1.clk0_duty_cycle = 50,
|
||||
pll1.clk0_multiply_by = 1,
|
||||
pll1.clk0_phase_shift = "0",
|
||||
pll1.clk1_divide_by = 1280,
|
||||
pll1.clk1_duty_cycle = 50,
|
||||
pll1.clk1_multiply_by = 1,
|
||||
pll1.clk1_phase_shift = "0",
|
||||
pll1.compensate_clock = "clk0",
|
||||
pll1.inclk0_input_frequency = 16276,
|
||||
pll1.operation_mode = "normal",
|
||||
pll1.pll_type = "auto",
|
||||
pll1.lpm_type = "cycloneive_pll";
|
||||
assign
|
||||
clk = {wire_pll1_clk[4:0]};
|
||||
endmodule //MAIN_PLL_altpll
|
||||
//VALID FILE
|
||||
Plik binarny nie jest wyświetlany.
Plik binarny nie jest wyświetlany.
Plik binarny nie jest wyświetlany.
Plik binarny nie jest wyświetlany.
Plik binarny nie jest wyświetlany.
Plik binarny nie jest wyświetlany.
Plik binarny nie jest wyświetlany.
Some files were not shown because too many files have changed in this diff Show More
Ładowanie…
Reference in New Issue