kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
22 wiersze
452 B
Verilog
22 wiersze
452 B
Verilog
// DEBUG2.v
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// Generated using ACDS version 18.1 625
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`timescale 1 ps / 1 ps
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module DEBUG2 (
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input wire [23:0] probe // probes.probe
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);
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altsource_probe_top #(
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.sld_auto_instance_index ("YES"),
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.sld_instance_index (0),
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.instance_id ("DBG2"),
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.probe_width (24),
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.source_width (0),
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.enable_metastability ("NO")
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) in_system_sources_probes_0 (
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.probe (probe) // probes.probe
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);
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endmodule
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