kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
8 wiersze
158 B
Plaintext
8 wiersze
158 B
Plaintext
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component clock_buffer is
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port (
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inclk : in std_logic := 'X'; -- inclk
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outclk : out std_logic -- outclk
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);
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end component clock_buffer;
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