kopia lustrzana https://github.com/jgromes/RadioLib
[SX126x] Added OCP config reset
jgromes
rodzic
2ca26d1a60
commit
e1c79af18b
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@ -6,7 +6,7 @@ SX1262::SX1262(Module* mod) : SX126x(mod) {
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int16_t SX1262::begin(float freq, float bw, uint8_t sf, uint8_t cr, uint16_t syncWord, int8_t power, float currentLimit, uint16_t preambleLength) {
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// execute common part
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int16_t state = SX126x::begin(bw, sf, cr, syncWord, preambleLength);
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int16_t state = SX126x::begin(bw, sf, cr, syncWord, currentLimit, preambleLength);
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if(state != ERR_NONE) {
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return(state);
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}
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@ -22,18 +22,12 @@ int16_t SX1262::begin(float freq, float bw, uint8_t sf, uint8_t cr, uint16_t syn
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return(state);
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}
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// OCP must be configured after PA
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state = SX126x::setCurrentLimit(currentLimit);
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if(state != ERR_NONE) {
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return(state);
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}
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return(state);
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}
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int16_t SX1262::beginFSK(float freq, float br, float freqDev, float rxBw, int8_t power, float currentLimit, uint16_t preambleLength, float dataShaping) {
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// execute common part
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int16_t state = SX126x::beginFSK(br, freqDev, rxBw, preambleLength, dataShaping);
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int16_t state = SX126x::beginFSK(br, freqDev, rxBw, currentLimit, preambleLength, dataShaping);
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if(state != ERR_NONE) {
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return(state);
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}
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@ -49,12 +43,6 @@ int16_t SX1262::beginFSK(float freq, float br, float freqDev, float rxBw, int8_t
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return(state);
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}
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// OCP must be configured after PA
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state = SX126x::setCurrentLimit(currentLimit);
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if(state != ERR_NONE) {
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return(state);
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}
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return(state);
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}
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@ -101,6 +89,13 @@ int16_t SX1262::setOutputPower(int8_t power) {
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return(ERR_INVALID_OUTPUT_POWER);
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}
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// get current OCP configuration
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uint8_t ocp = 0;
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int16_t state = readRegister(SX126X_REG_OCP_CONFIGURATION, &ocp, 1);
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if(state != ERR_NONE) {
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return(state);
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}
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// enable high power PA for output power higher than 14 dBm
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if(power > 13) {
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SX126x::setPaConfig(0x04, SX126X_PA_CONFIG_SX1262);
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@ -111,5 +106,7 @@ int16_t SX1262::setOutputPower(int8_t power) {
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// set output power
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// TODO power ramp time configuration
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SX126x::setTxParams(power);
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return(ERR_NONE);
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// restore OCP configuration
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return(writeRegister(SX126X_REG_OCP_CONFIGURATION, &ocp, 1));
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}
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@ -6,7 +6,7 @@ SX1268::SX1268(Module* mod) : SX126x(mod) {
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int16_t SX1268::begin(float freq, float bw, uint8_t sf, uint8_t cr, uint16_t syncWord, int8_t power, float currentLimit, uint16_t preambleLength) {
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// execute common part
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int16_t state = SX126x::begin(bw, sf, cr, syncWord, preambleLength);
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int16_t state = SX126x::begin(bw, sf, cr, syncWord, currentLimit, preambleLength);
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if(state != ERR_NONE) {
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return(state);
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}
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@ -22,17 +22,11 @@ int16_t SX1268::begin(float freq, float bw, uint8_t sf, uint8_t cr, uint16_t syn
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return(state);
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}
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// OCP must be configured after PA
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state = SX126x::setCurrentLimit(currentLimit);
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if(state != ERR_NONE) {
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return(state);
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}
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return(state);
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}
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int16_t SX1268::beginFSK(float freq, float br, float freqDev, float rxBw, int8_t power, float currentLimit, uint16_t preambleLength, float dataShaping) {
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// execute common part
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int16_t state = SX126x::beginFSK(br, freqDev, rxBw, preambleLength, dataShaping);
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int16_t state = SX126x::beginFSK(br, freqDev, rxBw, currentLimit, preambleLength, dataShaping);
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if(state != ERR_NONE) {
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return(state);
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}
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@ -48,12 +42,6 @@ int16_t SX1268::beginFSK(float freq, float br, float freqDev, float rxBw, int8_t
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return(state);
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}
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// OCP must be configured after PA
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state = SX126x::setCurrentLimit(currentLimit);
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if(state != ERR_NONE) {
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return(state);
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}
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return(state);
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}
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@ -94,11 +82,20 @@ int16_t SX1268::setOutputPower(int8_t power) {
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return(ERR_INVALID_OUTPUT_POWER);
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}
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// get current OCP configuration
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uint8_t ocp = 0;
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int16_t state = readRegister(SX126X_REG_OCP_CONFIGURATION, &ocp, 1);
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if(state != ERR_NONE) {
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return(state);
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}
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// enable high power PA
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SX126x::setPaConfig(0x04, SX126X_PA_CONFIG_SX1268);
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// set output power
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// TODO power ramp time configuration
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SX126x::setTxParams(power);
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return(ERR_NONE);
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// restore OCP configuration
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return(writeRegister(SX126X_REG_OCP_CONFIGURATION, &ocp, 1));
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}
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@ -447,7 +447,10 @@ int16_t SX126x::readData(uint8_t* data, size_t len) {
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}
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// get packet length
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size_t length = getPacketLength();
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size_t length = len;
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if(len == SX126X_MAX_PACKET_LENGTH) {
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length = getPacketLength();
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}
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// read packet data
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int16_t state = readBuffer(data, length);
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@ -774,67 +777,67 @@ int16_t SX126x::disableAddressFiltering() {
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return(setPacketParamsFSK(_preambleLengthFSK, _crcTypeFSK, _syncWordLength, _addrComp));
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}
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int16_t SX126x::setCRC(bool enableCRC) {
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// check active modem
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if(getPacketType() != SX126X_PACKET_TYPE_LORA) {
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return(ERR_WRONG_MODEM);
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}
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// update packet parameters
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if(enableCRC) {
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_crcType = SX126X_LORA_CRC_ON;
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} else {
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_crcType = SX126X_LORA_CRC_OFF;
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}
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return(setPacketParams(_preambleLength, _crcType));
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}
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int16_t SX126x::setCRC(uint8_t len, uint16_t initial, uint16_t polynomial, bool inverted) {
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// check active modem
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if(getPacketType() != SX126X_PACKET_TYPE_GFSK) {
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return(ERR_WRONG_MODEM);
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}
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uint8_t modem = getPacketType();
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if(modem == SX126X_PACKET_TYPE_GFSK) {
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// update packet parameters
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switch(len) {
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case 0:
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_crcTypeFSK = SX126X_GFSK_CRC_OFF;
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break;
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case 1:
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if(inverted) {
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_crcTypeFSK = SX126X_GFSK_CRC_1_BYTE_INV;
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} else {
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_crcTypeFSK = SX126X_GFSK_CRC_1_BYTE;
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}
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break;
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case 2:
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if(inverted) {
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_crcTypeFSK = SX126X_GFSK_CRC_2_BYTE_INV;
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} else {
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_crcTypeFSK = SX126X_GFSK_CRC_2_BYTE;
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}
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break;
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default:
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return(ERR_INVALID_CRC_CONFIGURATION);
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}
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int16_t state = setPacketParamsFSK(_preambleLengthFSK, _crcTypeFSK, _syncWordLength, _addrComp);
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if(state != ERR_NONE) {
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return(state);
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}
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// write initial CRC value
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uint8_t data[2] = {(uint8_t)((initial >> 8) & 0xFF), (uint8_t)(initial & 0xFF)};
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state = writeRegister(SX126X_REG_CRC_INITIAL_MSB, data, 2);
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if(state != ERR_NONE) {
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return(state);
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}
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// write CRC polynomial value
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data[0] = (uint8_t)((polynomial >> 8) & 0xFF);
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data[1] = (uint8_t)(polynomial & 0xFF);
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state = writeRegister(SX126X_REG_CRC_POLYNOMIAL_MSB, data, 2);
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// update packet parameters
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switch(len) {
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case 0:
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_crcTypeFSK = SX126X_GFSK_CRC_OFF;
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break;
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case 1:
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if(inverted) {
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_crcTypeFSK = SX126X_GFSK_CRC_1_BYTE_INV;
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} else {
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_crcTypeFSK = SX126X_GFSK_CRC_1_BYTE;
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}
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break;
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case 2:
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if(inverted) {
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_crcTypeFSK = SX126X_GFSK_CRC_2_BYTE_INV;
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} else {
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_crcTypeFSK = SX126X_GFSK_CRC_2_BYTE;
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}
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break;
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default:
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return(ERR_INVALID_CRC_CONFIGURATION);
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}
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int16_t state = setPacketParamsFSK(_preambleLengthFSK, _crcTypeFSK, _syncWordLength, _addrComp);
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if(state != ERR_NONE) {
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return(state);
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} else if(modem == SX126X_PACKET_TYPE_LORA) {
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// LoRa CRC doesn't allow to set CRC polynomial, inital value, or inversion
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// update packet parameters
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if(len) {
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_crcType = SX126X_LORA_CRC_ON;
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} else {
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_crcType = SX126X_LORA_CRC_OFF;
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}
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return(setPacketParams(_preambleLength, _crcType));
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}
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// write initial CRC value
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uint8_t data[2] = {(uint8_t)((initial >> 8) & 0xFF), (uint8_t)(initial & 0xFF)};
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state = writeRegister(SX126X_REG_CRC_INITIAL_MSB, data, 2);
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if(state != ERR_NONE) {
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return(state);
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}
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// write CRC polynomial value
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data[0] = (uint8_t)((polynomial >> 8) & 0xFF);
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data[1] = (uint8_t)(polynomial & 0xFF);
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state = writeRegister(SX126X_REG_CRC_POLYNOMIAL_MSB, data, 2);
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return(state);
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return(ERR_UNKNOWN);
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}
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float SX126x::getDataRate() {
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@ -944,6 +947,11 @@ int16_t SX126x::writeRegister(uint16_t addr, uint8_t* data, uint8_t numBytes) {
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return(state);
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}
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int16_t SX126x::readRegister(uint16_t addr, uint8_t* data, uint8_t numBytes) {
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uint8_t cmd[] = {SX126X_CMD_READ_REGISTER, (uint8_t)((addr >> 8) & 0xFF), (uint8_t)(addr & 0xFF)};
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return(SX126x::SPItransfer(cmd, 3, false, NULL, data, numBytes, true));
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}
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int16_t SX126x::writeBuffer(uint8_t* data, uint8_t numBytes, uint8_t offset) {
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uint8_t* dat = new uint8_t[1 + numBytes];
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dat[0] = offset;
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@ -1148,14 +1156,16 @@ int16_t SX126x::config(uint8_t modem) {
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}
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int16_t SX126x::SPIwriteCommand(uint8_t cmd, uint8_t* data, uint8_t numBytes, bool waitForBusy) {
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return(SX126x::SPItransfer(cmd, true, data, NULL, numBytes, waitForBusy));
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uint8_t cmdBuffer[] = {cmd};
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return(SX126x::SPItransfer(cmdBuffer, 1, true, data, NULL, numBytes, waitForBusy));
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}
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int16_t SX126x::SPIreadCommand(uint8_t cmd, uint8_t* data, uint8_t numBytes, bool waitForBusy) {
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return(SX126x::SPItransfer(cmd, false, NULL, data, numBytes, waitForBusy));
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uint8_t cmdBuffer[] = {cmd};
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return(SX126x::SPItransfer(cmdBuffer, 1, false, NULL, data, numBytes, waitForBusy));
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}
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int16_t SX126x::SPItransfer(uint8_t cmd, bool write, uint8_t* dataOut, uint8_t* dataIn, uint8_t numBytes, bool waitForBusy) {
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int16_t SX126x::SPItransfer(uint8_t* cmd, uint8_t cmdLen, bool write, uint8_t* dataOut, uint8_t* dataIn, uint8_t numBytes, bool waitForBusy) {
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// get pointer to used SPI interface and the settings
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SPIClass* spi = _mod->getSpi();
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SPISettings spiSettings = _mod->getSpiSettings();
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@ -1168,10 +1178,12 @@ int16_t SX126x::SPItransfer(uint8_t cmd, bool write, uint8_t* dataOut, uint8_t*
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digitalWrite(_mod->getCs(), LOW);
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spi->beginTransaction(spiSettings);
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// send command byte
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spi->transfer(cmd);
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DEBUG_PRINT(cmd, HEX);
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DEBUG_PRINT('\t');
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// send command byte(s)
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for(uint8_t n = 0; n < cmdLen; n++) {
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spi->transfer(cmd[n]);
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DEBUG_PRINT(cmd[n], HEX);
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DEBUG_PRINT('\t');
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}
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// variable to save error during SPI transfer
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uint8_t status = 0;
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@ -351,11 +351,13 @@ class SX126x: public PhysicalLayer {
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\param syncWord 2-byte LoRa sync word.
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\param currentLimit Current protection limit in mA.
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\param preambleLength LoRa preamble length in symbols. Allowed values range from 1 to 65535.
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\returns \ref status_codes
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*/
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int16_t begin(float bw, uint8_t sf, uint8_t cr, uint16_t syncWord, uint16_t preambleLength);
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int16_t begin(float bw, uint8_t sf, uint8_t cr, uint16_t syncWord, float currentLimit, uint16_t preambleLength);
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/*!
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\brief Initialization method for FSK modem.
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@ -366,13 +368,15 @@ class SX126x: public PhysicalLayer {
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\param rxBw Receiver bandwidth in kHz. Allowed values are 4.8, 5.8, 7.3, 9.7, 11.7, 14.6, 19.5, 23.4, 29.3, 39.0, 46.9, 58.6, 78.2, 93.8, 117.3, 156.2, 187.2, 234.3, 312.0, 373.6 and 467.0 kHz.
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\param currentLimit Current protection limit in mA.
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\param preambleLength FSK preamble length in bits. Allowed values range from 0 to 65535.
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\param dataShaping Time-bandwidth product of the Gaussian filter to be used for shaping. Allowed values are 0.3, 0.5, 0.7 and 1.0. Set to 0 to disable shaping.
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\returns \ref status_codes
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*/
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int16_t beginFSK(float br, float freqDev, float rxBw, uint16_t preambleLength, float dataShaping);
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int16_t beginFSK(float br, float freqDev, float rxBw, float currentLimit, uint16_t preambleLength, float dataShaping);
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/*!
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\brief Blocking binary transmit method.
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@ -626,24 +630,15 @@ class SX126x: public PhysicalLayer {
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int16_t disableAddressFiltering();
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/*!
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\brief Sets LoRa CRC.
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\brief Sets CRC configuration.
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\param enableCRC Enable or disable LoRa CRC.
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\param len CRC length in bytes, Allowed values are 1 or 2, set to 0 to disable CRC.
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\returns \ref status_codes
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*/
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int16_t setCRC(bool enableCRC);
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\param initial Initial CRC value. FSK only. Defaults to 0x1D0F (CCIT CRC).
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/*!
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\brief Sets FSK CRC configuration.
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\param polynomial Polynomial for CRC calculation. FSK only. Defaults to 0x1021 (CCIT CRC).
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\param len CRC length in bytes, Allowed values are 1 or 2, set to 0 to disable FSK CRC.
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\param initial Initial CRC value. Defaults to 0x1D0F (CCIT CRC).
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\param polynomial Polynomial for CRC calculation. Defaults to 0x1021 (CCIT CRC).
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\param inverted Invert CRC bytes. Defaults to true (CCIT CRC)
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\param inverted Invert CRC bytes. FSK only. Defaults to true (CCIT CRC).
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\returns \ref status_codes
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*/
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@ -702,6 +697,7 @@ class SX126x: public PhysicalLayer {
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int16_t setCad();
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int16_t setPaConfig(uint8_t paDutyCycle, uint8_t deviceSel, uint8_t hpMax = SX126X_PA_CONFIG_HP_MAX, uint8_t paLut = SX126X_PA_CONFIG_PA_LUT);
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int16_t writeRegister(uint16_t addr, uint8_t* data, uint8_t numBytes);
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int16_t readRegister(uint16_t addr, uint8_t* data, uint8_t numBytes);
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int16_t writeBuffer(uint8_t* data, uint8_t numBytes, uint8_t offset = 0x00);
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int16_t readBuffer(uint8_t* data, uint8_t numBytes);
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int16_t setDioIrqParams(uint16_t irqMask, uint16_t dio1Mask, uint16_t dio2Mask = SX126X_IRQ_NONE, uint16_t dio3Mask = SX126X_IRQ_NONE);
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@ -742,7 +738,7 @@ class SX126x: public PhysicalLayer {
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// common low-level SPI interface
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int16_t SPIwriteCommand(uint8_t cmd, uint8_t* data, uint8_t numBytes, bool waitForBusy = true);
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int16_t SPIreadCommand(uint8_t cmd, uint8_t* data, uint8_t numBytes, bool waitForBusy = true);
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int16_t SPItransfer(uint8_t cmd, bool write, uint8_t* dataOut, uint8_t* dataIn, uint8_t numBytes, bool waitForBusy);
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int16_t SPItransfer(uint8_t* cmd, uint8_t cmdLen, bool write, uint8_t* dataOut, uint8_t* dataIn, uint8_t numBytes, bool waitForBusy);
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};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue