David Banks 4b27164f3c CPLD: Added one cycle of skew to PSYNC ... Change-Id: I18b668e70c148781a5215b55a4e009760984855b		2019-03-08 18:32:41 +00:00
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RGBtoHDMI.jed	CPLD: Re-order bits when rate=1	2019-03-08 13:49:25 +00:00
RGBtoHDMI.ucf	CPLD: final pinout changes	2018-06-12 12:39:06 +01:00
RGBtoHDMI.vhdl	CPLD: Added one cycle of skew to PSYNC	2019-03-08 18:32:41 +00:00
RGBtoHDMI.xise	CPLD: Mostly cosmetic seperation of the logic into several blocks	2018-06-07 17:14:02 +01:00
fitting.notes	CPLD: Allow PSYNC duty cycle to be asymmetric	2019-03-08 16:22:19 +00:00