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1 043 Commity
17 Gałęzie
93 Tagi
20 MiB
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1043 Commity (f5af81592fd104d5faf5cf0c84c89d2b41fe8771)

Autor SHA1 Wiadomość Data
IanSB d9beb1ca86 Update profiles 2019-12-21 01:25:14 +00:00
IanSB 9faef338c3 Add more info in calibration summary 2019-12-21 00:47:55 +00:00
IanSB f0c1ee91b6 Update profiles 2019-12-21 00:47:17 +00:00
IanSB b8698c8464 Fix interlaced bug in sync time measurement 2019-12-20 13:41:29 +00:00
IanSB 9393c011e1 Increase field sync detection duration 2019-12-20 02:53:23 +00:00
IanSB 4da80516d1 Add sync detection test to timing window 2019-12-19 11:56:16 +00:00
IanSB 40bacc6c62 Support for YUV cpld v3.3 with inversions removed 2019-12-18 23:10:47 +00:00
IanSB 7d60e6acdb Update YUV cpld to v3.3 with inversions removed 2019-12-18 23:06:58 +00:00
IanSB a67cecbefc Update profiles 2019-12-18 23:06:14 +00:00
IanSB 2aabf26145 Add support for TI-994a 2019-12-18 16:36:31 +00:00
IanSB e2b9ca4a84 Update profiles 2019-12-18 16:30:33 +00:00
IanSB cb0e74c44e Update YUV CPLD to v3.2 2019-12-18 16:28:01 +00:00
IanSB 9ed150bda6 Fix Atom palette 2019-12-17 04:19:53 +00:00
IanSB 6be11155d1 Update palette generation 2019-12-17 03:56:21 +00:00
IanSB c2bffa1728 Update profiles 2019-12-17 03:54:29 +00:00
IanSB 887c04e2e1 Add support for new RGB/YUV board 2019-12-17 02:38:16 +00:00
IanSB 6df4ddcea5 Update profiles 2019-12-17 02:36:36 +00:00
IanSB a6b397fbc2 Update cpld firmware folder 2019-12-17 02:36:03 +00:00
IanSB f71d171ac6 VHDL release files 2019-12-17 02:35:28 +00:00
IanSB 9076eb238b Update common VHDL with support for new RGB/YUV board (RGB7.1 / YUV3.1) 2019-12-17 02:35:04 +00:00
IanSB 08cbd13df0 YUV CPLD updated to V3.1 for combined RGB/YUV board 2019-12-16 22:45:20 +00:00
IanSB dae265c6f8 Fix off by 1 error in info 2019-12-12 14:13:39 +00:00
IanSB 28dc491e57 Fix autoswitch bug 2019-12-12 13:07:25 +00:00
IanSB 4e97749d28 Code tidyup 2019-12-12 11:41:12 +00:00
IanSB b40825d4a8 Add vertical capture range clipping to avoid capturing during vsync 2019-12-12 05:06:54 +00:00
IanSB 6e5e7f9651 Add h and v out of tolerance detection to cope with Oric startup also inhibit Vsync when analog board connected 2019-12-12 03:17:07 +00:00
IanSB 20647a8ce4 Update Profiles 2019-12-12 03:07:51 +00:00
IanSB 2586b7d4b5 Update Oric Profile 2019-12-11 01:01:52 +00:00
IanSB cb2039d434 Fix whitespace 2019-12-11 00:57:05 +00:00
IanSB e636d9aba8 Add pixel aspect ratio enforcement and fix pi overscan bug 2019-12-10 23:06:53 +00:00
IanSB d1decc73d8 Update profiles 2019-12-10 23:04:41 +00:00
IanSB 54f4b282c8 Resolve conflict 2019-12-08 17:59:17 +00:00
IanSB f08f5e9597 Merge remote-tracking branch 'upstream/dev' into dev 
# Conflicts:
#	src/scripts/Profiles/BBC/BBC_Micro.txt
#	src/scripts/Profiles/BBC/Oric.txt
#	src/scripts/Profiles/BBC/Spectrum 2.txt
 2019-12-08 17:57:59 +00:00
IanSB 8cc1c80ba7 Update profiles 2019-12-08 17:28:58 +00:00
IanSB 7e98924d1c Add Mode 7 scaling option 4:3Uneven/Even 2019-12-08 17:27:20 +00:00
IanSB 48ea152931 Add small overscan for cases where integer scaling doesn't quite fit 2019-12-08 14:50:26 +00:00
IanSB c872ce15da Fix for 4 bit screencap with odd numbered frame buffer width 2019-12-08 05:01:28 +00:00
IanSB 1012ce2d6a Fix screencap fractional scaling 2019-12-08 02:45:40 +00:00
IanSB a1e8929954 rename to kicad_analog_6bit 2019-12-08 00:33:55 +00:00
IanSB ad0474fd1f Issue 2 analog board part2 2019-12-08 00:23:14 +00:00
IanSB e9df50f748 Issue 2 analog board with MAX 5259 2019-12-08 00:22:02 +00:00
IanSB d9c35ae2c4 Fix screencaps in 4bpp mode such as mode 7 2019-12-08 00:11:19 +00:00
IanSB 1a2ff36eb1 Update BBC profile default 2019-12-08 00:10:13 +00:00
IanSB f978f4a650 Update profiles 2019-12-08 00:09:34 +00:00
IanSB 3cd8e05eb0 Add gerbers 2019-12-07 16:04:30 +00:00
David Banks 6516568d12 Added all past versions of CPLD firmware for testing 
Change-Id: I0f003c226e4b92183e85d0b851183e3448149e41
 2019-12-07 15:05:56 +00:00
IanSB 49fd6bee8d Terminator and decoupling caps added plus pcb layout 2019-12-07 13:58:16 +00:00
David Banks 806fcc7dd1 Profiles: Renamed Normal to BBC 
Change-Id: Ic6e07addc559f91e36d47fcba8a98a0c16217bb0
 2019-12-06 12:15:42 +00:00
IanSB bdd0a71823 First attempt at RGB/YUV board with clamp 2019-12-06 11:19:23 +00:00
David Banks 98170366a5 Refactor xilinx projects so vhdl_bbc and vhdl_RGB_6bit share same vhdl/ucf file 
Change-Id: I7c6db57f6b1fe8331dbeaacc81e49e8239349625
 2019-12-05 14:34:59 +00:00