Add h and v out of tolerance detection to cope with Oric startup also inhibit Vsync when analog board connected

pull/116/head
IanSB 2019-12-12 03:17:07 +00:00
rodzic 20647a8ce4
commit 6e5e7f9651
3 zmienionych plików z 34 dodań i 9 usunięć

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@ -146,7 +146,7 @@ static param_t params[] = {
{ LVL_100, "DAC-A (RGB Hi)", "level_100", 0, 255, 1 },
{ LVL_50, "DAC-B (RGB Lo)", "level_50", 0, 255, 1 },
{ LVL_SYNC, "DAC-C (Sync)", "level_sync", 0, 255, 1 },
{ TERMINATE, "DAC-D (Term)", "termination", 0, 1, 1 },
{ TERMINATE, "DAC-D (Term)", "termination", 0, 255, 1 },
{ -1, NULL, NULL, 0, 0, 1 }
};
@ -246,7 +246,7 @@ static void write_config(config_t *config) {
if (sync < 8) sync = 8; // if sync is set too low then sync is just noise which causes software problems
int term = config->terminate;
if (term >= 1) term = 255;
if (term == 1) term = 255;
sendDAC(0, config->lvl_100); // addr 0 + range 0
sendDAC(1, config->lvl_50); // addr 1 + range 0
@ -629,6 +629,9 @@ static int cpld_analyse(int manual_setting) {
polarity ^= ((polarity & SYNC_BIT_VSYNC_INVERTED) ? SYNC_BIT_HSYNC_INVERTED : 0);
polarity |= SYNC_BIT_MIXED_SYNC;
}
if (supports_analog) {
polarity = (polarity & SYNC_BIT_HSYNC_INVERTED) | SYNC_BIT_COMPOSITE_SYNC; // inhibit vsync detection in analog mode as vsync used for other things
}
if (supports_vsync) {
return (polarity);
} else {

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@ -488,9 +488,14 @@ process_line_loop:
pop {r11}
skip_all_lines:
tst r3, #BIT_NO_AUTOSWITCH | BIT_OSD | BIT_CALIBRATE | BIT_PROBE
tst r3, #BIT_OSD | BIT_CALIBRATE | BIT_PROBE
bne skip_sync_time_test
ldr r7, hsync_comparison_lo
ldr r8, hsync_comparison_hi
cmp r7,r8
beq skip_sync_time_test //no sensible window
and r0, r3, #BIT_MODE7
orr r0, #RET_SYNC_TIMING_CHANGED
@ -524,6 +529,10 @@ skip_all_lines:
bgt exit
no_test_half:
tst r3, #BIT_NO_AUTOSWITCH
bne skip_sync_time_test
orr r0, #RET_VSYNC_POLARITY_CHANGED
SWITCH_PSYNC_TO_VSYNC
ldr r8, [r4] // dummy read for delay

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@ -2020,12 +2020,21 @@ void setup_profile() {
// force recalculation of the HDMI clock (if the vlockmode property requires this)
recalculate_hdmi_clock_line_locked_update(GENLOCK_FORCE);
double line_time = (double) clkinfo.line_len * 1000000000 / clkinfo.clock;
double window = (double) clkinfo.clock_ppm * line_time / 1000000;
hsync_comparison_lo = (int) line_time - window;
hsync_comparison_hi = (int) line_time + window;
vsync_comparison_lo = hsync_comparison_lo * clkinfo.lines_per_frame;
vsync_comparison_hi = hsync_comparison_hi * clkinfo.lines_per_frame;
if (autoswitch == AUTOSWITCH_PC) { // set window around expected time for profile
double line_time = (double) clkinfo.line_len * 1000000000 / clkinfo.clock;
double window = (double) clkinfo.clock_ppm * line_time / 1000000;
hsync_comparison_lo = (int) line_time - window;
hsync_comparison_hi = (int) line_time + window;
vsync_comparison_lo = hsync_comparison_lo * clkinfo.lines_per_frame;
vsync_comparison_hi = hsync_comparison_hi * clkinfo.lines_per_frame;
} else { // set window around measured time
double window = (double) clkinfo.clock_ppm * one_line_time_ns / 1000000;
double vwindow = (double) clkinfo.clock_ppm * (vsync_time_ns >> 1) / 1000000;
hsync_comparison_lo = (int) one_line_time_ns - window;
hsync_comparison_hi = (int) one_line_time_ns + window;
vsync_comparison_lo = (int) (vsync_time_ns >> 1) - vwindow;
vsync_comparison_hi = (int) (vsync_time_ns >> 1) + vwindow;
}
log_info("Window: H = %d to %d, V = %d to %d, S = %s", hsync_comparison_lo, hsync_comparison_hi, vsync_comparison_lo, vsync_comparison_hi, sync_names[capinfo->sync_type]);
}
@ -2319,6 +2328,10 @@ int show_detected_status(int line) {
osd_set(line++, 0, message);
sprintf(message, " Sync type: %s", sync_names_long[capinfo->detected_sync_type & SYNC_BIT_MASK]);
osd_set(line++, 0, message);
sprintf(message, " Capture Area: %d x %d", capinfo->chars_per_line << 3, capinfo->nlines << (capinfo->sizex2 & 1) );
osd_set(line++, 0, message);
sprintf(message, " Frame Buffer: %d x %d", capinfo->width, capinfo->height);
osd_set(line++, 0, message);
return (line);
}