IanSB
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f774bbe083
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fix comment
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2020-01-04 06:08:11 +00:00 |
IanSB
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758b48b016
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Update profiles
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2020-01-04 05:34:22 +00:00 |
IanSB
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dd14dbbca5
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YUV CPLD V7.0 with adjustable clamp
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2020-01-04 05:05:16 +00:00 |
David Banks
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d45d2e5d3e
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vhdl_YUV: Revert to original clamp timing (v6.1)
Change-Id: Ica50543ed4acbc4d23ba45cdb5d8011791bb6b39
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2019-12-31 15:31:55 +00:00 |
David Banks
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c0b58c0b53
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vhdl_YUV: Add sync edge and delay to scan chain (v6.0)
Change-Id: I0ad28f87ed9e8b852851b01f026dfba1b2cd9a36
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2019-12-31 11:38:37 +00:00 |
David Banks
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637aaad1cb
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vhdl_YUV: rework design: 63 -> 57 macro cells (v5.A)
Change-Id: Idbcdaf7363d0f705a024d91571c102b34b7b9b5c
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2019-12-31 11:38:37 +00:00 |
David Banks
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554bdcca5b
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vhdl_YUV: rework design: 71 -> 63 macro cells (v5.9)
Change-Id: Ia063eb4da2c3d20220a2e986922caec84686175f
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2019-12-31 11:38:37 +00:00 |
David Banks
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d70b2272d4
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vhdl_YUV: fix hang when sync threshold too low (v5.8)
Change-Id: Icf2cf283d45981e5f3ad9a04a88a56ce18eda003
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2019-12-30 17:52:26 +00:00 |
David Banks
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7a2071cc00
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vhdl_YUV: use the (faster) leading edge of HS as the reference (v57)
Change-Id: I83dd05741ff2f26469f655a3d53923f99917ccce
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2019-12-30 12:08:15 +00:00 |
David Banks
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867dc3126d
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vhdl_YUV: deglitch HS (v5.6)
Change-Id: I60aebd1bec12a2423c415b3f72059136d363e81b
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2019-12-30 09:55:52 +00:00 |
David Banks
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06b6060e39
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vhdl_YUV: fix recent bug in filtering (v5.2)
Change-Id: Ia955e87bcbcd219913bdbed6adf9b234afe9521f
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2019-12-28 18:24:42 +00:00 |
David Banks
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f0d0e0dbf6
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vhdl_YUV: added FS detection (v5.1)
Change-Id: Ib951b4c967b725cbe7b4414e8ec73bd3405188b4
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2019-12-28 17:11:50 +00:00 |
David Banks
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404b1afeef
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vhdl_YUV: Add altnative line R inversion (v5.0)
Change-Id: I230b5c63b37d5e74c736dd24eb24dc7fdede2d0b
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2019-12-28 14:08:04 +00:00 |
David Banks
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b984565bdd
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vhdl_YUV: Reduce macrocell usage (v4.1)
Change-Id: I71bf4d5f3eba5b2db4e539680768b92ab53519d8
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2019-12-28 14:00:25 +00:00 |
David Banks
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4357388a1f
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vhdl_YUV: make chroma subsampling controllable (v4.0)
Change-Id: Id09171473abeb149b0f849d893b89004cae303bb
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2019-12-28 13:58:21 +00:00 |
David Banks
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850703474c
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VHDL: formatting only, remove tabs
Change-Id: I3123b5ab7751c95953b5b5dd889c50c120324b95
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2019-12-22 15:30:38 +00:00 |
IanSB
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7d60e6acdb
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Update YUV cpld to v3.3 with inversions removed
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2019-12-18 23:06:58 +00:00 |
IanSB
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cb0e74c44e
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Update YUV CPLD to v3.2
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2019-12-18 16:28:01 +00:00 |
IanSB
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08cbd13df0
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YUV CPLD updated to V3.1 for combined RGB/YUV board
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2019-12-16 22:45:20 +00:00 |
David Banks
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b7ba4a2da0
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Remove space from directory name
Change-Id: Ia8c60f571a3e7c82951ab447ef8205588f5e11cb
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2019-12-05 13:47:11 +00:00 |