kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
Update rgb_to_fb.S
rodzic
7227d44b56
commit
e141edb8ea
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@ -20,7 +20,6 @@
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mcr p15, 0, r0, c7, c10, 5
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.endm
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.macro READ_CYCLE_COUNTER reg
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#if defined(RPI2) || defined(RPI3)
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mrc p15, 0, \reg, c9, c13, 0
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@ -66,8 +65,8 @@ novsync\@:
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// Flip to the last completed draw buffer
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// It seems the GPU delays this until the next vsync
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push {r0-r3}
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mov r0, r3, lsr #OFFSET_LAST_BUFFER
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and r0, r0, #3
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mov r14, r3, lsr #OFFSET_LAST_BUFFER
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and r0, r14, #3
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bl swapBuffer
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pop {r0-r3}
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noflip\@:
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@ -178,10 +177,9 @@ exitpsync10\@:
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orr r10, r10, r9, lsr #(3 + PIXEL_BASE)
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and r9, r8, #(7 << (PIXEL_BASE + 6))
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and r14, r8, #(7 << (PIXEL_BASE + 9))
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orr r10, r10, r9, lsl #(6 - PIXEL_BASE)
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and r9, r8, #(7 << (PIXEL_BASE + 9))
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orr r10, r10, r9, lsr #(1 + PIXEL_BASE)
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orr r10, r10, r14, lsr #(1 + PIXEL_BASE)
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.endm
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.macro CAPTURE_HIGH_BITS
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@ -191,16 +189,14 @@ exitpsync10\@:
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// Pixel 7 in GPIO 13..11 -> 27..24
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and r9, r8, #(7 << PIXEL_BASE)
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and r14, r8, #(7 << (PIXEL_BASE + 3))
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orr r10, r10, r9, lsl #(20 - PIXEL_BASE)
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and r9, r8, #(7 << (PIXEL_BASE + 3))
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orr r10, r10, r9, lsl #(13 - PIXEL_BASE)
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orr r10, r10, r14, lsl #(13 - PIXEL_BASE)
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and r9, r8, #(7 << (PIXEL_BASE + 6))
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and r14, r8, #(7 << (PIXEL_BASE + 9))
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orr r10, r10, r9, lsl #(22 - PIXEL_BASE)
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and r9, r8, #(7 << (PIXEL_BASE + 9))
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orr r10, r10, r9, lsl #(15 - PIXEL_BASE)
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orr r10, r10, r14, lsl #(15 - PIXEL_BASE)
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.endm
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@ -222,17 +218,16 @@ process_chars_loop\@:
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ldr r8, =0x11111111
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tst r3, #BIT_VSYNC_MARKER
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orrne r10, r10, r8
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str r10, [r12], #4
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// Line double always in Modes 0-6 regardless of interlace
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// On the multi core Pi this introduces stalling artefacts
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#ifndef HAS_MULTICORE
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tst r3, #BIT_SCANLINES
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movne r0, #0
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moveq r0, r10
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str r0, [r12, r2]
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movne r10, #0
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str r10, [r12, r2]
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#endif
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str r10, [r12], #4
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subs r6, r6, #1
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bne process_chars_loop\@
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@ -304,13 +299,12 @@ process_chars_loop_7_simple\@:
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// test for calibration or deinterlace disabled
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// if either branch to skip_deinterlace\@ as deinterlace code messes up the calibration
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tst r3, #(BIT_CALIBRATE | BIT_NO_DEINT)
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and r1, r3, #MASK_INTERLACE
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bne skip_deinterlace_simple\@
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movs r1, r1, lsr #OFFSET_INTERLACE // put interlace setting in R1 0-3: 1 field - 4 fields
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ands r1, r3, #MASK_INTERLACE
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// if setting = 0 then clear 2nd motion flag
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biceq r10, r10, #0x00800000
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mov r1, r1, lsr #OFFSET_INTERLACE // put interlace setting in R1 0-3: 1 field - 4 fields
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cmp r1,#2 // if setting =< 2 then clear 4th motion flag
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bicle r10, r10, #0x00000080
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cmp r1,#1 // if setting =< 1 then clear 3rd motion flag
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@ -388,7 +382,7 @@ process_chars_loop_7\@:
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bic r5, r5, r1 // extract OSD bits
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bic r6, r6, r1
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bic r7, r7, r1
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stmia r14!, {r5, r6, r7} // save for later in cached memory afterwards r14 points to osdbufferA1
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stmia r14, {r5, r6, r7} // save for later in cached memory
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CAPTURE_HIGH_BITS
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add r12, r12, r2
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tst r3, #BIT_OSD
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@ -398,9 +392,10 @@ process_chars_loop_7\@:
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moveq r7,#0
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mov r0, r10 // save left pixel data for later
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WAIT_FOR_PSYNC_10
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sub r12, r12, r2
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adr r14, osdbufferA1
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bic r5, r5, r1 // extract OSD bits
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bic r7, r7, r1 // extract OSD bits
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sub r12, r12, r2
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stmia r14, {r5, r6, r7} // save for later in osdbufferA1 but don't extract OSD bits on r6 as might need half old pixel data
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CAPTURE_LOW_BITS
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add r11, r11, r2 // r11 points to other field
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@ -743,8 +738,8 @@ rgb_to_fb:
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strgt r3, param_chars_per_line
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// Sanity check nlines <= fb_height / 2
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ldr r2, param_nlines
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ldr r3, param_fb_height
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ldr r2, param_nlines
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lsr r3, r3, #1
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cmp r2, r3
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strgt r3, param_nlines
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