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CPLD: Reduce csync de-glitch counter to 2 bits 

Change-Id: I5752c6f15cc8c69a656187a9c94d5172df276586
pull/28/head
David Banks 2018-10-15 21:58:42 +01:00
rodzic a91f915022
commit 7369f6416f
2 zmienionych plików z 24 dodań i 2 usunięć
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4
vhdl/RGBtoHDMI.vhdl
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@ -98,7 +98,7 @@ architecture Behavorial of RGBtoHDMI is
signal csync2 : std_logic;
signal last : std_logic;
signal csync_counter : unsigned(3 downto 0);
signal csync_counter : unsigned(1 downto 0);
-- The sampling counter runs at 96MHz
-- - In modes 0..6 it is 6x the pixel clock
@ -191,7 +191,7 @@ begin
-- output different to input
csync_counter <= csync_counter + 1;
-- if the difference lasts for N-1 cycles, update the output
if csync_counter = 15 then
if csync_counter = 3 then
csync2 <= csync1;
end if;
end if;

22
vhdl/fitting.notes
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@ -322,3 +322,25 @@ FB3 18/18* 29/54 79/90 9/ 9*
FB4 18/18* 46/54 71/90 5/ 7
----- ----- ----- -----
70/72 131/216 229/360 28/34
29. Reduce csync de-glitch counter to 3 bits
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 31/54 45/90 6/ 9
FB2 16/18 25/54 34/90 8/ 9
FB3 18/18* 29/54 79/90 9/ 9*
FB4 17/18 45/54 67/90 5/ 7
----- ----- ----- -----
69/72 130/216 225/360 28/34
30. Reduce csync de-glitch counter to 2 bits
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 31/54 45/90 6/ 9
FB2 16/18 25/54 34/90 8/ 9
FB3 18/18* 29/54 79/90 9/ 9*
FB4 16/18 44/54 63/90 5/ 7
----- ----- ----- -----
68/72 129/216 221/360 28/34