From 7369f6416f0e809c11738ebb999d535a457cf6be Mon Sep 17 00:00:00 2001 From: David Banks Date: Mon, 15 Oct 2018 21:58:42 +0100 Subject: [PATCH] CPLD: Reduce csync de-glitch counter to 2 bits Change-Id: I5752c6f15cc8c69a656187a9c94d5172df276586 --- vhdl/RGBtoHDMI.vhdl | 4 ++-- vhdl/fitting.notes | 22 ++++++++++++++++++++++ 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/vhdl/RGBtoHDMI.vhdl b/vhdl/RGBtoHDMI.vhdl index ca918143..c43b6379 100644 --- a/vhdl/RGBtoHDMI.vhdl +++ b/vhdl/RGBtoHDMI.vhdl @@ -98,7 +98,7 @@ architecture Behavorial of RGBtoHDMI is signal csync2 : std_logic; signal last : std_logic; - signal csync_counter : unsigned(3 downto 0); + signal csync_counter : unsigned(1 downto 0); -- The sampling counter runs at 96MHz -- - In modes 0..6 it is 6x the pixel clock @@ -191,7 +191,7 @@ begin -- output different to input csync_counter <= csync_counter + 1; -- if the difference lasts for N-1 cycles, update the output - if csync_counter = 15 then + if csync_counter = 3 then csync2 <= csync1; end if; end if; diff --git a/vhdl/fitting.notes b/vhdl/fitting.notes index 4307ce66..534a9214 100644 --- a/vhdl/fitting.notes +++ b/vhdl/fitting.notes @@ -322,3 +322,25 @@ FB3 18/18* 29/54 79/90 9/ 9* FB4 18/18* 46/54 71/90 5/ 7 ----- ----- ----- ----- 70/72 131/216 229/360 28/34 + +29. Reduce csync de-glitch counter to 3 bits + +Function Mcells FB Inps Pterms IO +Block Used/Tot Used/Tot Used/Tot Used/Tot +FB1 18/18* 31/54 45/90 6/ 9 +FB2 16/18 25/54 34/90 8/ 9 +FB3 18/18* 29/54 79/90 9/ 9* +FB4 17/18 45/54 67/90 5/ 7 + ----- ----- ----- ----- + 69/72 130/216 225/360 28/34 + +30. Reduce csync de-glitch counter to 2 bits + +Function Mcells FB Inps Pterms IO +Block Used/Tot Used/Tot Used/Tot Used/Tot +FB1 18/18* 31/54 45/90 6/ 9 +FB2 16/18 25/54 34/90 8/ 9 +FB3 18/18* 29/54 79/90 9/ 9* +FB4 16/18 44/54 63/90 5/ 7 + ----- ----- ----- ----- + 68/72 129/216 221/360 28/34