kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
VHDL: idle psync should be zero
Change-Id: I3422fb75376be0c3a29e8f02b5019910e9c84614issue_1022
rodzic
140b89d311
commit
6c519cdc29
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@ -84,6 +84,7 @@ begin
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if nCSYNC1 = '0' then
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-- within horizontal line sync pulse
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hsync <= '1';
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psync <= '0';
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counter <= to_unsigned(1311, counter'length);
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else
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-- within the line
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@ -103,7 +104,7 @@ begin
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end if;
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else
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quad <= (others => '0');
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psync <= '1';
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psync <= '0';
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end if;
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end if;
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end if;
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