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CPLD: Corrected sampling offset to better centre screen; CPLD version now 0.9 

Change-Id: I2ef25e2bda982080329deaf6569299c695d7ee1d
issue_1022
David Banks 2018-07-15 11:35:30 +01:00
rodzic a58f10d0d7
commit 6982b3149a
2 zmienionych plików z 28 dodań i 26 usunięć
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27
vhdl/RGBtoHDMI.vhdl
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@ -52,34 +52,35 @@ architecture Behavorial of RGBtoHDMI is
-- Version number: Design_Major_Minor -- Version number: Design_Major_Minor
-- Design: 0 = Normal CPLD, 1 = Alternative CPLD -- Design: 0 = Normal CPLD, 1 = Alternative CPLD
constant VERSION_NUM : std_logic_vector(11 downto 0) := x"001"; constant VERSION_NUM : std_logic_vector(11 downto 0) := x"009";
-- Measured values (trailing edge of HS to active display) -- Measured values (trailing edge of HS to active display)
-- Mode 0: 11.484us -- Mode 0: 11.484us
-- Mode 1: 11.546us ( +1 16MHz cycles) -- Mode 1: 11.546us ( +1 16MHz cycles / +6 96MHz cycles)
-- Mode 2: 11.671us ( +3 16MHz cycles) -- Mode 2: 11.671us ( +3 16MHz cycles / +18 96MHz cycles)
-- Mode 3: 11.484us -- Mode 3: 11.484us
-- Mode 4: 12.047us ( +9 16MHz cycles) -- Mode 4: 12.047us ( +9 16MHz cycles / +54 96MHz cycles)
-- Mode 5: 12.171us (+11 16MHz cycles) -- Mode 5: 12.171us (+11 16MHz cycles / +66 96MHz cycles)
-- Mode 6: 12.046us ( +9 16MHz cycles) -- Mode 6: 12.046us ( +9 16MHz cycles / +54 96MHz cycles)
-- Mode 7: 13.200us -- Mode 7: 13.200us
-- --
-- Mode 0-6 FB is 672px wide (cf 640 active pixels) -- Mode 0-6 FB is 672px wide (cf 640 active pixels)
-- 16 extra "16MHz" pixels at each side -- (ideally) 16 extra "16MHz" pixels at each side
-- 1us extra at each side -- 96 extra "96MHz" cycles at each side
-- start samping at 11.33us -- i.e. 1us extra at each side
-- == 96 * 11.33 == 1088 (must be a multiple of 8) -- => start samping at 10.50us
-- == 96 * 10.50 == 1008 (must be a multiple of 8)
-- --
-- Mode 7 FB is is 504px wide (cf 480 active pixels) -- Mode 7 FB is is 504px wide (cf 480 active pixels)
-- 12 extra pixels "12Mhz" pixels at each side -- (ideally) 12 extra pixels "12Mhz" pixels at each side
-- 1us extra at each side -- 1us extra at each side
-- start samping at 12.25us -- start samping at 12.25us
-- == 96 * 12.25 == 1176 (must be a multiple of 8) -- == 96 * 12.25 == 1176 (must be a multiple of 8)
-- For Modes 0..6 -- For Modes 0..6
constant default_offset_A : unsigned(11 downto 0) := to_unsigned(4096 - 1088, 12); constant default_offset_A : unsigned(11 downto 0) := to_unsigned(4096 - 1008, 12);
-- Offset B adds half a 16MHz pixel -- Offset B adds half a 16MHz pixel
constant default_offset_B : unsigned(11 downto 0) := to_unsigned(4096 - 1088 + 3, 12); constant default_offset_B : unsigned(11 downto 0) := to_unsigned(4096 - 1008 + 3, 12);
-- For Mode 7 -- For Mode 7
constant mode7_offset_A : unsigned(11 downto 0) := to_unsigned(4096 - 1176, 12); constant mode7_offset_A : unsigned(11 downto 0) := to_unsigned(4096 - 1176, 12);

27
vhdl_alt/RGBtoHDMI.vhdl
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@ -52,34 +52,35 @@ architecture Behavorial of RGBtoHDMI is
-- Version number: Design_Major_Minor -- Version number: Design_Major_Minor
-- Design: 0 = Normal CPLD, 1 = Alternative CPLD -- Design: 0 = Normal CPLD, 1 = Alternative CPLD
constant VERSION_NUM : std_logic_vector(11 downto 0) := x"101"; constant VERSION_NUM : std_logic_vector(11 downto 0) := x"109";
-- Measured values (trailing edge of HS to active display) -- Measured values (trailing edge of HS to active display)
-- Mode 0: 11.484us -- Mode 0: 11.484us
-- Mode 1: 11.546us ( +1 16MHz cycles) -- Mode 1: 11.546us ( +1 16MHz cycles / +6 96MHz cycles)
-- Mode 2: 11.671us ( +3 16MHz cycles) -- Mode 2: 11.671us ( +3 16MHz cycles / +18 96MHz cycles)
-- Mode 3: 11.484us -- Mode 3: 11.484us
-- Mode 4: 12.047us ( +9 16MHz cycles) -- Mode 4: 12.047us ( +9 16MHz cycles / +54 96MHz cycles)
-- Mode 5: 12.171us (+11 16MHz cycles) -- Mode 5: 12.171us (+11 16MHz cycles / +66 96MHz cycles)
-- Mode 6: 12.046us ( +9 16MHz cycles) -- Mode 6: 12.046us ( +9 16MHz cycles / +54 96MHz cycles)
-- Mode 7: 13.200us -- Mode 7: 13.200us
-- --
-- Mode 0-6 FB is 672px wide (cf 640 active pixels) -- Mode 0-6 FB is 672px wide (cf 640 active pixels)
-- 16 extra "16MHz" pixels at each side -- (ideally) 16 extra "16MHz" pixels at each side
-- 1us extra at each side -- 96 extra "96MHz" cycles at each side
-- start samping at 11.33us -- i.e. 1us extra at each side
-- == 96 * 11.33 == 1088 (must be a multiple of 8) -- => start samping at 10.50us
-- == 96 * 10.50 == 1008 (must be a multiple of 8)
-- --
-- Mode 7 FB is is 504px wide (cf 480 active pixels) -- Mode 7 FB is is 504px wide (cf 480 active pixels)
-- 12 extra pixels "12Mhz" pixels at each side -- (ideally) 12 extra pixels "12Mhz" pixels at each side
-- 1us extra at each side -- 1us extra at each side
-- start samping at 12.25us -- start samping at 12.25us
-- == 96 * 12.25 == 1176 (must be a multiple of 8) -- == 96 * 12.25 == 1176 (must be a multiple of 8)
-- For Modes 0..6 -- For Modes 0..6
constant default_offset_A : unsigned(11 downto 0) := to_unsigned(4096 - 1088, 12); constant default_offset_A : unsigned(11 downto 0) := to_unsigned(4096 - 1008, 12);
-- Offset B adds half a 16MHz pixel -- Offset B adds half a 16MHz pixel
constant default_offset_B : unsigned(11 downto 0) := to_unsigned(4096 - 1088 + 3, 12); constant default_offset_B : unsigned(11 downto 0) := to_unsigned(4096 - 1008 + 3, 12);
-- For Mode 7 -- For Mode 7
constant mode7_offset_A : unsigned(11 downto 0) := to_unsigned(4096 - 1176, 12); constant mode7_offset_A : unsigned(11 downto 0) := to_unsigned(4096 - 1176, 12);