From 6982b3149accd2523bbb3dd5b13f060da56c2cd9 Mon Sep 17 00:00:00 2001 From: David Banks Date: Sun, 15 Jul 2018 11:35:30 +0100 Subject: [PATCH] CPLD: Corrected sampling offset to better centre screen; CPLD version now 0.9 Change-Id: I2ef25e2bda982080329deaf6569299c695d7ee1d --- vhdl/RGBtoHDMI.vhdl | 27 ++++++++++++++------------- vhdl_alt/RGBtoHDMI.vhdl | 27 ++++++++++++++------------- 2 files changed, 28 insertions(+), 26 deletions(-) diff --git a/vhdl/RGBtoHDMI.vhdl b/vhdl/RGBtoHDMI.vhdl index f7f6affc..7e7df360 100644 --- a/vhdl/RGBtoHDMI.vhdl +++ b/vhdl/RGBtoHDMI.vhdl @@ -52,34 +52,35 @@ architecture Behavorial of RGBtoHDMI is -- Version number: Design_Major_Minor -- Design: 0 = Normal CPLD, 1 = Alternative CPLD - constant VERSION_NUM : std_logic_vector(11 downto 0) := x"001"; + constant VERSION_NUM : std_logic_vector(11 downto 0) := x"009"; -- Measured values (trailing edge of HS to active display) -- Mode 0: 11.484us - -- Mode 1: 11.546us ( +1 16MHz cycles) - -- Mode 2: 11.671us ( +3 16MHz cycles) + -- Mode 1: 11.546us ( +1 16MHz cycles / +6 96MHz cycles) + -- Mode 2: 11.671us ( +3 16MHz cycles / +18 96MHz cycles) -- Mode 3: 11.484us - -- Mode 4: 12.047us ( +9 16MHz cycles) - -- Mode 5: 12.171us (+11 16MHz cycles) - -- Mode 6: 12.046us ( +9 16MHz cycles) + -- Mode 4: 12.047us ( +9 16MHz cycles / +54 96MHz cycles) + -- Mode 5: 12.171us (+11 16MHz cycles / +66 96MHz cycles) + -- Mode 6: 12.046us ( +9 16MHz cycles / +54 96MHz cycles) -- Mode 7: 13.200us -- -- Mode 0-6 FB is 672px wide (cf 640 active pixels) - -- 16 extra "16MHz" pixels at each side - -- 1us extra at each side - -- start samping at 11.33us - -- == 96 * 11.33 == 1088 (must be a multiple of 8) + -- (ideally) 16 extra "16MHz" pixels at each side + -- 96 extra "96MHz" cycles at each side + -- i.e. 1us extra at each side + -- => start samping at 10.50us + -- == 96 * 10.50 == 1008 (must be a multiple of 8) -- -- Mode 7 FB is is 504px wide (cf 480 active pixels) - -- 12 extra pixels "12Mhz" pixels at each side + -- (ideally) 12 extra pixels "12Mhz" pixels at each side -- 1us extra at each side -- start samping at 12.25us -- == 96 * 12.25 == 1176 (must be a multiple of 8) -- For Modes 0..6 - constant default_offset_A : unsigned(11 downto 0) := to_unsigned(4096 - 1088, 12); + constant default_offset_A : unsigned(11 downto 0) := to_unsigned(4096 - 1008, 12); -- Offset B adds half a 16MHz pixel - constant default_offset_B : unsigned(11 downto 0) := to_unsigned(4096 - 1088 + 3, 12); + constant default_offset_B : unsigned(11 downto 0) := to_unsigned(4096 - 1008 + 3, 12); -- For Mode 7 constant mode7_offset_A : unsigned(11 downto 0) := to_unsigned(4096 - 1176, 12); diff --git a/vhdl_alt/RGBtoHDMI.vhdl b/vhdl_alt/RGBtoHDMI.vhdl index c8ede284..88068e6b 100644 --- a/vhdl_alt/RGBtoHDMI.vhdl +++ b/vhdl_alt/RGBtoHDMI.vhdl @@ -52,34 +52,35 @@ architecture Behavorial of RGBtoHDMI is -- Version number: Design_Major_Minor -- Design: 0 = Normal CPLD, 1 = Alternative CPLD - constant VERSION_NUM : std_logic_vector(11 downto 0) := x"101"; + constant VERSION_NUM : std_logic_vector(11 downto 0) := x"109"; -- Measured values (trailing edge of HS to active display) -- Mode 0: 11.484us - -- Mode 1: 11.546us ( +1 16MHz cycles) - -- Mode 2: 11.671us ( +3 16MHz cycles) + -- Mode 1: 11.546us ( +1 16MHz cycles / +6 96MHz cycles) + -- Mode 2: 11.671us ( +3 16MHz cycles / +18 96MHz cycles) -- Mode 3: 11.484us - -- Mode 4: 12.047us ( +9 16MHz cycles) - -- Mode 5: 12.171us (+11 16MHz cycles) - -- Mode 6: 12.046us ( +9 16MHz cycles) + -- Mode 4: 12.047us ( +9 16MHz cycles / +54 96MHz cycles) + -- Mode 5: 12.171us (+11 16MHz cycles / +66 96MHz cycles) + -- Mode 6: 12.046us ( +9 16MHz cycles / +54 96MHz cycles) -- Mode 7: 13.200us -- -- Mode 0-6 FB is 672px wide (cf 640 active pixels) - -- 16 extra "16MHz" pixels at each side - -- 1us extra at each side - -- start samping at 11.33us - -- == 96 * 11.33 == 1088 (must be a multiple of 8) + -- (ideally) 16 extra "16MHz" pixels at each side + -- 96 extra "96MHz" cycles at each side + -- i.e. 1us extra at each side + -- => start samping at 10.50us + -- == 96 * 10.50 == 1008 (must be a multiple of 8) -- -- Mode 7 FB is is 504px wide (cf 480 active pixels) - -- 12 extra pixels "12Mhz" pixels at each side + -- (ideally) 12 extra pixels "12Mhz" pixels at each side -- 1us extra at each side -- start samping at 12.25us -- == 96 * 12.25 == 1176 (must be a multiple of 8) -- For Modes 0..6 - constant default_offset_A : unsigned(11 downto 0) := to_unsigned(4096 - 1088, 12); + constant default_offset_A : unsigned(11 downto 0) := to_unsigned(4096 - 1008, 12); -- Offset B adds half a 16MHz pixel - constant default_offset_B : unsigned(11 downto 0) := to_unsigned(4096 - 1088 + 3, 12); + constant default_offset_B : unsigned(11 downto 0) := to_unsigned(4096 - 1008 + 3, 12); -- For Mode 7 constant mode7_offset_A : unsigned(11 downto 0) := to_unsigned(4096 - 1176, 12);