kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
CPLD: Updated to pinout from PCB based design
Change-Id: Ia13272589b9886c587bef7645dd2ee0809ac1e7fdev2
David Banks
rodzic
5723f48f92
commit
65b90f2ba4
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@ -5,36 +5,41 @@ NET "clk" BUFG=CLK;
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NET "clk" TNM_NET = clk_period_grp_1;
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TIMESPEC TS_clk_period_1 = PERIOD "clk_period_grp_1" 10.4ns HIGH;
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NET "clk" LOC = "P43"; # input
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NET "clk" LOC = "P43"; # input gpio21
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NET "R" LOC = "P12"; # input
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NET "G" LOC = "P13"; # input
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NET "B" LOC = "P14"; # input
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NET "S" LOC = "P16"; # input
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NET "SW" LOC = "P18"; # input
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NET "R0" LOC = "P33"; # input
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NET "G0" LOC = "P32"; # input
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NET "B0" LOC = "P31"; # input
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NET "R1" LOC = "P34"; # input
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NET "G1" LOC = "P36"; # input
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NET "B1" LOC = "P37"; # input
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NET "S" LOC = "P30"; # input
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NET "SW" LOC = "P39"; # input
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NET "mode7" LOC = "P19"; # input
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NET "sp_clk" LOC = "P1"; # input
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NET "sp_data" LOC = "P2"; # input
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NET "SWout" LOC = "P3"; # output
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NET "test" LOC = "P40"; # output
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NET "mode7" LOC = "P19"; # input gpio22
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NET "elk" LOC = "P21"; # input gpio27, also LED1
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NET "sp_clk" LOC = "P44"; # input gpio20
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NET "sp_data" LOC = "P20"; # input gpio23
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NET "quad(0)" LOC = "P37"; # output
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NET "quad(1)" LOC = "P36"; # output
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NET "quad(2)" LOC = "P34"; # output
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NET "quad(3)" LOC = "P23"; # output
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NET "quad(4)" LOC = "P22"; # output
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NET "quad(5)" LOC = "P27"; # output
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NET "quad(6)" LOC = "P28"; # output
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NET "quad(7)" LOC = "P30"; # output
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NET "quad(8)" LOC = "P31"; # output
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NET "quad(9)" LOC = "P29"; # output
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NET "quad(10)" LOC = "P21"; # output
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NET "quad(11)" LOC = "P20"; # output
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NET "psync" LOC = "P33"; # output
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NET "csync" LOC = "P32"; # output
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NET "LED1" LOC = "P39"; # output
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NET "LED2" LOC = "P38"; # output
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NET "SWout" LOC = "P2"; # output gpio16
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# LOC = "P18"; # gpio24 spare
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NET "quad(0)" LOC = "P29"; # output gpio2
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NET "quad(1)" LOC = "P28"; # output gpio3
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NET "quad(2)" LOC = "P27"; # output gpio4
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NET "quad(3)" LOC = "P7"; # output gpio5
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NET "quad(4)" LOC = "P5"; # output gpio6
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NET "quad(5)" LOC = "P8"; # output gpio7
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NET "quad(6)" LOC = "P12"; # output gpio8
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NET "quad(7)" LOC = "P14"; # output gpio9
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NET "quad(8)" LOC = "P16"; # output gpio10
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NET "quad(9)" LOC = "P13"; # output gpio11
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NET "quad(10)" LOC = "P6"; # output gpio12
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NET "quad(11)" LOC = "P3"; # output gpio13
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NET "psync" LOC = "P22"; # output gpio17
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NET "csync" LOC = "P23"; # output gpio18
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NET "LED" LOC = "P38"; # output to LED2
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NET "quad(0)" SLOW;
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NET "quad(1)" SLOW;
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@ -50,5 +55,5 @@ NET "quad(10)" SLOW;
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NET "quad(11)" SLOW;
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NET "psync" SLOW;
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NET "csync" SLOW;
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NET "LED1" SLOW;
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NET "LED2" SLOW;
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NET "LED" SLOW;
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NET "SWout" SLOW;
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@ -16,14 +16,18 @@ use ieee.numeric_std.all;
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entity RGBtoHDMI is
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Port (
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-- From Beeb RGB Connector
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R: in std_logic;
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G: in std_logic;
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B: in std_logic;
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R0: in std_logic;
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G0: in std_logic;
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B0: in std_logic;
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R1: in std_logic;
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G1: in std_logic;
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B1: in std_logic;
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S: in std_logic;
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-- From Pi
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clk: in std_logic;
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mode7: in std_logic;
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elk: in std_logic;
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sp_clk: in std_logic;
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sp_data: in std_logic;
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@ -33,11 +37,9 @@ entity RGBtoHDMI is
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csync: out std_logic;
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SWout: out std_logic;
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-- Test
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-- User interface
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SW: in std_logic;
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LED1: out std_logic;
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LED2: out std_logic;
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test: out std_logic
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LED: out std_logic
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);
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end RGBtoHDMI;
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@ -71,9 +73,6 @@ architecture Behavorial of RGBtoHDMI is
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signal counter2 : unsigned(5 downto 3);
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-- Hsync is every 64us
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--signal led_counter : unsigned(12 downto 0);
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-- Sample point register;
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--
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-- In Modes 0..6 each pixel lasts 6 clocks (96MHz / 16MHz). The original
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@ -99,16 +98,17 @@ architecture Behavorial of RGBtoHDMI is
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signal sp_index : std_logic_vector(2 downto 0);
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-- Sample pixel on next clock; pipelined to reducethe number of product terms
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signal sample : std_logic;
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signal sample : std_logic;
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signal R : std_logic;
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signal G : std_logic;
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signal B : std_logic;
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begin
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-- process(S)
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-- begin
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-- if rising_edge(S) then
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-- led_counter <= led_counter + 1;
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-- end if;
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-- end process;
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R <= R1 when elk = '1' else R0;
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G <= G1 when elk = '1' else G0;
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B <= B1 when elk = '1' else B0;
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mode7_sp_A <= sp_reg(2 downto 0);
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mode7_sp_B <= sp_reg(5 downto 3);
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@ -212,14 +212,10 @@ begin
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end if;
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end process;
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csync <= S;
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csync <= CSYNC1;
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LED1 <= mode7;
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--LED2 <= led_counter(led_counter'left);
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LED <= mode7;
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SWOut <= SW;
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test <= sample;
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end Behavorial;
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@ -0,0 +1,9 @@
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 16/18 33/54 62/90 6/ 9
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FB2 18/18* 25/54 34/90 5/ 9
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FB3 18/18* 35/54 61/90 8/ 9
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FB4 18/18* 37/54 58/90 4/ 7
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----- ----- ----- -----
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70/72 130/216 215/360 23/34
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@ -0,0 +1,125 @@
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1. Original design:
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 27/54 69/90 6/ 9
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FB2 18/18* 34/54 60/90 8/ 9
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FB3 18/18* 19/54 32/90 5/ 9
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FB4 18/18* 37/54 56/90 7/ 7*
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----- ----- ----- -----
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72/72 117/216 217/360 26/34
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2. New design, with RGB mux, switch pass throughs, etc commented out
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(failed to map sp_reg<9>, hence one less macrocell)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 26/54 51/90 7/ 9
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FB2 18/18* 25/54 33/90 6/ 9
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FB3 18/18* 35/54 61/90 8/ 9
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FB4 17/18 53/54 70/90 4/ 7
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----- ----- ----- -----
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71/72 139/216 215/360 25/34
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3. Change from csync=>S to csync=>CSYNC1 (as passthroughs still use up a macro cell).
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(now fits)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 17/18 33/54 64/90 7/ 9
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FB2 18/18* 25/54 33/90 6/ 9
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FB3 18/18* 35/54 61/90 8/ 9
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FB4 18/18* 37/54 58/90 4/ 7
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----- ----- ----- -----
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71/72 130/216 216/360 25/34
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4. Add in RGB mux:
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(still fits)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 17/18 33/54 64/90 7/ 9
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FB2 18/18* 25/54 33/90 9/ 9*
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FB3 18/18* 37/54 61/90 8/ 9
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FB4 18/18* 41/54 61/90 5/ 7
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----- ----- ----- -----
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71/72 136/216 219/360 29/34
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5. Add in SW2out <= SW2:
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(still fits)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 28/54 62/90 8/ 9
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FB2 18/18* 25/54 33/90 9/ 9*
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FB3 18/18* 37/54 61/90 8/ 9
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FB4 18/18* 48/54 64/90 6/ 7
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----- ----- ----- -----
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72/72 138/216 220/360 31/34
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6. Change to optimization effort normal->high:
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(no difference)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 28/54 62/90 8/ 9
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FB2 18/18* 25/54 33/90 9/ 9*
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FB3 18/18* 37/54 61/90 8/ 9
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FB4 18/18* 48/54 64/90 6/ 7
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----- ----- ----- -----
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72/72 138/216 220/360 31/34
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7. Change to optimization effort speed->area:
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(no difference)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 28/54 62/90 8/ 9
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FB2 18/18* 25/54 33/90 9/ 9*
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FB3 18/18* 37/54 61/90 8/ 9
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FB4 18/18* 48/54 64/90 6/ 7
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----- ----- ----- -----
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72/72 138/216 220/360 31/34
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8. Fitter Implmenetation Template: Optimize Balance-> Optimize Speed:
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(no difference)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 28/54 62/90 8/ 9
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FB2 18/18* 25/54 33/90 9/ 9*
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FB3 18/18* 37/54 61/90 8/ 9
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FB4 18/18* 48/54 64/90 6/ 7
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----- ----- ----- -----
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72/72 138/216 220/360 31/34
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9. Fitter Implmenetation Template: Optimize Speed -> Optimize Density:
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(no difference)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 28/54 62/90 8/ 9
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FB2 18/18* 25/54 33/90 9/ 9*
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FB3 18/18* 37/54 61/90 8/ 9
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FB4 18/18* 48/54 64/90 6/ 7
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----- ----- ----- -----
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72/72 138/216 220/360 31/34
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10. Reverted to original .xise file
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Cleaned up design to remove SW2/3 pass throughs
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Used gpio22/23 for mode7 / sp_data
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Used gpio19/26 for sw2/3 (not via cpld)
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(same result as 4 above)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 17/18 33/54 64/90 5/ 9
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FB2 18/18* 25/54 33/90 9/ 9*
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FB3 18/18* 37/54 61/90 8/ 9
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FB4 18/18* 41/54 61/90 7/ 7*
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----- ----- ----- -----
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71/72 136/216 219/360 29/34
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