diff --git a/vhdl/RGBtoHDMI.ucf b/vhdl/RGBtoHDMI.ucf index 7ff44cfc..82bc818f 100644 --- a/vhdl/RGBtoHDMI.ucf +++ b/vhdl/RGBtoHDMI.ucf @@ -5,36 +5,41 @@ NET "clk" BUFG=CLK; NET "clk" TNM_NET = clk_period_grp_1; TIMESPEC TS_clk_period_1 = PERIOD "clk_period_grp_1" 10.4ns HIGH; -NET "clk" LOC = "P43"; # input +NET "clk" LOC = "P43"; # input gpio21 -NET "R" LOC = "P12"; # input -NET "G" LOC = "P13"; # input -NET "B" LOC = "P14"; # input -NET "S" LOC = "P16"; # input -NET "SW" LOC = "P18"; # input +NET "R0" LOC = "P33"; # input +NET "G0" LOC = "P32"; # input +NET "B0" LOC = "P31"; # input +NET "R1" LOC = "P34"; # input +NET "G1" LOC = "P36"; # input +NET "B1" LOC = "P37"; # input +NET "S" LOC = "P30"; # input +NET "SW" LOC = "P39"; # input -NET "mode7" LOC = "P19"; # input -NET "sp_clk" LOC = "P1"; # input -NET "sp_data" LOC = "P2"; # input -NET "SWout" LOC = "P3"; # output -NET "test" LOC = "P40"; # output +NET "mode7" LOC = "P19"; # input gpio22 +NET "elk" LOC = "P21"; # input gpio27, also LED1 +NET "sp_clk" LOC = "P44"; # input gpio20 +NET "sp_data" LOC = "P20"; # input gpio23 -NET "quad(0)" LOC = "P37"; # output -NET "quad(1)" LOC = "P36"; # output -NET "quad(2)" LOC = "P34"; # output -NET "quad(3)" LOC = "P23"; # output -NET "quad(4)" LOC = "P22"; # output -NET "quad(5)" LOC = "P27"; # output -NET "quad(6)" LOC = "P28"; # output -NET "quad(7)" LOC = "P30"; # output -NET "quad(8)" LOC = "P31"; # output -NET "quad(9)" LOC = "P29"; # output -NET "quad(10)" LOC = "P21"; # output -NET "quad(11)" LOC = "P20"; # output -NET "psync" LOC = "P33"; # output -NET "csync" LOC = "P32"; # output -NET "LED1" LOC = "P39"; # output -NET "LED2" LOC = "P38"; # output +NET "SWout" LOC = "P2"; # output gpio16 + +# LOC = "P18"; # gpio24 spare + +NET "quad(0)" LOC = "P29"; # output gpio2 +NET "quad(1)" LOC = "P28"; # output gpio3 +NET "quad(2)" LOC = "P27"; # output gpio4 +NET "quad(3)" LOC = "P7"; # output gpio5 +NET "quad(4)" LOC = "P5"; # output gpio6 +NET "quad(5)" LOC = "P8"; # output gpio7 +NET "quad(6)" LOC = "P12"; # output gpio8 +NET "quad(7)" LOC = "P14"; # output gpio9 +NET "quad(8)" LOC = "P16"; # output gpio10 +NET "quad(9)" LOC = "P13"; # output gpio11 +NET "quad(10)" LOC = "P6"; # output gpio12 +NET "quad(11)" LOC = "P3"; # output gpio13 +NET "psync" LOC = "P22"; # output gpio17 +NET "csync" LOC = "P23"; # output gpio18 +NET "LED" LOC = "P38"; # output to LED2 NET "quad(0)" SLOW; NET "quad(1)" SLOW; @@ -50,5 +55,5 @@ NET "quad(10)" SLOW; NET "quad(11)" SLOW; NET "psync" SLOW; NET "csync" SLOW; -NET "LED1" SLOW; -NET "LED2" SLOW; +NET "LED" SLOW; +NET "SWout" SLOW; diff --git a/vhdl/RGBtoHDMI.vhdl b/vhdl/RGBtoHDMI.vhdl index a8ac496f..faf5802f 100644 --- a/vhdl/RGBtoHDMI.vhdl +++ b/vhdl/RGBtoHDMI.vhdl @@ -16,14 +16,18 @@ use ieee.numeric_std.all; entity RGBtoHDMI is Port ( -- From Beeb RGB Connector - R: in std_logic; - G: in std_logic; - B: in std_logic; + R0: in std_logic; + G0: in std_logic; + B0: in std_logic; + R1: in std_logic; + G1: in std_logic; + B1: in std_logic; S: in std_logic; -- From Pi clk: in std_logic; mode7: in std_logic; + elk: in std_logic; sp_clk: in std_logic; sp_data: in std_logic; @@ -33,11 +37,9 @@ entity RGBtoHDMI is csync: out std_logic; SWout: out std_logic; - -- Test + -- User interface SW: in std_logic; - LED1: out std_logic; - LED2: out std_logic; - test: out std_logic + LED: out std_logic ); end RGBtoHDMI; @@ -71,9 +73,6 @@ architecture Behavorial of RGBtoHDMI is signal counter2 : unsigned(5 downto 3); - -- Hsync is every 64us - --signal led_counter : unsigned(12 downto 0); - -- Sample point register; -- -- In Modes 0..6 each pixel lasts 6 clocks (96MHz / 16MHz). The original @@ -99,17 +98,18 @@ architecture Behavorial of RGBtoHDMI is signal sp_index : std_logic_vector(2 downto 0); -- Sample pixel on next clock; pipelined to reducethe number of product terms - signal sample : std_logic; + signal sample : std_logic; + + signal R : std_logic; + signal G : std_logic; + signal B : std_logic; begin --- process(S) --- begin --- if rising_edge(S) then --- led_counter <= led_counter + 1; --- end if; --- end process; - + R <= R1 when elk = '1' else R0; + G <= G1 when elk = '1' else G0; + B <= B1 when elk = '1' else B0; + mode7_sp_A <= sp_reg(2 downto 0); mode7_sp_B <= sp_reg(5 downto 3); mode7_sp_C <= sp_reg(8 downto 6); @@ -212,14 +212,10 @@ begin end if; end process; - csync <= S; + csync <= CSYNC1; - LED1 <= mode7; - - --LED2 <= led_counter(led_counter'left); + LED <= mode7; SWOut <= SW; - - test <= sample; end Behavorial; diff --git a/vhdl/X b/vhdl/X new file mode 100644 index 00000000..4d3a7a51 --- /dev/null +++ b/vhdl/X @@ -0,0 +1,9 @@ +Function Mcells FB Inps Pterms IO +Block Used/Tot Used/Tot Used/Tot Used/Tot +FB1 16/18 33/54 62/90 6/ 9 +FB2 18/18* 25/54 34/90 5/ 9 +FB3 18/18* 35/54 61/90 8/ 9 +FB4 18/18* 37/54 58/90 4/ 7 + ----- ----- ----- ----- + 70/72 130/216 215/360 23/34 + diff --git a/vhdl/fitting.notes b/vhdl/fitting.notes new file mode 100644 index 00000000..b5b6b98c --- /dev/null +++ b/vhdl/fitting.notes @@ -0,0 +1,125 @@ +1. Original design: + +Function Mcells FB Inps Pterms IO +Block Used/Tot Used/Tot Used/Tot Used/Tot +FB1 18/18* 27/54 69/90 6/ 9 +FB2 18/18* 34/54 60/90 8/ 9 +FB3 18/18* 19/54 32/90 5/ 9 +FB4 18/18* 37/54 56/90 7/ 7* + ----- ----- ----- ----- + 72/72 117/216 217/360 26/34 + + +2. New design, with RGB mux, switch pass throughs, etc commented out +(failed to map sp_reg<9>, hence one less macrocell) + +Function Mcells FB Inps Pterms IO +Block Used/Tot Used/Tot Used/Tot Used/Tot +FB1 18/18* 26/54 51/90 7/ 9 +FB2 18/18* 25/54 33/90 6/ 9 +FB3 18/18* 35/54 61/90 8/ 9 +FB4 17/18 53/54 70/90 4/ 7 + ----- ----- ----- ----- + 71/72 139/216 215/360 25/34 + + +3. Change from csync=>S to csync=>CSYNC1 (as passthroughs still use up a macro cell). +(now fits) + +Function Mcells FB Inps Pterms IO +Block Used/Tot Used/Tot Used/Tot Used/Tot +FB1 17/18 33/54 64/90 7/ 9 +FB2 18/18* 25/54 33/90 6/ 9 +FB3 18/18* 35/54 61/90 8/ 9 +FB4 18/18* 37/54 58/90 4/ 7 + ----- ----- ----- ----- + 71/72 130/216 216/360 25/34 + + +4. Add in RGB mux: +(still fits) + +Function Mcells FB Inps Pterms IO +Block Used/Tot Used/Tot Used/Tot Used/Tot +FB1 17/18 33/54 64/90 7/ 9 +FB2 18/18* 25/54 33/90 9/ 9* +FB3 18/18* 37/54 61/90 8/ 9 +FB4 18/18* 41/54 61/90 5/ 7 + ----- ----- ----- ----- + 71/72 136/216 219/360 29/34 + +5. Add in SW2out <= SW2: +(still fits) + +Function Mcells FB Inps Pterms IO +Block Used/Tot Used/Tot Used/Tot Used/Tot +FB1 18/18* 28/54 62/90 8/ 9 +FB2 18/18* 25/54 33/90 9/ 9* +FB3 18/18* 37/54 61/90 8/ 9 +FB4 18/18* 48/54 64/90 6/ 7 + ----- ----- ----- ----- + 72/72 138/216 220/360 31/34 + +6. Change to optimization effort normal->high: +(no difference) + +Function Mcells FB Inps Pterms IO +Block Used/Tot Used/Tot Used/Tot Used/Tot +FB1 18/18* 28/54 62/90 8/ 9 +FB2 18/18* 25/54 33/90 9/ 9* +FB3 18/18* 37/54 61/90 8/ 9 +FB4 18/18* 48/54 64/90 6/ 7 + ----- ----- ----- ----- + 72/72 138/216 220/360 31/34 + +7. Change to optimization effort speed->area: +(no difference) + +Function Mcells FB Inps Pterms IO +Block Used/Tot Used/Tot Used/Tot Used/Tot +FB1 18/18* 28/54 62/90 8/ 9 +FB2 18/18* 25/54 33/90 9/ 9* +FB3 18/18* 37/54 61/90 8/ 9 +FB4 18/18* 48/54 64/90 6/ 7 + ----- ----- ----- ----- + 72/72 138/216 220/360 31/34 + +8. Fitter Implmenetation Template: Optimize Balance-> Optimize Speed: +(no difference) + +Function Mcells FB Inps Pterms IO +Block Used/Tot Used/Tot Used/Tot Used/Tot +FB1 18/18* 28/54 62/90 8/ 9 +FB2 18/18* 25/54 33/90 9/ 9* +FB3 18/18* 37/54 61/90 8/ 9 +FB4 18/18* 48/54 64/90 6/ 7 + ----- ----- ----- ----- + 72/72 138/216 220/360 31/34 + + +9. Fitter Implmenetation Template: Optimize Speed -> Optimize Density: +(no difference) + +Function Mcells FB Inps Pterms IO +Block Used/Tot Used/Tot Used/Tot Used/Tot +FB1 18/18* 28/54 62/90 8/ 9 +FB2 18/18* 25/54 33/90 9/ 9* +FB3 18/18* 37/54 61/90 8/ 9 +FB4 18/18* 48/54 64/90 6/ 7 + ----- ----- ----- ----- + 72/72 138/216 220/360 31/34 + +10. Reverted to original .xise file +Cleaned up design to remove SW2/3 pass throughs +Used gpio22/23 for mode7 / sp_data +Used gpio19/26 for sw2/3 (not via cpld) +(same result as 4 above) + +Function Mcells FB Inps Pterms IO +Block Used/Tot Used/Tot Used/Tot Used/Tot +FB1 17/18 33/54 64/90 5/ 9 +FB2 18/18* 25/54 33/90 9/ 9* +FB3 18/18* 37/54 61/90 8/ 9 +FB4 18/18* 41/54 61/90 7/ 7* + ----- ----- ----- ----- + 71/72 136/216 219/360 29/34