kopia lustrzana https://github.com/hoglet67/RGBtoHDMI
vhdl_YUV: rework design: 63 -> 57 macro cells (v5.A)
Change-Id: Idbcdaf7363d0f705a024d91571c102b34b7b9b5cyuv_cpld_61
David Banks
rodzic
554bdcca5b
commit
637aaad1cb
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@ -49,7 +49,7 @@ architecture Behavorial of RGBtoHDMI is
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-- Version number: Design_Major_Minor
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-- Design: 0 = Normal CPLD, 1 = Alternative CPLD, 2=Atom CPLD, 3=YUV6847 CPLD
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constant VERSION_NUM : std_logic_vector(11 downto 0) := x"359";
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constant VERSION_NUM : std_logic_vector(11 downto 0) := x"35A";
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-- Default offset to start sampling at when using the leading edge of sync
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constant leading_offset : unsigned(9 downto 0) := to_unsigned(1024 - 512, 10);
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@ -66,8 +66,6 @@ architecture Behavorial of RGBtoHDMI is
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-- Sampling points
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constant INIT_SAMPLING_POINTS : std_logic_vector(8 downto 0) := "000110000";
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signal colour1 : std_logic_vector(5 downto 0);
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signal colour2 : std_logic_vector(5 downto 0);
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-- The sampling counter runs at 8x pixel clock of 7.15909MHz = 56.272720MHz
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--
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@ -110,6 +108,13 @@ architecture Behavorial of RGBtoHDMI is
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signal LL2 : std_logic;
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signal LH2 : std_logic;
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signal AL_next : std_logic;
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signal AH_next : std_logic;
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signal BL_next : std_logic;
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signal BH_next : std_logic;
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signal LL_next : std_logic;
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signal LH_next : std_logic;
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signal AL : std_logic;
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signal AH : std_logic;
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signal BL : std_logic;
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@ -151,12 +156,46 @@ begin
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end process;
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-- Combine the YUV bits into a 6-bin colour value (combinatorial logic)
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process(AL, AH, BL, BH, LL, LH, inv_R)
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process(AL1, AL2, AL_I,
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AH1, AH2, AH_I,
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BL1, BL2, BL_I,
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BH1, BH2, BH_I,
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LL1, LL2, LL_S,
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LH1, LH2, LH_S,
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filter_C,
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filter_L,
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inv_R
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)
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variable tmp_AL : std_logic;
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variable tmp_AH : std_logic;
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begin
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if inv_R = '1' and AH = AL then
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colour1 <= BL & LL & not(AL) & BH & LH & not(AH);
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if filter_C = '1' then
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tmp_AL := (AL1 AND AL2) OR (AL1 AND AL_I) OR (AL2 AND AL_I);
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tmp_AH := (AH1 AND AH2) OR (AH1 AND AH_I) OR (AH2 AND AH_I);
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else
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colour1 <= BL & LL & AL & BH & LH & AH;
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tmp_AL := AL1;
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tmp_AH := AH1;
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end if;
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if filter_C = '1' then
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BL_next <= (BL1 AND BL2) OR (BL1 AND BL_I) OR (BL2 AND BL_I);
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BH_next <= (BH1 AND BH2) OR (BH1 AND BH_I) OR (BH2 AND BH_I);
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else
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BL_next <= BL1;
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BH_next <= BH1;
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end if;
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if filter_L = '1' then
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LL_next <= (LL1 AND LL2) OR (LL1 AND LL_S) OR (LL2 AND LL_S);
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LH_next <= (LH1 AND LH2) OR (LH1 AND LH_S) OR (LH2 AND LH_S);
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else
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LL_next <= LL1;
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LH_next <= LH1;
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end if;
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if inv_R = '1' and tmp_AH = tmp_AL then
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AL_next <= not tmp_AL;
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AH_next <= not tmp_AH;
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else
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AL_next <= tmp_AL;
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AH_next <= tmp_AH;
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end if;
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end process;
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@ -223,28 +262,16 @@ begin
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-- sample colour signal
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if (subsam_C = '0' and counter(2 downto 0) = "000") or
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(subsam_C = '1' and counter(3 downto 0) = "0100") then
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if filter_C = '1' then
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AL <= (AL1 AND AL2) OR (AL1 AND AL_I) OR (AL2 AND AL_I);
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AH <= (AH1 AND AH2) OR (AH1 AND AH_I) OR (AH2 AND AH_I);
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BL <= (BL1 AND BL2) OR (BL1 AND BL_I) OR (BL2 AND BL_I);
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BH <= (BH1 AND BH2) OR (BH1 AND BH_I) OR (BH2 AND BH_I);
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else
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AL <= AL1;
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AH <= AH1;
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BL <= BL1;
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BH <= BH1;
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end if;
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AL <= AL_next;
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AH <= AH_next;
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BL <= BL_next;
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BH <= BH_next;
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end if;
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-- sample luminance signal
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if counter(2 downto 0) = "000" then
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if filter_L = '1' then
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LL <= (LL1 AND LL2) OR (LL1 AND LL_S) OR (LL2 AND LL_S);
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LH <= (LH1 AND LH2) OR (LH1 AND LH_S) OR (LH2 AND LH_S);
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else
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LL <= LL1;
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LH <= LH1;
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end if;
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LL <= LL_next;
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LH <= LH_next;
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end if;
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-- TODO - if more space needed
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@ -255,7 +282,7 @@ begin
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--
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-- 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0
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-- L Sample L0 L1 L2 L3
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-- C Sample C0 C2
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-- C Sample CA CB
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-- Quad L0/CA/L1 L2/CB/L3
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--
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@ -263,12 +290,9 @@ begin
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quad <= VERSION_NUM;
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psync <= FS_I;
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elsif counter(counter'left) = '0' then
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if counter(2 downto 0) = "000" then
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colour2 <= colour1;
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end if;
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if counter(3 downto 0) = "0000" then
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quad(11 downto 6) <= colour1;
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quad( 5 downto 0) <= colour2;
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quad(11 downto 6) <= BL_next & LL_next & AL_next & BH_next & LH_next & AH_next;
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quad( 5 downto 0) <= BL & LL & AL & BH & LH & AH;
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end if;
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if counter(3 downto 0) = "0010" then
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psync <= counter(4);
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Plik binarny nie jest wyświetlany.
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@ -1,175 +1,32 @@
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1. Atom CPLD: Initial version for home-etched prototype
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vhdl_YUV: fix hang when sync threshold too low (v5.8)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 30/54 49/90 8/ 9
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FB2 17/18 26/54 38/90 4/ 9
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FB3 18/18* 30/54 69/90 8/ 9
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FB4 18/18* 32/54 48/90 7/ 7*
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FB1 18/18* 30/54 47/90 6/ 9
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FB2 17/18 26/54 35/90 8/ 9
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FB3 18/18* 32/54 70/90 9/ 9*
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FB4 18/18* 37/54 65/90 6/ 7
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----- ----- ----- -----
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71/72 118/216 204/360 27/34
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71/72 125/216 217/360 29/34
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2. Atom CPLD: Reworked for a 57.272MHz clock
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vhdl_YUV: rework design: 71 -> 63 macro cells (v5.9)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 26/54 48/90 8/ 9
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FB2 14/18 23/54 31/90 4/ 9
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FB3 18/18* 30/54 61/90 8/ 9
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FB4 18/18* 29/54 45/90 7/ 7*
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FB1 16/18 33/54 63/90 6/ 9
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FB2 12/18 20/54 25/90 8/ 9
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FB3 18/18* 28/54 63/90 9/ 9*
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FB4 17/18 36/54 75/90 6/ 7
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----- ----- ----- -----
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68/72 108/216 185/360 27/34
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63/72 117/216 226/360 29/34
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3. Atom CPLD: Shave two bits of the counter
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vhdl_YUV: rework design: 63 -> 57 macro cells (v5.A)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 30/54 49/90 8/ 9
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FB2 12/18 22/54 27/90 4/ 9
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FB3 18/18* 28/54 60/90 8/ 9
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FB4 18/18* 30/54 44/90 7/ 7*
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FB1 12/18 33/54 83/90 6/ 9
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FB2 17/18 27/54 32/90 8/ 9
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FB3 10/18 33/54 81/90 9/ 9*
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FB4 18/18* 33/54 71/90 6/ 7
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----- ----- ----- -----
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66/72 110/216 180/360 27/34
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4. Atom CPLD: Added back in glitch filtering
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 30/54 58/90 8/ 9
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FB2 12/18 24/54 39/90 4/ 9
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FB3 18/18* 27/54 60/90 8/ 9
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FB4 18/18* 31/54 83/90 7/ 7*
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----- ----- ----- -----
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66/72 112/216 240/360 27/34
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5. Atom CPLD: Generate CSYNC from HS_N and FS_N
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 30/54 58/90 8/ 9
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FB2 13/18 25/54 40/90 4/ 9
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FB3 18/18* 29/54 63/90 8/ 9
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FB4 18/18* 31/54 83/90 7/ 7*
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----- ----- ----- -----
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67/72 115/216 244/360 27/34
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6. Atom CPLD: Increase Offset to 4 bits
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 29/54 52/90 8/ 9
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FB2 15/18 30/54 41/90 4/ 9
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FB3 18/18* 30/54 69/90 8/ 9
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FB4 18/18* 30/54 72/90 7/ 7*
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----- ----- ----- -----
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69/72 119/216 234/360 27/34
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7. Atom CPLD: Clock pixel pipeline every cycle
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 28/54 53/90 8/ 9
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FB2 15/18 25/54 28/90 4/ 9
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FB3 18/18* 30/54 69/90 8/ 9
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FB4 18/18* 28/54 39/90 7/ 7*
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----- ----- ----- -----
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69/72 111/216 189/360 27/34
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8. Atom CPLD: Send two 4-bit pixels per psync edge
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 27/54 46/90 8/ 9
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FB2 11/18 20/54 21/90 4/ 9
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FB3 18/18* 28/54 63/90 8/ 9
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FB4 18/18* 27/54 36/90 7/ 7*
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----- ----- ----- -----
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65/72 102/216 166/360 27/34
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9. Atom CPLD: Discriminate normal and bright orange
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 28/54 46/90 8/ 9
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FB2 15/18 24/54 25/90 5/ 9
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FB3 18/18* 28/54 63/90 8/ 9
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FB4 18/18* 29/54 39/90 7/ 7*
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----- ----- ----- -----
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69/72 109/216 173/360 28/34
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10. Atom CPLD: Discriminate dark green/dark orange text background
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 28/54 48/90 8/ 9
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FB2 15/18 24/54 25/90 5/ 9
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FB3 18/18* 28/54 63/90 8/ 9
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FB4 18/18* 29/54 39/90 7/ 7*
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----- ----- ----- -----
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69/72 109/216 175/360 28/34
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10. Atom CPLD: Made C/L noise filters configurable
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 29/54 49/90 8/ 9
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FB2 17/18 26/54 29/90 5/ 9
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FB3 18/18* 28/54 63/90 8/ 9
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FB4 18/18* 31/54 44/90 7/ 7*
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----- ----- ----- -----
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71/72 114/216 185/360 28/34
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11. Atom CPLD: Added two cycles of skew to PSYNC
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 29/54 49/90 8/ 9
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FB2 17/18 26/54 29/90 5/ 9
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FB3 18/18* 28/54 63/90 8/ 9
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FB4 18/18* 31/54 44/90 7/ 7*
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----- ----- ----- -----
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71/72 114/216 185/360 28/34
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13. Atom CPLD: Use sixbit pixels, with a new mapping of colours
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 32/54 59/90 8/ 9
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FB2 17/18 26/54 29/90 5/ 9
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FB3 18/18* 32/54 76/90 8/ 9
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FB4 18/18* 33/54 45/90 7/ 7*
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----- ----- ----- -----
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71/72 123/216 209/360 28/34
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14. Atom CPLD: Changed .ucf file for PCB v2
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 33/54 63/90 9/ 9*
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FB2 18/18* 35/54 47/90 7/ 9
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FB3 18/18* 32/54 76/90 9/ 9*
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FB4 17/18 18/54 23/90 3/ 7
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----- ----- ----- -----
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71/72 118/216 209/360 28/34
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15. Atom CPLD: Adjust start offset by one pixel to allow perfect centering (now v2.3)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 33/54 63/90 9/ 9*
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FB2 18/18* 35/54 47/90 7/ 9
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FB3 18/18* 32/54 77/90 9/ 9*
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FB4 17/18 18/54 23/90 3/ 7
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----- ----- ----- -----
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71/72 118/216 210/360 28/34
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16. Atom CPLD: Adjust colour sampling point (now v2.4)
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Function Mcells FB Inps Pterms IO
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Block Used/Tot Used/Tot Used/Tot Used/Tot
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FB1 18/18* 33/54 63/90 9/ 9*
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FB2 18/18* 35/54 47/90 7/ 9
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FB3 18/18* 32/54 75/90 9/ 9*
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FB4 17/18 18/54 23/90 3/ 7
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----- ----- ----- -----
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71/72 118/216 208/360 28/34
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57/72 126/216 267/360 29/34
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