diff --git a/vhdl_YUV_6bit/RGBtoHDMI.vhdl b/vhdl_YUV_6bit/RGBtoHDMI.vhdl index ae4cab45..d65b4166 100644 --- a/vhdl_YUV_6bit/RGBtoHDMI.vhdl +++ b/vhdl_YUV_6bit/RGBtoHDMI.vhdl @@ -49,7 +49,7 @@ architecture Behavorial of RGBtoHDMI is -- Version number: Design_Major_Minor -- Design: 0 = Normal CPLD, 1 = Alternative CPLD, 2=Atom CPLD, 3=YUV6847 CPLD - constant VERSION_NUM : std_logic_vector(11 downto 0) := x"359"; + constant VERSION_NUM : std_logic_vector(11 downto 0) := x"35A"; -- Default offset to start sampling at when using the leading edge of sync constant leading_offset : unsigned(9 downto 0) := to_unsigned(1024 - 512, 10); @@ -66,8 +66,6 @@ architecture Behavorial of RGBtoHDMI is -- Sampling points constant INIT_SAMPLING_POINTS : std_logic_vector(8 downto 0) := "000110000"; - signal colour1 : std_logic_vector(5 downto 0); - signal colour2 : std_logic_vector(5 downto 0); -- The sampling counter runs at 8x pixel clock of 7.15909MHz = 56.272720MHz -- @@ -110,6 +108,13 @@ architecture Behavorial of RGBtoHDMI is signal LL2 : std_logic; signal LH2 : std_logic; + signal AL_next : std_logic; + signal AH_next : std_logic; + signal BL_next : std_logic; + signal BH_next : std_logic; + signal LL_next : std_logic; + signal LH_next : std_logic; + signal AL : std_logic; signal AH : std_logic; signal BL : std_logic; @@ -151,12 +156,46 @@ begin end process; -- Combine the YUV bits into a 6-bin colour value (combinatorial logic) - process(AL, AH, BL, BH, LL, LH, inv_R) + process(AL1, AL2, AL_I, + AH1, AH2, AH_I, + BL1, BL2, BL_I, + BH1, BH2, BH_I, + LL1, LL2, LL_S, + LH1, LH2, LH_S, + filter_C, + filter_L, + inv_R + ) + variable tmp_AL : std_logic; + variable tmp_AH : std_logic; begin - if inv_R = '1' and AH = AL then - colour1 <= BL & LL & not(AL) & BH & LH & not(AH); + if filter_C = '1' then + tmp_AL := (AL1 AND AL2) OR (AL1 AND AL_I) OR (AL2 AND AL_I); + tmp_AH := (AH1 AND AH2) OR (AH1 AND AH_I) OR (AH2 AND AH_I); else - colour1 <= BL & LL & AL & BH & LH & AH; + tmp_AL := AL1; + tmp_AH := AH1; + end if; + if filter_C = '1' then + BL_next <= (BL1 AND BL2) OR (BL1 AND BL_I) OR (BL2 AND BL_I); + BH_next <= (BH1 AND BH2) OR (BH1 AND BH_I) OR (BH2 AND BH_I); + else + BL_next <= BL1; + BH_next <= BH1; + end if; + if filter_L = '1' then + LL_next <= (LL1 AND LL2) OR (LL1 AND LL_S) OR (LL2 AND LL_S); + LH_next <= (LH1 AND LH2) OR (LH1 AND LH_S) OR (LH2 AND LH_S); + else + LL_next <= LL1; + LH_next <= LH1; + end if; + if inv_R = '1' and tmp_AH = tmp_AL then + AL_next <= not tmp_AL; + AH_next <= not tmp_AH; + else + AL_next <= tmp_AL; + AH_next <= tmp_AH; end if; end process; @@ -223,28 +262,16 @@ begin -- sample colour signal if (subsam_C = '0' and counter(2 downto 0) = "000") or (subsam_C = '1' and counter(3 downto 0) = "0100") then - if filter_C = '1' then - AL <= (AL1 AND AL2) OR (AL1 AND AL_I) OR (AL2 AND AL_I); - AH <= (AH1 AND AH2) OR (AH1 AND AH_I) OR (AH2 AND AH_I); - BL <= (BL1 AND BL2) OR (BL1 AND BL_I) OR (BL2 AND BL_I); - BH <= (BH1 AND BH2) OR (BH1 AND BH_I) OR (BH2 AND BH_I); - else - AL <= AL1; - AH <= AH1; - BL <= BL1; - BH <= BH1; - end if; + AL <= AL_next; + AH <= AH_next; + BL <= BL_next; + BH <= BH_next; end if; -- sample luminance signal if counter(2 downto 0) = "000" then - if filter_L = '1' then - LL <= (LL1 AND LL2) OR (LL1 AND LL_S) OR (LL2 AND LL_S); - LH <= (LH1 AND LH2) OR (LH1 AND LH_S) OR (LH2 AND LH_S); - else - LL <= LL1; - LH <= LH1; - end if; + LL <= LL_next; + LH <= LH_next; end if; -- TODO - if more space needed @@ -255,7 +282,7 @@ begin -- -- 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 -- L Sample L0 L1 L2 L3 - -- C Sample C0 C2 + -- C Sample CA CB -- Quad L0/CA/L1 L2/CB/L3 -- @@ -263,12 +290,9 @@ begin quad <= VERSION_NUM; psync <= FS_I; elsif counter(counter'left) = '0' then - if counter(2 downto 0) = "000" then - colour2 <= colour1; - end if; if counter(3 downto 0) = "0000" then - quad(11 downto 6) <= colour1; - quad( 5 downto 0) <= colour2; + quad(11 downto 6) <= BL_next & LL_next & AL_next & BH_next & LH_next & AH_next; + quad( 5 downto 0) <= BL & LL & AL & BH & LH & AH; end if; if counter(3 downto 0) = "0010" then psync <= counter(4); diff --git a/vhdl_YUV_6bit/YUV_CPLD_v5A.xsvf b/vhdl_YUV_6bit/YUV_CPLD_v5A.xsvf new file mode 100644 index 00000000..df2fdcdf Binary files /dev/null and b/vhdl_YUV_6bit/YUV_CPLD_v5A.xsvf differ diff --git a/vhdl_YUV_6bit/fitting.notes b/vhdl_YUV_6bit/fitting.notes index 3cac220e..6c9d5f45 100644 --- a/vhdl_YUV_6bit/fitting.notes +++ b/vhdl_YUV_6bit/fitting.notes @@ -1,175 +1,32 @@ -1. Atom CPLD: Initial version for home-etched prototype +vhdl_YUV: fix hang when sync threshold too low (v5.8) Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot -FB1 18/18* 30/54 49/90 8/ 9 -FB2 17/18 26/54 38/90 4/ 9 -FB3 18/18* 30/54 69/90 8/ 9 -FB4 18/18* 32/54 48/90 7/ 7* +FB1 18/18* 30/54 47/90 6/ 9 +FB2 17/18 26/54 35/90 8/ 9 +FB3 18/18* 32/54 70/90 9/ 9* +FB4 18/18* 37/54 65/90 6/ 7 ----- ----- ----- ----- - 71/72 118/216 204/360 27/34 + 71/72 125/216 217/360 29/34 -2. Atom CPLD: Reworked for a 57.272MHz clock +vhdl_YUV: rework design: 71 -> 63 macro cells (v5.9) Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot -FB1 18/18* 26/54 48/90 8/ 9 -FB2 14/18 23/54 31/90 4/ 9 -FB3 18/18* 30/54 61/90 8/ 9 -FB4 18/18* 29/54 45/90 7/ 7* +FB1 16/18 33/54 63/90 6/ 9 +FB2 12/18 20/54 25/90 8/ 9 +FB3 18/18* 28/54 63/90 9/ 9* +FB4 17/18 36/54 75/90 6/ 7 ----- ----- ----- ----- - 68/72 108/216 185/360 27/34 + 63/72 117/216 226/360 29/34 -3. Atom CPLD: Shave two bits of the counter +vhdl_YUV: rework design: 63 -> 57 macro cells (v5.A) Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot -FB1 18/18* 30/54 49/90 8/ 9 -FB2 12/18 22/54 27/90 4/ 9 -FB3 18/18* 28/54 60/90 8/ 9 -FB4 18/18* 30/54 44/90 7/ 7* +FB1 12/18 33/54 83/90 6/ 9 +FB2 17/18 27/54 32/90 8/ 9 +FB3 10/18 33/54 81/90 9/ 9* +FB4 18/18* 33/54 71/90 6/ 7 ----- ----- ----- ----- - 66/72 110/216 180/360 27/34 - -4. Atom CPLD: Added back in glitch filtering - -Function Mcells FB Inps Pterms IO -Block Used/Tot Used/Tot Used/Tot Used/Tot -FB1 18/18* 30/54 58/90 8/ 9 -FB2 12/18 24/54 39/90 4/ 9 -FB3 18/18* 27/54 60/90 8/ 9 -FB4 18/18* 31/54 83/90 7/ 7* - ----- ----- ----- ----- - 66/72 112/216 240/360 27/34 - -5. Atom CPLD: Generate CSYNC from HS_N and FS_N - -Function Mcells FB Inps Pterms IO -Block Used/Tot Used/Tot Used/Tot Used/Tot -FB1 18/18* 30/54 58/90 8/ 9 -FB2 13/18 25/54 40/90 4/ 9 -FB3 18/18* 29/54 63/90 8/ 9 -FB4 18/18* 31/54 83/90 7/ 7* - ----- ----- ----- ----- - 67/72 115/216 244/360 27/34 - -6. Atom CPLD: Increase Offset to 4 bits - -Function Mcells FB Inps Pterms IO -Block Used/Tot Used/Tot Used/Tot Used/Tot -FB1 18/18* 29/54 52/90 8/ 9 -FB2 15/18 30/54 41/90 4/ 9 -FB3 18/18* 30/54 69/90 8/ 9 -FB4 18/18* 30/54 72/90 7/ 7* - ----- ----- ----- ----- - 69/72 119/216 234/360 27/34 - -7. Atom CPLD: Clock pixel pipeline every cycle - -Function Mcells FB Inps Pterms IO -Block Used/Tot Used/Tot Used/Tot Used/Tot -FB1 18/18* 28/54 53/90 8/ 9 -FB2 15/18 25/54 28/90 4/ 9 -FB3 18/18* 30/54 69/90 8/ 9 -FB4 18/18* 28/54 39/90 7/ 7* - ----- ----- ----- ----- - 69/72 111/216 189/360 27/34 - -8. Atom CPLD: Send two 4-bit pixels per psync edge - -Function Mcells FB Inps Pterms IO -Block Used/Tot Used/Tot Used/Tot Used/Tot -FB1 18/18* 27/54 46/90 8/ 9 -FB2 11/18 20/54 21/90 4/ 9 -FB3 18/18* 28/54 63/90 8/ 9 -FB4 18/18* 27/54 36/90 7/ 7* - ----- ----- ----- ----- - 65/72 102/216 166/360 27/34 - -9. Atom CPLD: Discriminate normal and bright orange - -Function Mcells FB Inps Pterms IO -Block Used/Tot Used/Tot Used/Tot Used/Tot -FB1 18/18* 28/54 46/90 8/ 9 -FB2 15/18 24/54 25/90 5/ 9 -FB3 18/18* 28/54 63/90 8/ 9 -FB4 18/18* 29/54 39/90 7/ 7* - ----- ----- ----- ----- - 69/72 109/216 173/360 28/34 - -10. Atom CPLD: Discriminate dark green/dark orange text background - -Function Mcells FB Inps Pterms IO -Block Used/Tot Used/Tot Used/Tot Used/Tot -FB1 18/18* 28/54 48/90 8/ 9 -FB2 15/18 24/54 25/90 5/ 9 -FB3 18/18* 28/54 63/90 8/ 9 -FB4 18/18* 29/54 39/90 7/ 7* - ----- ----- ----- ----- - 69/72 109/216 175/360 28/34 - -10. Atom CPLD: Made C/L noise filters configurable - -Function Mcells FB Inps Pterms IO -Block Used/Tot Used/Tot Used/Tot Used/Tot -FB1 18/18* 29/54 49/90 8/ 9 -FB2 17/18 26/54 29/90 5/ 9 -FB3 18/18* 28/54 63/90 8/ 9 -FB4 18/18* 31/54 44/90 7/ 7* - ----- ----- ----- ----- - 71/72 114/216 185/360 28/34 - -11. Atom CPLD: Added two cycles of skew to PSYNC - -Function Mcells FB Inps Pterms IO -Block Used/Tot Used/Tot Used/Tot Used/Tot -FB1 18/18* 29/54 49/90 8/ 9 -FB2 17/18 26/54 29/90 5/ 9 -FB3 18/18* 28/54 63/90 8/ 9 -FB4 18/18* 31/54 44/90 7/ 7* - ----- ----- ----- ----- - 71/72 114/216 185/360 28/34 - -13. Atom CPLD: Use sixbit pixels, with a new mapping of colours - -Function Mcells FB Inps Pterms IO -Block Used/Tot Used/Tot Used/Tot Used/Tot -FB1 18/18* 32/54 59/90 8/ 9 -FB2 17/18 26/54 29/90 5/ 9 -FB3 18/18* 32/54 76/90 8/ 9 -FB4 18/18* 33/54 45/90 7/ 7* - ----- ----- ----- ----- - 71/72 123/216 209/360 28/34 - -14. Atom CPLD: Changed .ucf file for PCB v2 - -Function Mcells FB Inps Pterms IO -Block Used/Tot Used/Tot Used/Tot Used/Tot -FB1 18/18* 33/54 63/90 9/ 9* -FB2 18/18* 35/54 47/90 7/ 9 -FB3 18/18* 32/54 76/90 9/ 9* -FB4 17/18 18/54 23/90 3/ 7 - ----- ----- ----- ----- - 71/72 118/216 209/360 28/34 - -15. Atom CPLD: Adjust start offset by one pixel to allow perfect centering (now v2.3) - -Function Mcells FB Inps Pterms IO -Block Used/Tot Used/Tot Used/Tot Used/Tot -FB1 18/18* 33/54 63/90 9/ 9* -FB2 18/18* 35/54 47/90 7/ 9 -FB3 18/18* 32/54 77/90 9/ 9* -FB4 17/18 18/54 23/90 3/ 7 - ----- ----- ----- ----- - 71/72 118/216 210/360 28/34 - -16. Atom CPLD: Adjust colour sampling point (now v2.4) - -Function Mcells FB Inps Pterms IO -Block Used/Tot Used/Tot Used/Tot Used/Tot -FB1 18/18* 33/54 63/90 9/ 9* -FB2 18/18* 35/54 47/90 7/ 9 -FB3 18/18* 32/54 75/90 9/ 9* -FB4 17/18 18/54 23/90 3/ 7 - ----- ----- ----- ----- - 71/72 118/216 208/360 28/34 + 57/72 126/216 267/360 29/34