kopia lustrzana https://github.com/OpenRTX/OpenRTX
255 wiersze
13 KiB
C
255 wiersze
13 KiB
C
/*
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*********************************************************************************************************
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* uC/CPU
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* CPU CONFIGURATION & PORT LAYER
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*
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* Copyright 2004-2020 Silicon Laboratories Inc. www.silabs.com
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*
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* SPDX-License-Identifier: APACHE-2.0
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*
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* This software is subject to an open source license and is distributed by
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* Silicon Laboratories Inc. pursuant to the terms of the Apache License,
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* Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
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*
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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*
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* CPU CONFIGURATION FILE
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*
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* TEMPLATE
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*
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* Filename : cpu_cfg.h
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* Version : v1.32.00
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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* MODULE
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*********************************************************************************************************
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*/
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#ifndef CPU_CFG_MODULE_PRESENT
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#define CPU_CFG_MODULE_PRESENT
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/*
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*********************************************************************************************************
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* CPU NAME CONFIGURATION
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*
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* Note(s) : (1) Configure CPU_CFG_NAME_EN to enable/disable CPU host name feature :
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*
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* (a) CPU host name storage
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* (b) CPU host name API functions
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*
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* (2) Configure CPU_CFG_NAME_SIZE with the desired ASCII string size of the CPU host name,
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* including the terminating NULL character.
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*
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* See also 'cpu_core.h GLOBAL VARIABLES Note #1'.
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*********************************************************************************************************
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*/
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/* Configure CPU host name feature (see Note #1) : */
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#define CPU_CFG_NAME_EN DEF_DISABLED
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/* DEF_DISABLED CPU host name DISABLED */
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/* DEF_ENABLED CPU host name ENABLED */
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/* Configure CPU host name ASCII string size ... */
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#define CPU_CFG_NAME_SIZE 16 /* ... (see Note #2). */
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/*
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*********************************************************************************************************
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* CPU TIMESTAMP CONFIGURATION
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*
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* Note(s) : (1) Configure CPU_CFG_TS_xx_EN to enable/disable CPU timestamp features :
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*
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* (a) CPU_CFG_TS_32_EN enable/disable 32-bit CPU timestamp feature
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* (b) CPU_CFG_TS_64_EN enable/disable 64-bit CPU timestamp feature
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*
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* (2) (a) Configure CPU_CFG_TS_TMR_SIZE with the CPU timestamp timer's word size :
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*
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* CPU_WORD_SIZE_08 8-bit word size
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* CPU_WORD_SIZE_16 16-bit word size
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* CPU_WORD_SIZE_32 32-bit word size
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* CPU_WORD_SIZE_64 64-bit word size
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*
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* (b) If the size of the CPU timestamp timer is not a binary multiple of 8-bit octets
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* (e.g. 20-bits or even 24-bits), then the next lower, binary-multiple octet word
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* size SHOULD be configured (e.g. to 16-bits). However, the minimum supported word
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* size for CPU timestamp timers is 8-bits.
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*
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* See also 'cpu_core.h FUNCTION PROTOTYPES CPU_TS_TmrRd() Note #2a'.
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*********************************************************************************************************
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*/
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/* Configure CPU timestamp features (see Note #1) : */
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#define CPU_CFG_TS_32_EN DEF_DISABLED
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#define CPU_CFG_TS_64_EN DEF_DISABLED
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/* DEF_DISABLED CPU timestamps DISABLED */
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/* DEF_ENABLED CPU timestamps ENABLED */
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/* Configure CPU timestamp timer word size ... */
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/* ... (see Note #2) : */
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#define CPU_CFG_TS_TMR_SIZE CPU_WORD_SIZE_32
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/*
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*********************************************************************************************************
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* CPU INTERRUPTS DISABLED TIME MEASUREMENT CONFIGURATION
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*
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* Note(s) : (1) (a) Configure CPU_CFG_INT_DIS_MEAS_EN to enable/disable measuring CPU's interrupts
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* disabled time :
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*
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* (a) Enabled, if CPU_CFG_INT_DIS_MEAS_EN #define'd in 'cpu_cfg.h'
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*
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* (b) Disabled, if CPU_CFG_INT_DIS_MEAS_EN NOT #define'd in 'cpu_cfg.h'
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*
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* See also 'cpu_core.h FUNCTION PROTOTYPES Note #1'.
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*
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* (b) Configure CPU_CFG_INT_DIS_MEAS_OVRHD_NBR with the number of times to measure &
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* average the interrupts disabled time measurements overhead.
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*
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* See also 'cpu_core.c CPU_IntDisMeasInit() Note #3a'.
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*********************************************************************************************************
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*/
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#if 0 /* Configure CPU interrupts disabled time ... */
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#define CPU_CFG_INT_DIS_MEAS_EN /* ... measurements feature (see Note #1a). */
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#endif
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/* Configure number of interrupts disabled overhead ... */
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#define CPU_CFG_INT_DIS_MEAS_OVRHD_NBR 1u /* ... time measurements (see Note #1b). */
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/*
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*********************************************************************************************************
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* CPU COUNT ZEROS CONFIGURATION
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*
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* Note(s) : (1) (a) Configure CPU_CFG_LEAD_ZEROS_ASM_PRESENT to define count leading zeros bits
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* function(s) in :
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*
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* (1) 'cpu_a.asm', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT #define'd in 'cpu.h'/
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* 'cpu_cfg.h' to enable assembly-optimized function(s)
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*
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* (2) 'cpu_core.c', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT NOT #define'd in 'cpu.h'/
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* 'cpu_cfg.h' to enable C-source-optimized function(s) otherwise
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*
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* (b) Configure CPU_CFG_TRAIL_ZEROS_ASM_PRESENT to define count trailing zeros bits
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* function(s) in :
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*
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* (1) 'cpu_a.asm', if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT #define'd in 'cpu.h'/
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* 'cpu_cfg.h' to enable assembly-optimized function(s)
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*
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* (2) 'cpu_core.c', if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT NOT #define'd in 'cpu.h'/
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* 'cpu_cfg.h' to enable C-source-optimized function(s) otherwise
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*********************************************************************************************************
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*/
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#if 0 /* Configure CPU count leading zeros bits ... */
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#define CPU_CFG_LEAD_ZEROS_ASM_PRESENT /* ... assembly-version (see Note #1a). */
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#endif
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#if 0 /* Configure CPU count trailing zeros bits ... */
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#define CPU_CFG_TRAIL_ZEROS_ASM_PRESENT /* ... assembly-version (see Note #1b). */
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#endif
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/*
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*********************************************************************************************************
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* CPU ENDIAN TYPE OVERRIDE
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*
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* Note(s) : (1) Configure CPU_CFG_ENDIAN_TYPE to override the default CPU endian type defined in cpu.h.
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*
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* (a) CPU_ENDIAN_TYPE_BIG Big- endian word order (CPU words' most significant
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* octet @ lowest memory address)
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* (b) CPU_ENDIAN_TYPE_LITTLE Little-endian word order (CPU words' least significant
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* octet @ lowest memory address)
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*
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* (2) Defining CPU_CFG_ENDIAN_TYPE here is only valid for supported bi-endian architectures.
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* See 'cpu.h CPU WORD CONFIGURATION Note #3' for details
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*********************************************************************************************************
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*/
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// #if 0
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#define CPU_CFG_ENDIAN_TYPE CPU_ENDIAN_TYPE_LITTLE /* Defines CPU data word-memory order (see Note #2). */
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// #endif
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/*
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*********************************************************************************************************
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* CACHE MANAGEMENT
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*
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* Note(s) : (1) Configure CPU_CFG_CACHE_MGMT_EN to enable the cache management API.
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*
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* (2) This option only enables the cache management functions.
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* It does not enable any hardware caches, which should be configured in startup code.
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* Caches must be configured and enabled by the time CPU_Init() is called.
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*
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* (3) This option is usually required for device drivers which use a DMA engine to transmit
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* buffers that are located in cached memory.
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*********************************************************************************************************
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*/
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#define CPU_CFG_CACHE_MGMT_EN DEF_DISABLED /* Defines CPU data word-memory order (see Note #1). */
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/*
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*********************************************************************************************************
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* KERNEL AWARE IPL BOUNDARY
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*
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* Note(s) : (1) Determines the IPL level that establishes the boundary for ISRs that are kernel-aware and
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* those that are not. All ISRs at this level or lower are kernel-aware.
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*
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* (2) ARMv7-M: Since the port is using BASEPRI to separate kernel vs non-kernel aware ISR, please
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* make sure your external interrupt priorities are set accordingly. For example, if
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* CPU_CFG_KA_IPL_BOUNDARY is set to 4 then external interrupt priorities 4-15 will be kernel
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* aware while priorities 0-3 will be use as non-kernel aware.
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*********************************************************************************************************
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*/
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#define CPU_CFG_KA_IPL_BOUNDARY 4u
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/*
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*********************************************************************************************************
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* ARM CORTEX-M
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*
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* Note(s) : (1) Determines the interrupt programmable priority levels. This is normally specified in the
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* Microcontroller reference manual. 4-bits gives us 16 programmable priority levels.
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*
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* Example 1 Example 2
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* NVIC_IPRx NVIC_IPRx
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* 7 0 7 0
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* +------------------+ +------------------+
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* | PRIO | | PRIO |
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* +------------------+ +------------------+
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*
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* Bits[7:4] Priority mask bits Bits[7:6] Priority mask bits
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* Bits[3:0] Reserved Bits[5:0] Reserved
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*
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* Example 1: CPU_CFG_NVIC_PRIO_BITS should be set to 4 due to the processor
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* implementing only bits[7:4].
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*
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* Example 2: CPU_CFG_NVIC_PRIO_BITS should be set to 2 due to the processor
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* implementing only bits[7:6].
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*********************************************************************************************************
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*/
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// #if 0
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#define CPU_CFG_NVIC_PRIO_BITS 4u
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// #endif
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/*
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*********************************************************************************************************
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* MODULE END
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*********************************************************************************************************
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*/
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#endif /* End of CPU cfg module include. */
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